CN210897283U - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN210897283U CN210897283U CN201921777090.XU CN201921777090U CN210897283U CN 210897283 U CN210897283 U CN 210897283U CN 201921777090 U CN201921777090 U CN 201921777090U CN 210897283 U CN210897283 U CN 210897283U
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Abstract
The utility model discloses a semiconductor device relates to semiconductor technology field. The semiconductor device of the utility model comprises a substrate; a first portion disposed on the substrate, the first portion including a HEMT structure; a second portion disposed on the substrate laterally connecting the first portion, the second portion being coplanar with the first portion and being dielectrically insulated from each other, the second portion comprising a SIC MOSFET structure. The utility model discloses compare current semiconductor integrated device, have more high frequency, the characteristics of higher density.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor, especially, relate to a semiconductor device.
Background
With the development of high frequency and high power density of electronic power technology, the requirements of the switching power supply on the performance and reliability of power electronic devices are increasingly strict, and a novel semiconductor device needs to be developed to adapt to the application occasions of high frequency and high power density, so that the market demand is met.
Most of the existing semiconductor devices have the problems of high on-resistance and large leakage current, so that the semiconductor device with high frequency and high power density is difficult to obtain.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor device through the on-resistance who reduces the device, reduces the leakage current to obtain the semiconductor device that has more excellent performance.
In order to solve the technical problem, the utility model discloses a realize through following technical scheme:
the utility model provides a semiconductor device, it includes:
a first portion comprising:
a first substrate;
a first epitaxial layer disposed on the first substrate;
a passivation layer disposed on the epitaxial layer;
the first source electrode, the first grid electrode and the first drain electrode penetrate through the passivation layer and are connected with the epitaxial layer;
a first insulating layer disposed on the passivation layer and covering the first gate electrode and the first drain electrode and a portion of the first source electrode;
a second portion laterally connected with the first portion and coplanar with the first portion and dielectrically insulated from each other, the second portion comprising:
a silicon carbide substrate connected laterally side-by-side with the first substrate;
a P-type material region disposed on the silicon carbide substrate;
an N-type diffusion region disposed on the P-type material region;
a third insulating layer covering the P-type material region and the N-type diffusion region; the third insulating layer and the first insulating layer are the same in thickness and are arranged in a coplanar manner;
a second source and a second drain penetrating the third insulating layer and connected to the N-type diffusion region; the second source electrode is connected with the silicon carbide substrate;
a second gate disposed on the third insulating layer and between the second source and the second drain.
In one embodiment of the present invention, the first portion includes a HEMT structure.
In one embodiment of the present invention, the second portion includes a SiC MOSFET structure.
In an embodiment of the invention, the first substrate comprises one of sapphire, silicon carbide, silicon, zinc oxide, alumina, lithium aluminate or gallium nitride.
In an embodiment of the present invention, the semiconductor device further includes a substrate, and the first portion and the second portion are disposed on the substrate and connected side by side on the substrate.
In one embodiment of the present invention, the distance between the first gate and the first drain is 8-10 μm.
In an embodiment of the present invention, a first buffer layer is further included between the first substrate and the first epitaxial layer.
In an embodiment of the present invention, the material used for the first buffer layer includes one or more of aluminum oxide, hafnium oxide, titanium nitride, aluminum gallium nitride, or gallium nitride.
In one embodiment of the present invention, the first portion further comprises a field plate layer disposed on the first insulating layer.
In an embodiment of the present invention, a fourth insulating layer is disposed on a side interface of the first portion and the second portion.
In one embodiment of the present invention, the first gate includes a plurality of gate structures.
The utility model discloses a semiconductor device has excellent body diode characteristic, drives very easily simultaneously, and the designer can use the traditional gate driver like ordinary MOSFET, adopt voltage drive can. The utility model discloses compare current semiconductor integrated device, on-resistance is lower, and the leakage current still less, and output capacitance improves, and the efficiency of system improves.
Of course, it is not necessary for any particular product to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to the present invention;
fig. 2 is a schematic structural diagram of another embodiment of the semiconductor device of the present invention;
fig. 3 is a flow chart of a method of manufacturing the semiconductor device of fig. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
Referring to fig. 1 and 2, the present invention is a semiconductor device, including: a substrate 1, a first part 2 and a second part 3.
Referring to fig. 1 and fig. 2, the first portion 2 is disposed on the substrate 1, and the first portion 2 includes a HEMT structure, which includes: a first substrate 4, a first buffer layer 5, a first epitaxial layer 6, a passivation layer 14, a first source electrode 20, a first gate electrode 24, a first drain electrode 22, a field plate layer 25.
As shown in fig. 1 and fig. 2, the first substrate 4 is disposed on the substrate 1, the first buffer layer 5 is disposed on the first substrate 4 at a side away from the substrate 1, the thickness of the first buffer layer 5 may be 10nm to 300nm, and the first buffer layer 5 can effectively relieve the stress of the first epitaxial layer 6 grown in the later period, and can also reduce the vertical leakage of the semiconductor device and improve the voltage resistance of the device.
As shown in fig. 1 and fig. 2, the first buffer layer 5 may be a single layer structure or a composite structure composed of different material layers. The first buffer layer 5 material comprises: one or more of aluminum oxide, hafnium oxide, titanium nitride, aluminum gallium nitride, or gallium nitride. When the first buffer layer 5 is of a composite structure, lattice constants of different layers gradually change, the lattice constant of a material located near the surface of the first substrate 4 is closest to the lattice constant of the first substrate 4, and the lattice constant of a material at the top layer is closest to the lattice constant of the subsequently formed first epitaxial layer 6, so that lattice defects caused by the lattice constant of the first buffer layer 5 and the first substrate 4 in the first buffer layer 5 can be reduced, the interface state on the interface between the first buffer layer 5 and the first substrate 4 is reduced, and the interface leakage current on the interface is reduced. When the first buffer layer 5 has a single-layer structure, a material having a lattice constant closest to that of a group III metal nitride may be selected as the material of the first buffer layer 5. In this embodiment, the first buffer layer 5 may be made of aluminum nitride, and the thickness of the first buffer layer 5 is, for example, 100-200nm, and the aluminum nitride buffer layer in this range can effectively relieve the stress of the first epitaxial layer 6 grown in the later stage, and at the same time, reduce the vertical leakage of the semiconductor device, and improve the voltage resistance of the device.
Referring to fig. 1 and fig. 2, the semiconductor device of the present application further includes a first epitaxial layer 6, the first epitaxial layer 6 is disposed on the first buffer layer 5 on a side away from the substrate 1, the first epitaxial layer 6 may include a channel layer 7, a back barrier layer 8, a barrier layer 10, and a cap layer 12, wherein the channel layer 7 is disposed on the first buffer layer 5 on a side away from the first substrate 4, wherein the back barrier layer 8 is disposed on the channel layer 7 on a side away from the first buffer layer 5, wherein the barrier layer 10 is disposed on the back barrier layer 8 on a side away from the channel layer 7, and wherein the cap layer 12 is disposed on the barrier layer 10 on a side away from the back barrier layer 8.
Referring to fig. 1 and 2, the passivation layer 14 is disposed on the first epitaxial layer 6 at a side away from the first buffer layer 5. The first source electrode 20 and the first drain electrode 22 penetrate through the passivation layer 14, the cap layer 12 is connected with the barrier layer 10 in the first epitaxial layer 6, and the first gate electrode 24 penetrates through the passivation layer 14 and extends to the cap layer 12 in the first epitaxial layer 6. The length of the first gate 24 is, for example, 0.5 μm, which can achieve an operating frequency of the semiconductor device of 2.6 GHZ. The distance between the first gate 24 and the first drain 22 is 8-10 μm, for example, so that the semiconductor device can withstand the breakdown voltage of 600-800V.
Referring to fig. 1 and 2, in other embodiments, a plurality of first gates 24 may be included to further improve gate control capability and reduce gate leakage and off-state leakage.
Referring to fig. 1 and fig. 2, in the present embodiment, a first insulating layer 16 may be further disposed on the passivation layer 14, and the first insulating layer 16 covers the first gate 24, the first drain 22 and a portion of the first source 20. In other embodiments, a second insulating layer 18 may be further disposed between the first gate 24 and the cap layer 12 for insulating the first gate 24 from the cap layer 12, and the thickness of the second insulating layer 18 is, for example, 35nm, so that the threshold voltage of the semiconductor device reaches-10V.
Referring to fig. 1 and fig. 2, in other embodiments, the semiconductor device of the present application further includes a field plate layer 25, the field plate layer 25 is disposed on a side of the first insulating layer 16 away from the passivation layer 14, and the field plate layer 25 is connected to the first source electrode 20.
Referring to fig. 1 and 2, the first substrate 4 may be one or more of sapphire, silicon carbide, silicon, zinc oxide, aluminum oxide, lithium aluminate or gallium nitride. The silicon carbide (SiC) as the substrate has the outstanding characteristics of high pressure resistance, high frequency resistance and the like. The SiC material has the advantages of small lattice mismatch with GaN, high thermal conductivity, small device size, strong antistatic capability, high reliability and the like, is an ideal substrate of the GaN series epitaxial material, and can solve the heat dissipation problem of the power type GaN device due to the good thermal conductivity of the SiC material.
Referring to fig. 1 and 2, the channel layer 7 may be, for example, GaN, the back barrier layer 8 may be, for example, AlN, the barrier layer 10 may be, for example, AlGaN, the cap layer 12 may be, for example, n-GaN, and the passivation layer 14 may be, for example, SiN, which is a nitride of siliconxThe first insulating layer 16 may be, for example, silicon dioxide, the second insulating layer 18 may be, for example, aluminum oxide, the field plate layer 25 may be, for example, an al-si-cu metal layer, the first source electrode 20 may be an ohmic contact metal, the first drain electrode 22 may be an ohmic contact metal, and the first gate electrode 24 may be a first gate electrode 24 metal and an ohmic contact metal.
Referring to fig. 1 and 2, the second portion 3 is disposed on the substrate 1 and laterally connected to the first portion 2, the second portion 3 and the first portion 2 are coplanar and insulated from each other by a dielectric, and a fourth insulating layer 26, such as a silicon dioxide layer, is disposed at a side interface of the second portion 3 and the first portion 2. The second section 3 comprises a SIC MOSFET structure, i.e. comprising: a silicon carbide substrate 27, a P-type material region 30, an N-type diffusion region 32, a third insulating layer 33, a second source 34, a second drain 36, and a second gate 38.
Referring to fig. 1 and 2 together, a SiC substrate 27 is disposed on a substrate 1 and connected to a first substrate 4 in parallel, and SiC is used as a substrate of a second portion 3 in the present application because SiC has advantages of forbidden bandwidth, high thermal conductivity, high breakdown field strength, high saturated electron drift rate, stable chemical properties, high hardness, wear resistance, high bonding strength, high energy, and radiation resistance, and is very suitable for manufacturing high-temperature, high-frequency, high-power, radiation-resistant, high-power, and highly-dense integrated electronic devices.
Referring to fig. 1 and 2, the P-type material region 30 is disposed on the silicon carbide substrate 27, in this embodiment, the P-type material region 30 completely covers the silicon carbide substrate 27, in other embodiments, a second epitaxial layer 28 may be disposed on the silicon carbide substrate 27, and, for example, two P-type material regions 30 may be disposed in the second epitaxial layer 28, where the P-type material regions 30 may have any shape. The semiconductor device of the present application further includes, for example, two N-type diffusion regions 32, the two N-type diffusion regions 32 are disposed in the P-type material region 30, the two N-type diffusion regions 32 are isolated from or connected to each other, and the tops of the two N-type diffusion regions 32 are flush with the top of the P-type material region 30. The third insulating layer 33 is disposed on the P-type material region 30 and the N-type diffusion region 32, and completely or partially covers the P-type material region 30 and the N-type diffusion region 32, and the third insulating layer 33 is disposed in the same thickness and coplanar with the first insulating layer 16 in the first portion 2, so as to ensure that the second portion 3 is coplanar with the first portion 2. The second source electrode 34 and the second drain electrode 36 are connected to, for example, two N-type diffusion regions 32 through the third insulating layer 33, respectively, and the second source electrode 34 is connected to the silicon carbide substrate 27. The second gate electrode 38 is disposed on the third insulating layer 33 and between the second source electrode 34 and the second drain electrode 36.
As shown in fig. 1 and fig. 2, the third insulating layer 33 may be silicon dioxide, the second source electrode 34 may be an ohmic contact metal, the second drain electrode 36 may be an ohmic contact metal, and the second gate electrode 38 may be a second gate electrode 38 metal and an ohmic contact metal.
Referring to fig. 1 and 2, the second drain 36 and the second source 34 in the second portion 3 are respectively connected to the first source 20 and the first gate 24 in the first portion 2.
Referring to fig. 1 and 2, in the present embodiment, the contact surface formed by AlGaN and GaN forms a heterojunction due to the difference of the forbidden bandwidths of these two materials. Due to the fact that the Fermi level of the semiconductor material at the heterojunction contact surface is suddenly changed, electrons can be transferred from AlGaN to the GaN direction, the electric field at the heterojunction contact surface is changed due to the transfer of the electrons, AlGaN loses the electrons to form a depletion layer, the movement of the electrons far away from the heterojunction is prevented, the electronic potential energy of GaN is low, the electrons can be bound, holes can be driven, and a potential well region with the electrons is formed on one side of the GaN semiconductor material at the heterojunction contact surface. As free electrons accumulate in the potential well, a two-dimensional electron gas (2DEG) is formed, and the 2DEG is constrained by the two-sided semiconductor and can only move in a direction parallel to the heterojunction interface. The 2DEG exhibits high electron mobility since it is free from the AlGaN supplied to it and into GaN, no longer dominated by ionized impurity scattering. The 2DEG with high electron mobility can move at high speed on a heterojunction surface formed by AlGaN and GaN so as to form a conductive channel of the depletion type GaN transistor, and the on and off of the depletion type HEMT crystal structure can be controlled by controlling the concentration of the 2DEG in the GaN/AlGaN heterojunction.
Referring to fig. 1 and 2, a high voltage depletion mode first part 2(HEMT) and a low voltage enhancement mode second part 3(SiC MOSFET) are combined to form an enhancement mode semiconductor device. The drain and source electrodes of the low-voltage enhancement type SiC MOSFET are respectively connected with the source and the grid electrode of the high-voltage depletion type HEMT crystal structure, so that the drain-source voltage of the low-voltage enhancement type SiC MOSFET provides negative bias for the grid-source voltage of the high-voltage depletion type HEMT crystal structure device, and the high-voltage depletion type HEMT crystal structure device is turned off.
Referring to fig. 1, fig. 2 and fig. 3, the present invention further provides a method for manufacturing a semiconductor device, which includes the following steps:
s01: providing a substrate 1; s02: arranging a first substrate 4 and a silicon carbide substrate 27 on the base plate 1, wherein the first substrate 4 and the silicon carbide substrate 27 are transversely arranged side by side; s03: preparing a first portion 2 on said first substrate 4; s04: a second portion 3 is prepared on the silicon carbide substrate 27, the second portion 3 being coplanar and insulated from the first portion 2.
Referring to fig. 1, 2 and 3, in step S01 and step S02, a base plate 1 is provided, a first substrate 4 and a silicon carbide substrate 27 are disposed on the base plate 1, and the first substrate 4 and the silicon carbide substrate 27 are laterally disposed side by side. The material of the first substrate 4 may be sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, gallium nitride, or the like. And the surface of the first substrate 4 needs to be sufficiently cleaned before the subsequent processes are performed. The first substrate 4 may be 2 inches, 4 inches, 6 inches, 8 inches, or 12 inches in size.
Referring to fig. 1, fig. 2 and fig. 3 together, in step S03, a first portion 2 is prepared on a first substrate 4, the first portion 2 includes a HEMT structure, that is, includes: a first substrate 4, a first buffer layer 5, a first epitaxial layer 6, a passivation layer 14, a first source electrode 20, a first gate electrode 24, a first drain electrode 22, a field plate layer 25.
Referring to fig. 1, fig. 2 and fig. 3, in step S03, a first buffer layer 5 is formed on the surface of the first substrate 4, and the first buffer layer 5 may be formed by a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process. The lattice constant of the first buffer layer 5 is generally between the first substrate 4 and the first epitaxial layer 6, and the first buffer layer 5 is used for relieving the stress between the first epitaxial layer 6 to be formed subsequently and the first substrate 4, and reducing the defects such as dislocation and the like in the first epitaxial layer 6 to be formed subsequently.
Referring to fig. 1, 2 and 3, in step S03, the first buffer layer 5 may be a single layer or a composite structure composed of different material layers. The first buffer layer 5 material comprises: one or more of aluminum oxide, hafnium oxide, titanium nitride, aluminum gallium nitride, or gallium nitride. When the first buffer layer 5 is of a composite structure, lattice constants of different layers gradually change, the lattice constant of a material located near the surface of the first substrate 4 is closest to the lattice constant of the first substrate 4, and the lattice constant of a material at the top layer is closest to the lattice constant of the subsequently formed first epitaxial layer 6, so that lattice defects caused by the lattice constant of the first buffer layer 5 and the first substrate 4 in the first buffer layer 5 can be reduced, the interface state on the interface between the first buffer layer 5 and the first substrate 4 is reduced, and the interface leakage current on the interface is reduced. When the first buffer layer 5 has a single-layer structure, a material having a lattice constant closest to that of a group III metal nitride may be selected as the material of the first buffer layer 5. The thickness of the first buffer layer 5 may be 10nm to 300 nm. In this embodiment, aluminum nitride is used as the material of the first buffer layer 5, and the aluminum nitride first buffer layer 5 is deposited on the first substrate 4 by PVD at a temperature range of 780-.
Referring to fig. 1, fig. 2 and fig. 3, in step S03, a first epitaxial layer 6 may be formed on the first buffer layer 5 by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, where the first epitaxial layer 6 sequentially includes a channel layer 7, a back barrier layer 8, a barrier layer 10 and a cap layer 12, where the channel layer 7 may be, for example, GaN, the back barrier layer 8 may be, for example, AlN, the barrier layer 10 may be, for example, AlGaN, and the cap layer 12 may be, for example, n-GaN.
Referring to fig. 1, fig. 2 and fig. 3, in step S03, the channel layer 7 may be formed on the surface of the first buffer layer 5 by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, because the lattice constant difference between the first buffer layer 5 and the channel layer 7 is low, the crystal quality of the channel layer 7 may be effectively improved, the dislocation density in the channel layer 7 may be reduced, and the quality of the first epitaxial layer 6 may be effectively improved on the basis.
Referring to fig. 1, 2 and 3, in step S03, a passivation layer 14 may be formed on the first epitaxial layer 6 by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, where the passivation layer 14 may be, for example, a silicon nitride SiNxAnd simultaneously etching the passivation layer 14, the cap layer 12 and the first epitaxial layer 6 to form a first source contact hole and a first drain contact hole which penetrate through the passivation layer 14 and the cap layer 1212 and are connected with the barrier layer 10 in the first epitaxial layer 6. Ohmic contact metal is deposited in the first source contact hole and the first drain contact hole, and a first source electrode 20 and a first drain electrode 22 are obtained. The ohmic contact metal comprises, for example, from bottom to top: the metal layer comprises a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer. The first titanium metal layer and the second titanium metal layer are made of titanium (Ti), and the aluminum metal layer is made of aluminum (Al)(Al), the titanium nitride layer is composed of titanium nitride (TiN).
Referring to fig. 1, 2 and 3, in step S03, the deposition of the ohmic contact metal may be performed by, for example, magnetron sputtering, and in order to make the ohmic contact good, the contact holes, i.e., the first source contact hole and the first drain contact hole, need to be cleaned with less impurities, so that the fabrication process of the first source electrode 20 and the first drain electrode 22 may further include an impurity removal step, specifically, for example, cleaning the contact holes with hydrofluoric acid (HF) before depositing the ohmic contact metal, and performing a rapid annealing (RTS) at 850 ℃ for 45S in a nitrogen (N2) environment after depositing the ohmic contact metal.
Referring to fig. 1, 2 and 3, in step S03, the passivation layer 14 is etched to form a first gate contact hole penetrating the passivation layer 14 and extending to the cap layer 12 in the first epitaxial layer 6, and a second insulating layer may be formed in the first gate contact hole by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, wherein the second insulating layer is configured to insulate the first gate 24 from the cap layer 12. The second insulating layer may be, for example, alumina, and the thickness of the second insulating layer is, for example, 35nm, so that the threshold voltage of the semiconductor device reaches-10V. And sequentially depositing a first gate 24 metal and an ohmic contact metal on the second insulating layer, wherein the first gate 24 metal is made of titanium nitride (TiN), and the thickness of the gate metal is 220nm, for example.
Referring to fig. 1, 2 and 3, in step S03, a first insulating layer may be formed on the passivation layer 14 by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, and the first insulating layer covers the first gate 24, the first drain 22 and a portion of the first source 20. The first insulating layer is made of silicon dioxide, for example.
Referring to fig. 1, fig. 2 and fig. 3, in step S03, in another embodiment, the semiconductor device further includes a field plate layer 25, the field plate layer 25 is disposed on a side of the passivation layer 14 away from the first epitaxial layer 6, the field plate layer 25 is connected to the first source electrode 20, and the field plate layer 25 is made of an al-si-cu metal layer.
Referring to fig. 1, 2 and 3, in step S04, a second portion 3 is formed on the sic substrate 27, and the second portion 3 and the first portion 2 are coplanar and insulated from each other. A fourth insulating layer, which may be, for example, silicon dioxide, is provided at the side interface of the second portion 3 and the first portion 2. The second section 3 comprises a SIC MOSFET structure, i.e. comprising: a silicon carbide substrate 27, a P-type material region 30, an N-type diffusion region 32, a third insulating layer 33, a second source 34, a second drain 36, and a second gate 38.
Referring to fig. 1, 2 and 3, in step S04, the silicon carbide substrate 27 is disposed on the substrate 1, so that the silicon carbide substrate 27 and the first substrate 4 are connected side by side in the transverse direction, and the silicon carbide substrate is used as the substrate of the second portion 3 in the present application because SiC has the advantages of high forbidden bandwidth, high thermal conductivity, high breakdown field strength, high saturated electron drift rate, stable chemical performance, high hardness, wear resistance, high bonding, high energy and radiation resistance, and is very suitable for manufacturing high-temperature, high-frequency, high-power, radiation resistance, high-power and high-density integrated electronic devices.
Referring to fig. 1, 2 and 3, in step S04, the second epitaxial layer 28 may be deposited on the silicon carbide substrate 27, the second epitaxial layer 28 may be formed by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, and the second epitaxial layer 28 may be formed of GaN or AlGaN.
Referring to fig. 1, 2 and 3, in step S04, P-type material regions 30 are diffused on the silicon carbide substrate 27 or the second epitaxial layer 28, and the P-type material regions 30 may completely cover the silicon carbide substrate 27, or two P-type material regions 30 isolated from each other may be diffused in the second epitaxial layer 28, where the P-type material regions 30 may have any shape.
Referring to fig. 1, 2 and 3, in step S04, for example, two N-type diffusion regions 32 are diffused in the P-type material region 30, the two N-type diffusion regions 32 are respectively disposed in the P-type material region 30, the two N-type diffusion regions 32 are isolated from or connected to each other, and the tops of the two N-type diffusion regions 32 are flush with the top of the P-type material region 30.
Referring to fig. 1, 2 and 3, in step S04, a third insulating layer 33 may be deposited on the P-type material region 30 and the N-type diffusion region 32 by one or more of a metal organic chemical vapor deposition process, a molecular beam epitaxy process, a hydride vapor phase epitaxy process or an atomic layer epitaxy process, the third insulating layer 33 may be, for example, silicon dioxide, the third insulating layer 33 completely or partially covers the P-type material region 30 and the N-type diffusion region 32, and the third insulating layer 33 is as thick as and coplanar with the first insulating layer in the first portion 2, so as to ensure that the second portion 3 is coplanar with the first portion 2.
Referring to fig. 1, 2 and 3, in step S04, the third insulating layer 33 is etched to form a second source electrode 34 contact hole and a second drain electrode 36 contact hole penetrating the third insulating layer 33 and connecting with the N-type diffusion region 32. And depositing an ohmic contact metal in the second source electrode 34 contact hole and the second drain electrode 36 contact hole to obtain a second source electrode 34 and a second drain electrode 36. The ohmic contact metal comprises, for example, from bottom to top: the metal layer comprises a first titanium metal layer, an aluminum metal layer, a second titanium metal layer and a titanium nitride layer. The first titanium metal layer and the second titanium metal layer are made of titanium (Ti), the aluminum metal layer is made of aluminum (Al), and the titanium nitride layer is made of titanium nitride (TiN). The second source electrode 34 is connected to the silicon carbide substrate 27. The drain-source in the second section 3 is connected to the source-gate in the first section 2, respectively.
Referring to fig. 1, 2 and 3, in step S04, a second gate 38 is deposited on the third insulating layer 33 such that the second gate 38 is located between the second source 34 and the second drain 36. The second gate 38 includes a second gate 38 metal and an ohmic contact metal from bottom to top.
Gallium nitride, the third generation semiconductor material, has the advantages of wide bandgap, high critical breakdown electric field, high electron mobility and the like. With the development and maturity of two fields of Light Emitting Diode (LED) and radio frequency amplifier, the preparation of gallium nitride materials is continuously advanced, and gallium nitride HEMT devices are also widely concerned in the electronic power field. In addition, the SiC MOSFET prepared based on the silicon carbide (SiC) material has more obvious advantages compared with the Si MOSFET: smaller on-resistance, faster switching process, smaller parasitic capacitance, higher operating temperature, better diode reverse recovery characteristics. The reverse recovery current of the SiC-based device is small, and the change of the reverse recovery current is small when the load current changes. The reverse recovery of the Si-based diode requires the recombination of electrons and holes, so that the reverse recovery time is long, the reverse recovery current is large, and the reverse recovery is also influenced by the load current. Based on the advantages of the gallium nitride HEMT device and the SiC MOSFET device, the gallium nitride HEMT device and the SiC MOSFET device are considered to be integrated to form an enhanced device.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. A semiconductor device, comprising:
a first portion comprising:
a first substrate;
a first epitaxial layer disposed on the first substrate;
a passivation layer disposed on the epitaxial layer;
the first source electrode, the first grid electrode and the first drain electrode penetrate through the passivation layer and are connected with the epitaxial layer;
a first insulating layer disposed on the passivation layer and covering the first gate electrode and the first drain electrode and a portion of the first source electrode;
a second portion laterally connected with the first portion and coplanar with the first portion and dielectrically insulated from each other, the second portion comprising:
a silicon carbide substrate connected laterally side-by-side with the first substrate;
a P-type material region disposed on the silicon carbide substrate;
an N-type diffusion region disposed on the P-type material region;
a third insulating layer covering the P-type material region and the N-type diffusion region; the third insulating layer and the first insulating layer are the same in thickness and are arranged in a coplanar manner;
a second source and a second drain penetrating the third insulating layer and connected to the N-type diffusion region; the second source electrode is connected with the silicon carbide substrate;
a second gate disposed on the third insulating layer and between the second source and the second drain.
2. The semiconductor device of claim 1, wherein the first portion comprises a HEMT structure.
3. The semiconductor device of claim 1, wherein the second portion comprises a SiC MOSFET structure.
4. The semiconductor device according to claim 1, wherein the first substrate comprises one of sapphire, silicon carbide, silicon, zinc oxide, aluminum oxide, lithium aluminate, or gallium nitride.
5. The semiconductor device according to claim 1, further comprising a substrate, wherein the first portion and the second portion are disposed on the substrate and are connected side by side on the substrate.
6. The semiconductor device of claim 1, further comprising a first buffer layer between the first substrate and the first epitaxial layer.
7. The semiconductor device of claim 1, wherein the first portion further comprises a field plate layer disposed on the first insulating layer.
8. A semiconductor device according to claim 1, wherein a fourth insulating layer is provided at a side interface of the first portion and the second portion.
9. The semiconductor device of claim 1, wherein the first gate comprises a plurality of gate structures.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496934A (en) * | 2022-01-25 | 2022-05-13 | 西安电子科技大学 | GaN HEMTs and top layer hydrogen terminal diamond MOSFETs integrated structure and preparation method thereof |
| CN114497038A (en) * | 2022-01-25 | 2022-05-13 | 西安电子科技大学 | GaN HEMT device and p-type diamond MOSFET integrated device and preparation method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114496934A (en) * | 2022-01-25 | 2022-05-13 | 西安电子科技大学 | GaN HEMTs and top layer hydrogen terminal diamond MOSFETs integrated structure and preparation method thereof |
| CN114497038A (en) * | 2022-01-25 | 2022-05-13 | 西安电子科技大学 | GaN HEMT device and p-type diamond MOSFET integrated device and preparation method thereof |
| CN114496934B (en) * | 2022-01-25 | 2023-11-28 | 西安电子科技大学 | GaN HEMTs and top-layer hydrogen-terminated diamond MOSFETs integrated structure and preparation method thereof |
| CN114497038B (en) * | 2022-01-25 | 2024-02-06 | 西安电子科技大学 | GaN HEMT device and p-type diamond MOSFET integrated device and manufacturing method thereof |
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