CN102082176A - Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof - Google Patents
Gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and manufacturing method thereof Download PDFInfo
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- CN102082176A CN102082176A CN2010105721323A CN201010572132A CN102082176A CN 102082176 A CN102082176 A CN 102082176A CN 2010105721323 A CN2010105721323 A CN 2010105721323A CN 201010572132 A CN201010572132 A CN 201010572132A CN 102082176 A CN102082176 A CN 102082176A
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Abstract
The invention relates to a gallium nitride (GaN) enhancement type metal insulator semiconductor field effect transistor (MISFET) device and a manufacturing method thereof. The GaN enhancement type MISFET device comprises a substrate and an epitaxial layer arranged on the substrate, wherein the epitaxial layer comprises a stress buffer layer and a GaN layer sequentially from bottom to top; a heterogeneous layer selectively grows on the GaN layer; insulating medium layers are formed on the surface, where the heterogeneous layer does not grow, of the GaN layer and the surface of the heterogeneous layer; a grid region is arranged on the insulating medium layer formed on the surface of the GaN layer; the insulating medium layer formed on the surface of the heterogeneous layer is etched to form a source region and a drain region; grid metals are formed in the grid region; and ohmic contact metals are formed on the source region and the drain region. The GaN enhancement type MISFET device and the manufacturing method thereof have the characteristics that: a heterogeneous structure with high-concentration two-dimensional electron gas grows in an access region by a selected region epitaxial technique, so that the conducting channel plane of the grid can naturally align with that of the source and the drain, the resistance of the access region can be effectively reduced, and the threshold voltage of the grid of the device can be increased.
Description
Technical field
The present invention relates to a kind of GaN enhancement mode MISFET device and preparation method thereof, relate in particular to a kind of GaN enhancement mode MISFET device in high temperature high power switching device and microwave device and preparation method thereof.
Background technology
With GaN is the semiconductor material with wide forbidden band of representative, with the material property of broad stopband, high breakdown field strength, high heat conductance, high saturated electron drift velocity, the high excellence of heterogeneous interface two-dimensional electron gas; Become present third generation semiconducter research focus.These characteristics make GaN have very big advantage and application prospect aspect the making high-power electronic device.
The research of enhancing (normal closing) type HEMT has important meaning for the practicability of GaN electronic device.The enhancement device grid does not need the negative voltage power supply just can realize closing of raceway groove, satisfies general power switch circuit to the device security designing requirement.In the microwave power amplifying circuit, the application of enhancement device can realize the one pole power supply, the design of simplified driving circuit; Improve the good compatibility of distorted signals and realization and existing system.
But have a strong polarity effect because AlGaN/GaN is heterogeneous, easily form concentration up to 10
13Cm
-2The two-dimensional electron gas of surface density (2DEG) when grid does not add any bias voltage, just has the high electronics surface density and the 2DEG of electron mobility, makes AlGaN/GaN HEMT device form depletion mode fet naturally; And enhancement device needs grid not during making alive, realizes exhausting of conducting channel charge carrier under the grid.AlGaN/GaN HEMT realizes that the difficulty of enhancement mode just is that when not adding grid voltage, the 2DEG of high concentration is difficult to exhaust.
In the technical scheme that realizes enhancement mode GaN FET device at present, mainly be divided into conductivity gate field effect transistor Manifold technology and metal dielectric layer semiconductor field effect transistor (MISFET) technology.
For conductivity gate field-effect transistor technology, the researcher has also proposed different schemes and has realized enhancement mode, and the most frequently used method is to adopt recessed gate technique.By on traditional depletion-mode AlGaN/GaN HEMT device architecture, doing the fovea superior grid technique, promptly behind the AlGaN/GaN heterojunction of having grown, by groove of ICP-RIE etching, in groove, make the Ni/Au conductivity gate at area of grid.Can reduce the concentration of the two-dimensional electron gas of conducting channel below the grid greatly by recessed grid structure,, realize often closing in conjunction with high barrier schottky gate metal.Fluoride plasma treatment technology realizes that normal pass type device is a kind of new technology of rising in recent years, injects electronegative ions such as fluorine ion in the AlGaN barrier layer, and control is injected ion concentration and the two-dimensional electron gas of conducting channel can be exhausted.With top two kinds is that the conductivity gate field-effect transistor of representative realizes that advantage is: realized big source-drain current in enhanced AlGaN/GaN HEMT scheme; With low opening resistor (R
On).But shortcoming also clearly: to compare grid leakage current bigger with MISFET; Threshold voltage can reach about 0V-1V, also has with a certain distance from the threshold voltage of using (3V-5V); Because adopt the recessed gate technique and the ion implantation technique of dry etching all to adopt the plasma treatment technology, plasma treatment causes damage to lattice, technology repeats controlled poor, and the stability and the reliability of device impacted.
The MISFET technology is improving threshold voltage, and reducing the grid leakage current aspect has bigger advantage.Be similar to the conventional MOS pipe, the MISFET of GaN base also adopts p type and n type to mix and realizes device function.Insert the zone by source electrode on p type GaN layer and drain electrode and carry out the injection of selectivity ion, form n type Doped GaN and insert the district.When grid adds malleation, and after reaching certain voltage, form inversion layer at interfacial dielectric layer, inversion layer is realized the raceway groove conducting by electron accumulation.
Another kind of improved MISFET scheme is, the MISFET that has comprised the AlGaN/GaN heterostructure, utilize the two-dimensional electron gas of heterojunction high concentration and high mobility to realize big electric current and low opening resistor characteristic in source-drain electrode ohmic contact zone, utilize MIS(metal-insulant-semiconductor at area of grid) the normal characteristic of closing of realization.When adding positive voltage, and after reaching certain voltage, form electron accumulation layer at semiconductor contact interface, thereby realize the unlatching of conducting channel to grid.In up-to-date achievement in research, people such as Ki-Sil Im, by the AlGaN/GaN that grows on the Si substrate, ICP etching area of grid etches into the high resistant GaN layer, utilizes the ALD(ald) Al on the deposition
2O
3As gate oxide.Device performance has realized that threshold voltage is 2V, maximum current density 353mA/mm, peak value mutual conductance 98mS/mm.Referring to document Ki-Sil Im, Jong-Bong Ha, Ki-Won Kim et al. Normally off GaN MOSFET Based on AlGaN/GaN Heterostructure With Extremely High 2DEG Density Grown on Silicon Substrate IEEE Electron Device Lett., vol.31, no.3, pp.192-194.
The MISFET technology is with the obvious advantage aspect realization raising enhancement device threshold voltage as can be seen from nearest achievement in research, is more satisfactory technology path.But the GaN base MISFET conducting electric current based on traditional MISFET structure is little at present, is unfavorable for realizing high-power characteristic; Utilize in the MISFET report of AlGaN/GaN heterojunction, aspect the formation of grid groove structure and making, adopt the ICP-RIE etching technics, and the damage influence device performance that etching technics causes material, can't accurately control aiming at of conducting channel plane and source leakage conductance electricity channel plane under the grid after the etching, increased break-over of device resistance, current density is low.Therefore in the advantages such as high threshold voltage that guarantee MISFET, can there be a kind of new technical scheme to realize the device low on-resistance, increases the key point that current density becomes research.The present invention utilizes the regional diauxic growth technology of selecting, and inserting district's growth heterostructure, forms the high concentration two-dimensional electron gas, reduces MISFET and inserts district's resistance, increases current density; Select growing technology also to simplify device technology simultaneously, realize aiming at naturally of grid and source-drain electrode conducting channel plane, improve device performance.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of GaN enhancement mode MISFET device and preparation method thereof is provided.The present invention hangs down the characteristic of grid leakage current in conjunction with the MISFET high threshold voltage; And the selection growing technology, avoided the etching injury conducting channel, technology is simple, and repeatability is high, improves device reliability and stability.
For achieving the above object, technical scheme of the present invention is: a kind of GaN enhancement mode MISFET device, comprise substrate and be located at the epitaxial loayer of substrate, wherein, epitaxial loayer comprises stress-buffer layer and GaN layer from lower to upper successively, select growth that heterosphere is arranged on the GaN layer, do not grow to have on the GaN laminar surface of heterosphere and the heterosphere surface and be formed with insulating medium layer, and on the insulating medium layer that the GaN laminar surface forms, be provided with area of grid, form source region and drain region at heterosphere surface etch insulating medium layer, area of grid is formed with gate metal, this source, be formed with metal ohmic contact on the drain region.
Heterosphere is a kind of or any several combination in AlGaN, AlInN, AlInGaN, the AlN material, and this heterosphere is non-doped layer or N type doped layer; The GaN layer is high resistant GaN layer or p type GaN layer.
This insulating medium layer is SiO
2, SiNx, Al
2O
3, AlN, HFO
2, MgO, Sc
2O
3, Ga
2O
3, among AlHFOx, the HFSiON any.
Thickness of insulating layer can be controlled at 1nm～50nm.
Metal ohmic contact is Ti/Al/Ni/Au alloy or Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Gate metal is for realizing the various metal or alloy of device high threshold voltage, as Ni/Au alloy or Pt/Al alloy or Pd/Au alloy etc.
Simultaneously, the invention provides a kind of GaN enhancement mode MISFET preparation of devices method, it may further comprise the steps:
A, utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating and GaN layer successively on substrate;
B, on the GaN layer, by plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetic control sputtering plating, evenly long last layer dielectric layer is as selecting the growth mask layer;
C, employing photoetching technique, the selective etch mask layer keeps the area of grid mask layer;
D, utilize metal organic chemical vapor deposition or molecular beam epitaxy, the regrowth heterosphere;
After E, dry etching are finished device isolation, utilize wet etching method etching gate mask layer, show the insulating medium layer contact interface;
F, utilize plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD), megohmite insulant on the contact interface deposition is as gate insulator;
G, employing litho pattern carve source electrode, drain electrode ohmic contact zone, the insulating barrier material in wet etching or dry etching etching window zone, metal ohmic contact on the evaporation again;
H, employing evaporation process, evaporation gate metal on gate insulator.
Among the step B, the AlN insert layer is arranged in the growth of GaN laminar surface.The thickness of AlN insert layer is 1nm～10nm.
This programme inserts district's diauxic growth heterosphere at first by mask technique, can increase the two-dimensional electron gas that MISFET inserts the zone, reduces the contact resistance and the break-over of device resistance that insert the district; Secondly at area of grid, remove the diauxic growth mask after, by plasma reinforced chemical vapour deposition, ald, insulation oxide or other megohmite insulants realize that as the MISFET insulating barrier device grids insulation isolates on the deposition techniques such as physical vapour deposition (PVD); Finally realize the normal pass characteristic of device in conjunction with two technical schemes.
Compare with the enhancement mode GaN based hemts device of prior art, the present invention has adopted diauxic growth technology and insulated gate electrode technology.Selection source, drain region growth heterosphere are inserting district's formation high concentration, high mobility two-dimensional electron gas, reduce device and insert district's contact resistance, increase the device current density.The insulated gate electrode technology, at the area of grid depositing insulating layer, when having realized that device channel is often closed characteristic, that has also realized grid conducting channel and source, drain electrode two-dimensional electron gas channel plane aims at the loss of the scattering formation of reduction charge carrier in raceway groove naturally; When insulated gate electrode added positive voltage, channel electrons accumulation conducting improved device threshold voltage, reduces grid leakage current.
Description of drawings
Fig. 1 is first kind of structural representation of GaN enhancement mode MISFET of the present invention and preparation method thereof;
Fig. 2 is second kind of structural representation of GaN enhancement mode MISFET of the present invention and preparation method thereof;
Fig. 3 is the third structural representation of GaN enhancement mode MISFET of the present invention and preparation method thereof;
Fig. 4 is the 4th kind of structural representation of GaN enhancement mode MISFET of the present invention and preparation method thereof;
Fig. 5 A-5H is the process schematic representation of GaN enhancement mode MISFET of the present invention and preparation method thereof.
Embodiment
Embodiment 1
Present embodiment such as Fig. 1 have provided a kind of GaN enhancement mode MISFET device, it comprises: substrate 1 and the stress-buffer layer 2 and the GaN layer 3 of growing by MOCVD or MBE on substrate 1, on GaN layer 3, select the heterosphere 6 of growth, inserting district's growth heterosphere structure when selecting growth, and the grid place is stopped by mask layer 5, area of grid forms insulating medium layer 8 by deposition, source-drain electrode inserts the zone and goes up evaporation metal ohmic contact 9, gate metal 10 on the evaporation above the area of grid insulating medium layer.
Select the thickness of growth heterosphere 6 need control to and to form enough two-dimensional electron gas in the GaN bed boundary, reduce source-drain electrode ohmic contact resistance and break-over of device resistance again.Heterosphere thickness can be controlled at 1nm～50nm.
The control of the thickness of gate oxidation insulating medium layer 8 can either be satisfied the conductive characteristic that grid contacts the fine control raceway groove of 10 energy, also needs to keep good gate insulator.
As shown in Figure 2, present embodiment has provided a kind of second kind of structure of GaN enhancement mode MISFET device, the device architecture of it and embodiment 1 is roughly the same, difference is, mix by modulation N type when selecting growth heterosphere 11, further reduction source, drain region ohmic contact resistance improve device current density.
As shown in Figure 3, present embodiment has provided the third structure of a kind of GaN enhancement mode MISFET device, present embodiment is in the conducting channel district, promptly in the AlN insert layer 12 of GaN layer 3 superficial growth one deck 1nm-10nm, AlN insert layer 12 can effectively improve conducting channel 2DEG concentration and mobility, improves the break-over of device current density.Specifically scheme is, after the GaN layer 3 of on backing material, having grown, and growing AIN insert layer 12, later stage technology is identical with embodiment 1.
Embodiment 4
As shown in Figure 4, present embodiment has provided a kind of the 4th kind of structure of GaN enhancement mode MISFET device, and present embodiment replaces high resistant GaN layer 3 by growing p-type GaN layer 13; P type GaN layer 13 could communication channel when conducting channel forms the electron inversion layer at the interface, and forming the electron inversion layer needs bigger grid positive voltage, is the effective ways that improve the grid cut-in voltage.
Fig. 5 A-5H is a kind of GaN enhancement mode of the present invention MISFET device preparation method's process flow diagram, and its technological process is as follows:
A, utilize metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), on Si substrate or SiC substrate or Sapphire Substrate 1, growth stress resilient coating 2 and high resistant GaN layer 3 successively;
B, on high resistant GaN layer 3, by plasma enhanced chemical vapor deposition (PECVD) or ald (ALD) or physical vapor deposition (PVD) or magnetic control sputtering plating etc., evenly long last layer dielectric layer is as selecting growth mask layer 4;
C, employing photoetching technique, selective etch mask layer 4 keeps area of grid mask layer 5;
D, utilize metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), regrowth heterosphere 6;
After E, dry etching are finished device isolation, utilize wet etching method etching gate mask layer 5, show the contact interface 7 of insulating medium layer 8;
F, utilize plasma enhanced chemical vapor deposition (PECVD) or ald (ALD) or physical vapor deposition (PVD) etc., on contact surface 7, deposit megohmite insulant, as gate insulator dielectric layer 8;
G, employing litho pattern carve source electrode and drain electrode ohmic contact zone, the insulating barrier material in wet etching or dry etching etching window zone, metal ohmic contact 9 on the evaporation again;
H, employing evaporation process, evaporation gate metal 10 on gate insulator dielectric layer 8.
Claims (9)
1. GaN enhancement mode MISFET device, comprise substrate (1) and be located at the epitaxial loayer of substrate (1), it is characterized in that, epitaxial loayer comprises stress-buffer layer (2) and GaN layer (3) from lower to upper successively, GaN layer (3) is gone up and is selected growth that heterosphere (6) is arranged, do not grow to have on GaN layer (3) surface of heterosphere (6) and heterosphere (6) surface and be formed with insulating medium layer (8), and on the insulating medium layer (8) of GaN layer (3) surface formation, be provided with area of grid, on heterosphere (6) surface, form source region and drain region by etching insulating medium layer (8), area of grid is formed with gate metal (10), this source, be formed with metal ohmic contact (9) on the drain region.
2. GaN enhancement mode MISFET device according to claim 1 is characterized in that, heterosphere (6) is a kind of or any several combination in AlGaN, AlInN, AlInGaN, the AlN material, and this heterosphere is non-doped layer or N type doped layer; GaN layer (3) is high resistant GaN layer or p type GaN layer.
3. GaN enhancement mode MISFET device according to claim 1 is characterized in that this insulating medium layer (8) is SiO
2, SiNx, Al
2O
3, AlN, HfO
2, MgO, Sc
2O
3, Ga
2O
3, among AlHfOx, the HfSiON any.
4. GaN enhancement mode MISFET device according to claim 3 is characterized in that insulating medium layer (8) thickness is between 1nm～50nm; Heterosphere (6) thickness is between 1nm～50nm.
5. according to each described GaN enhancement mode MISFET device of claim 1 to 4, it is characterized in that metal ohmic contact (9) is Ti/Al/Ni/Au alloy or Ti/Al/Ti/Au alloy or Ti/Al/Mo/Au alloy; Gate metal (10) is for realizing the metal or alloy of device high threshold voltage.
6. GaN enhancement mode MISFET device according to claim 5 is characterized in that, gate metal is Ni/Au alloy or Pt/Al alloy or Pd/Au alloy.
7. a GaN enhancement mode MISFET preparation of devices method is characterized in that, may further comprise the steps:
A, utilize metal organic chemical vapor deposition or molecular beam epitaxy, growth stress resilient coating (2) and GaN layer (3) successively on substrate;
B, on GaN layer (3), by plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD) or magnetic control sputtering plating, evenly long last layer dielectric layer is as selecting growth mask layer (4);
C, employing photoetching technique, selective etch mask layer (4) keeps area of grid mask layer (5);
D, utilize metal organic chemical vapor deposition or molecular beam epitaxy, regrowth heterosphere (6);
After E, dry etching are finished device isolation, utilize wet etching method etching gate mask layer (5), show the contact interface (7) of insulating medium layer (8);
F, utilize plasma enhanced chemical vapor deposition or ald or physical vapour deposition (PVD), megohmite insulant on contact interface (7) deposition is as gate insulator;
G, employing litho pattern carve source electrode, drain electrode ohmic contact zone, the insulating barrier material in wet etching or dry etching etching window zone, metal ohmic contact (9) on the evaporation again;
H, employing evaporation process, evaporation gate metal (10) on gate insulator.
8. GaN enhancement mode MISFET preparation of devices method according to claim 7 is characterized in that, among the step B, in GaN layer (3) superficial growth AlN insert layer (12) is arranged.
9. GaN enhancement mode MISFET preparation of devices method according to claim 8 is characterized in that the thickness of AlN insert layer (12) is 1nm～10nm.
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| CN102280494A (en) * | 2011-08-16 | 2011-12-14 | 电子科技大学 | Normally-closed field control channel GaN heterojunction diode |
| CN102856374A (en) * | 2012-10-10 | 2013-01-02 | 中山大学 | GaN enhanced MIS-HFET device and preparation method of same |
| CN102881721A (en) * | 2012-10-26 | 2013-01-16 | 中山大学 | Mixed-structure field effect transistor and manufacturing method thereof |
| CN103094105A (en) * | 2013-01-28 | 2013-05-08 | 华中科技大学 | A face normally closed type high electron mobility transistor (HEMT) manufacturing method through adoption of GaN self-imaging template |
| CN104465403A (en) * | 2014-12-29 | 2015-03-25 | 苏州能屋电子科技有限公司 | Enhanced AlGaN/GaN HEMT device preparation method |
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| CN102856374A (en) * | 2012-10-10 | 2013-01-02 | 中山大学 | GaN enhanced MIS-HFET device and preparation method of same |
| CN102856374B (en) * | 2012-10-10 | 2015-06-10 | 中山大学 | GaN enhanced MIS-HFET device and preparation method of same |
| CN102881721B (en) * | 2012-10-26 | 2015-04-22 | 中山大学 | Mixed-structure field effect transistor and manufacturing method thereof |
| CN102881721A (en) * | 2012-10-26 | 2013-01-16 | 中山大学 | Mixed-structure field effect transistor and manufacturing method thereof |
| CN103094105A (en) * | 2013-01-28 | 2013-05-08 | 华中科技大学 | A face normally closed type high electron mobility transistor (HEMT) manufacturing method through adoption of GaN self-imaging template |
| CN104465403A (en) * | 2014-12-29 | 2015-03-25 | 苏州能屋电子科技有限公司 | Enhanced AlGaN/GaN HEMT device preparation method |
| CN106548939A (en) * | 2015-09-17 | 2017-03-29 | 苏州能屋电子科技有限公司 | The system and method for recessed grid enhancement mode HEMT device is realized by light auxiliary etch self-stopping technology |
| CN106548939B (en) * | 2015-09-17 | 2019-08-02 | 苏州能屋电子科技有限公司 | The system and method for the enhanced HEMT device of recessed grid is realized by light auxiliary etch self-stopping technology |
| CN106298887A (en) * | 2016-09-30 | 2017-01-04 | 中山大学 | A kind of preparation method of high threshold voltage high mobility notched gates MOSFET |
| CN106298887B (en) * | 2016-09-30 | 2023-10-10 | 中山大学 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
| CN109103249A (en) * | 2018-04-04 | 2018-12-28 | 北京大学 | A kind of high current GaN high electron mobility transistor optimizing plane figure and structure |
| CN113540231A (en) * | 2021-06-15 | 2021-10-22 | 西安电子科技大学 | P-GaN high electron mobility transistor based on in-situ growth MIS structure and preparation method |
| CN113707708A (en) * | 2021-07-26 | 2021-11-26 | 西安电子科技大学 | Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof |
| CN113707708B (en) * | 2021-07-26 | 2023-03-14 | 西安电子科技大学 | Junction accumulation layer enhanced AlGaN/GaN high electron mobility transistor and manufacturing method thereof |
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Application publication date: 20110601 |