CN105336789A - GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor - Google Patents
GaN-based field effect transistor with high quality MIS structure and preparation method of GaN-based field effect transistor Download PDFInfo
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- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 238000000407 epitaxy Methods 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 14
- 229910001020 Au alloy Inorganic materials 0.000 claims description 12
- 230000008569 process Effects 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000009413 insulation Methods 0.000 claims description 8
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000010301 surface-oxidation reaction Methods 0.000 claims description 5
- 229910017109 AlON Inorganic materials 0.000 claims description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 4
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- -1 AlON compound Chemical class 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 2
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 238000006385 ozonation reaction Methods 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 230000006872 improvement Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 2
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention belongs to the semiconductor material and device field and discloses a GaN-based field effect transistor with a high quality MIS structure and a preparation method of the GaN-based field effect transistor, in particular, a GaN MISFET device gate dielectric layer and an improvement method of a dielectric layer and GaN interface. The device includes a substrate, an epitaxial layer grown on the substrate as well as a gate electrode, a source electrode, a drain electrode and an insulating layer; the epitaxial layer includes a stress buffer layer which is formed through primary epitaxial growth, a GaN epitaxial layer as well as a second epitaxial layer and a third epitaxial layer which are grown on selective regions on the GaN epitaxial layer; a GaN/AlGaN heterostructure is formed through secondary epitaxial growth, and groove channels are formed; an AlN thin layer is formed through third epitaxial growth; the AlN thin layer is partially oxidized so as to form an AlN/oxide dielectric layer stack structure; gate metal covers the groove channels; a source electrode region and a drain electrode region are formed at two ends; and the source electrode region and the drain electrode region are covered with metal, so that the source electrode and the drain electrode can be formed. The device and preparation process of the invention are simple and reliable. With the preparation method adopted, the high quality MIS structure can be formed, and the performance of the GaN MISFET device can be improved. The preparation method can play a key role in decreasing the electric leakage of the gate electrode, decreasing the resistance of the channels and stabilizing threshold voltage.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, disclose a kind of high-quality GaN MISFET structure and preparation method thereof, be specifically related to GaNMISFET device grids dielectric layer and with the improving one's methods of GaN interface.
Background technology
GaN semi-conducting material has that energy gap is large, breakdown electric field is high, saturated electron drift velocity is large and the thermal conductivity superior performance such as high.GaN base device for power switching utilizes the two-dimensional electron gas work of AlGaN/GaN heterostructure interface place high concentration, high mobility usually, device is had conducting resistance is little, switching speed is fast advantage, becomes the ideal substitute of device for power switching of future generation.
The realization of high-performance normally-off switching device is the significant challenge that GaN power electronic device faces, and is the scientific and technological difficult point that academic circles at present and industrial circle are generally acknowledged.High-performance normally-off device not only requires to possess positive threshold voltage and high threshold voltage value, to simplify device peripheral circuit, to ensure thrashing safety, and will have stable threshold voltage, guarantee the work that device is reliable and stable.Adopt fluted body MIS grid structure to realize device often to close, wherein MIS grid are mainly in order to reduce grid leakage current, increase grid voltage scope.Thermal oxidation process can be adopted in Si base device to prepare high-quality Si/SiO
2mOS interfacial structure, but for GaN base device, the introducing of MIS grid adds some extra problems, as: interface charge, interfacial state, medium layer defect etc.It is not good that current preparation method obtains GaNMIS interface quality, causes existing in MIS interface system higher fixed charge and dielectric layer/GaN interface charge and interface state density.The bulk oxidation thing of the Ga existed at dielectric layer and GaN contact interface is the key factor causing high interfacial state, deteriorated device property.Grid is under different bias voltages, and these interfacial states and defect electric charge can carry out discharge and recharge, and cause the drift of threshold voltage, deteriorate the stability of devices function widely.Therefore find suitable method and prepare high-quality dielectric layer, reduce or remove dielectric layer/GaN interface Ga
2o
3generation, thus reducing interface state density, improve the performance of device, is especially very important to the reduction of MIS structure electric leakage of the grid and the improvement of threshold voltage stability problem.
Summary of the invention
The present invention is for overcoming at least one defect described in above-mentioned prior art, the object of the invention is mainly the quality improving the interface system that gate dielectric layer and GaN are formed in prior art, promote the insulation characterisitic of dielectric layer, reduce MIS interface state density, improve the mobility of area of grid channel electrons, a kind of normally-off GaNMISFET device and preparation method thereof that can realize high threshold voltage stability, low on-resistance, High Output Current density, high on-off ratio is provided.
The present invention can adopt molecular beam epitaxy (MBE) equipment to carry out three extensions to prepare high-quality AlN layer, and oxidation step of going forward side by side obtains high-quality insulating medium layer and makes MIS interface state density effectively be reduced simultaneously.Basic ideas are: in plasmaassisted MBE equipment, and GaN Surface Intrinsic oxide is removed in process in place, carries out surfaces nitrided process subsequently, then epitaxial growth high-quality AlN thin layer.Because AlN is easily thermally oxidized, generate high-quality Al by oxidation
2o
3(or AlON), controlled oxidization condition forms Al to retain the ultra-thin AlN layer of one deck
2o
3/ AlN/GaN gate stack structure.The method of this oxidation AlN had both prepared the Al of the low defect electric charge of high-quality
2o
3, turn avoid the Al of high interfacial state simultaneously
2o
3/ Ga
2o
3/ GaN interface.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of high-quality GaN MISFET structure and preparation method thereof, and the insulating barrier that surface oxidation generates one deck insulation oxide dielectric layer, two ends form source electrode and drain electrode, recess channel place that its structure comprises the groove that substrate, stress-buffer layer, GaN epitaxial layer, secondary epitaxy layer and secondary epitaxy formed, three epitaxial loayers, three epitaxial loayers from lower to upper is successively coated with grid.
U-shaped or the trapezoidal-structure of this groove.
Described substrate is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
Described stress-buffer layer is any one of AlN, AlGaN, GaN or combines; Stress buffer layer thickness is 100nm ~ 10 μm.
Described GaN epitaxial layer is GaN epitaxial layer or the doping high resistant GaN epitaxial loayer of involuntary doping, and the doped chemical of described doping resistive formation is carbon or iron; GaN epitaxial layer thickness is 100nm ~ 20 μm.
Described secondary epitaxy layer AlGaN/GaN heterostructure, AlGaN layer thickness is 5-50nm, and al composition varying concentrations, GaN layer thickness is 0-500nm.
Described AlGaN potential barrier material can also be a kind of or several arbitrarily combination in AlInN, InGaN, AlInGaN, AlN; AlGaN potential barrier in described secondary epitaxy layer and can also insert an AlN thin layer between GaN layer, thickness is 1-10nm.
Three times described epitaxial loayers are high-quality AlN layer, and thickness is 1-100nm; Described insulation oxide dielectric layer is Al
2o
3or AlON compound, thickness is 1-100nm; After the surface oxidation of general three epitaxial AlN layer forms one deck insulation oxide dielectric layer, the residual thickness of AlN layer controls at 0-5nm, forms AlN/ medium of oxides layer stacked structure.
Described source electrode and drain material include but not limited to Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy, and other various metal or alloy that can realize ohmic contact all can be used as source electrode and drain material; Grid material includes but not limited to Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Al/Ti/TiN alloy, and other various metal or alloy that can realize high threshold voltage all can be used as grid material.
A manufacture method for the GaN base field-effect transistor of described high-quality MIS structure, comprises the following steps:
S1, on a si substrate growth stress resilient coating;
S2, on stress-buffer layer growing GaN epitaxial loayer;
S3, in GaN epitaxial layer, deposit one deck SiO
2, as mask layer;
S4, method by photoetching, retain the mask layer formed on area of grid;
S5, selective area growth secondary epitaxy layer, form fluted body area of grid;
Mask layer on S6, removal area of grid;
S7, growth three epitaxial loayer AlN thin layers;
S8, oxidation form AlN/ medium of oxides layer stacked structure;
S9, dry etching complete device isolation, etch source electrode and drain ohmic contact region simultaneously;
S10, on source electrode and drain region evaporation source electrode and drain ohmic contact metal;
S11, on groove dielectric layer area of grid evaporation gate metal.
The growing method of the stress-buffer layer in described step S1 and the GaN epitaxial layer in step S2 and the secondary epitaxy layer in step S5 is Metalorganic Chemical Vapor Deposition, the contour quality film formation method of molecular beam epitaxy;
In described step S3, the growing method of mask layer is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method;
In described step S7, the growing method of three epitaxial loayer AlN thin layers is the contour quality film formation method of Metalorganic Chemical Vapor Deposition, molecular beam epitaxy or Atomic layer deposition method;
The method for oxidation of described step S8 is the mode of oxidizing such as high-temperature thermal oxidation method, oxygen plasma oxidizing process, Ozonation or solution oxide method.
Compared with prior art, beneficial effect is: the present invention proposes a kind of high-quality GaN MISFET structure and preparation method thereof, improve the performance of device, is especially very significant to the reduction of MIS structure electric leakage of the grid and the raising of threshold voltage stability.Device architecture of the present invention is simple, process repeatability and reliability high, high-quality insulating medium layer can be prepared, and reduce simultaneously or remove the generation of dielectric layer/GaN interface bulk oxidation thing, MIS interface state density is effectively reduced, improve the mobility of area of grid channel electrons, a kind of normally-off GaNMISFET device and preparation method thereof that can realize high threshold voltage stability, low on-resistance, High Output Current density, high on-off ratio is provided.
Accompanying drawing explanation
Fig. 1-11 is the device manufacture method process schematic representation of the embodiment of the present invention 1.
Figure 12 is the device architecture schematic diagram of the embodiment of the present invention 2.
Figure 13 is the device architecture schematic diagram of the embodiment of the present invention 3.
Embodiment
Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent; In order to better the present embodiment is described, some parts of accompanying drawing have omission, zoom in or out, and do not represent the size of actual product; To those skilled in the art, in accompanying drawing, some known features and explanation thereof may be omitted is understandable.Describe position relationship in accompanying drawing only for exemplary illustration, the restriction to this patent can not be interpreted as.
Embodiment 1
Be the device architecture schematic diagram of the present embodiment as shown in figure 11, its structure comprises substrate 1 from lower to upper successively, stress-buffer layer 2, GaN epitaxial layer 3, secondary epitaxy layer 4, secondary epitaxy forms groove, three epitaxial loayers 5, the surface oxidation of three epitaxial loayers 5 generates one deck insulation oxide dielectric layer 6, and two ends form source electrode 7 and drain electrode 8, and the insulating barrier 6 at recess channel place is coated with grid 9.
The manufacture method of the GaN base field-effect transistor of above-mentioned high-quality MIS structure, as shown in Fig. 1-Figure 10, comprises the following steps:
S1, utilize mocvd method, at Si substrate (1) upper growth one deck stress-buffer layer (2), as shown in Figure 1;
S2, utilize mocvd method, at the upper growing GaN epitaxial loayer (3) of stress-buffer layer (2), as shown in Figure 2;
S3, by plasma enhanced chemical vapor deposition one deck SiO
2, as mask layer (10), as shown in Figure 3;
S4, to be etched by photoetching method selected zone, retain the mask layer (10) on area of grid, as shown in Figure 4;
S5, utilize mocvd method, selective area growth secondary epitaxy GaN/AlGaN layer (4) on the substrate having mask layer (10), form groove grids, as shown in Figure 5;
S6, employing caustic solution, remove the mask layer (10) on area of grid, as shown in Figure 6;
S7, utilize molecular beam epitaxial method, high-quality three the extension AlN thin layers (5) of growth one deck, as shown in Figure 7;
S8, utilize plasma oxidation method, the oxidation of the AlN layer of three extensions is formed AlN/AlON dielectric layer (6) stacked structure, as shown in Figure 8;
S9, utilize ICP to complete device isolation, etch source electrode and drain ohmic contact region, as shown in Figure 9 simultaneously;
S10, on source electrode and drain region evaporation Ti/Al/Ni/Au alloy as source electrode (7) and drain electrode (8) metal ohmic contact, as shown in Figure 10;
S11, on the insulating barrier in groove grids region evaporation Ni/Au alloy as grid (9) metal, as shown in figure 11.
So far, the preparation process of whole device is namely completed.Figure 11 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
Be the device architecture schematic diagram of the present embodiment as shown in figure 12, itself and embodiment 1 structure are distinguished and are only: in embodiment 1, GaN/AlGaN heterostructure is that secondary epitaxy forms also self-assembling formation gate recess district simultaneously, and GaN/AlGaN heterostructure is that an extension is formed and utilizes dry method (or wet method) to etch formation gate recess district in embodiment 2, label 11 is an extension GaN/AlGaN hetero structure layers.
Embodiment 3
Be the device architecture schematic diagram of the present embodiment as shown in figure 13, itself and embodiment 1 structure are distinguished and are only: embodiment 1 is horizontal conducting type device architecture, and embodiment 2 is longitudinal conducting type device architecture.Substrate 12 is attached most importance to Doped GaN self-supported substrate or low-resistance silicon substrate or low-resistance silicon carbide substrates etc., and 13 is resilient coating, and 14 is light dope GaN drift layer, and 15 is GaN layer or the AlGaN layer of p-type doping.Adopt vertical structure, improve unit are chip power, effectively improve device electric breakdown strength etc.
In addition, it should be noted that, the accompanying drawing of above embodiment is only the object in order to illustrate, so there is no necessity and draws in proportion.
Obviously, the above embodiment of the present invention is only for example of the present invention is clearly described, and is not the restriction to embodiments of the present invention.Core content of the present invention is the Design & preparation of high-quality GaN base MIS interface system, the present invention only by means of several device architecture to carry out illustrating of correlation technique, and still feasible in the device solution of other similar process distortion, the thin barrier layer of such as AlGaN, p-type gate, F
-the modes such as injection all can be formed and often close structure, do not illustrate one by one at this.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description, technical scheme in each execution mode comprises the selection etc. of the selection of order of steps, material category and parameter, process and parameter, suitably can change combination, also can be appropriately combined between each embodiment, form other embodiments that it will be appreciated by those skilled in the art that.Here exhaustive without the need to also giving all execution modes.All any amendments done within the spirit and principles in the present invention, equivalent to replace and improvement etc., within the protection range that all should be included in the claims in the present invention.
Claims (10)
1. the GaN base field-effect transistor of a high-quality MIS structure, it is characterized in that, comprise substrate (1) from lower to upper successively, stress-buffer layer (2), GaN epitaxial layer (3), secondary epitaxy layer (4), secondary epitaxy forms groove, three epitaxial loayers (5), and the surface oxidation of three epitaxial loayers (5) generates one deck insulation oxide dielectric layer (6), two ends form source electrode (7) and drain electrode (8), and the insulating barrier (6) at recess channel place is coated with grid (9).
2. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, is characterized in that: the U-shaped or trapezoidal-structure of described groove.
3. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, is characterized in that: described substrate (1) is Si substrate, any one in Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
4. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, is characterized in that: described stress-buffer layer (2) is AlN, AlGaN, GaN any one or combination; Stress buffer layer thickness is 100nm ~ 10 μm.
5. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, it is characterized in that: the GaN epitaxial layer that a described growing GaN epitaxial loayer (3) is involuntary doping or the high resistant GaN epitaxial loayer of doping, the doped chemical of described doping resistive formation is carbon or iron; GaN epitaxial layer thickness is 100nm ~ 20 μm.
6. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, it is characterized in that: described secondary epitaxy layer (4) is AlGaN/GaN heterostructure, AlGaN layer thickness is 5-50nm, and al composition varying concentrations, GaN layer thickness is 0-500nm.
7. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 6, is characterized in that: described AlGaN potential barrier material can also for a kind of or several arbitrarily combination in AlInN, InGaN, AlInGaN, AlN.
8. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 5, is characterized in that: in described secondary epitaxy layer (4), can also insert an AlN thin layer between AlGaN potential barrier and GaN layer, thickness is 1-10nm.
9. the GaN base field-effect transistor of a kind of high-quality MIS structure according to claim 1, is characterized in that: three times described epitaxial loayers (5) are high-quality AlN layer, and thickness is 1-100nm; Described insulation oxide dielectric layer (6) is Al
2o
3or AlON compound, thickness is 1-100nm; After the surface oxidation of general three epitaxial AlN layer (5) forms one deck insulation oxide dielectric layer (6), the residual thickness of AlN layer (5) controls at 0-5nm, forms AlN/ medium of oxides layer stacked structure;
Source electrode (7) and drain electrode (8) material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; Grid (9) material is Ni/Au alloy, Pt/Al alloy, Pd/Au alloy or TiN/Ti/Al/Ti/TiN alloy.
10. a preparation method for the GaN base field-effect transistor of high-quality MIS structure according to claim 1, is characterized in that, comprise the following steps:
S1, at the upper growth stress resilient coating (2) of Si substrate (1);
S2, on stress-buffer layer growing GaN epitaxial loayer (3);
S3, in GaN epitaxial layer, deposit one deck SiO
2, as mask layer (10);
S4, method by photoetching, retain the mask layer (10) formed on area of grid;
S5, selective area growth secondary epitaxy layer (4), form fluted body area of grid;
Mask layer (10) on S6, removal area of grid;
S7, growth three epitaxial loayer AlN thin layers (5);
S8, oxidation form AlN/ medium of oxides layer (6) stacked structure;
S9, dry etching complete device isolation, etch source electrode and drain ohmic contact region simultaneously;
S10, on source electrode and drain region evaporation source electrode (7) and drain electrode (8) metal ohmic contact;
S11, on groove dielectric layer area of grid evaporation grid (9) metal;
The growing method of the stress-buffer layer (2) in step S1 and the GaN epitaxial layer (3) in step S2 and the secondary epitaxy layer (4) in step S5 is Metalorganic Chemical Vapor Deposition, the contour quality film formation method of molecular beam epitaxy; In described step S3, the growing method of mask layer (10) is plasma enhanced chemical vapor deposition method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method; In described step S7, the growing method of three epitaxial loayer AlN thin layers (5) is the contour quality film formation method of Metalorganic Chemical Vapor Deposition, molecular beam epitaxy or Atomic layer deposition method; The method for oxidation of described step S8 is the mode of oxidizing such as high-temperature thermal oxidation method, oxygen plasma oxidizing process, Ozonation or solution oxide method.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789315A (en) * | 2016-05-03 | 2016-07-20 | 中山大学 | AINGaN base field effect transistor of high quality MIS structure and manufacturing method thereof |
| CN106206297A (en) * | 2016-09-05 | 2016-12-07 | 中山大学 | A kind of selective area epitaxial high-quality AlGaN/GaN growing method |
| CN106373884A (en) * | 2016-09-08 | 2017-02-01 | 西安电子科技大学 | Fabrication method for transistor with composite gate dielectric GaN-based insulating gate and high electron mobility |
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| CN107742644B (en) * | 2017-10-30 | 2024-05-28 | 中山大学 | High-performance normally-off GaN field effect transistor and preparation method thereof |
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