JP2007281453A - Semiconductor field effect transistor, and method for manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gallium nitride based field effect transistor that is excellent in current hysteresis characteristics and is capable of decreasing a forward gate leak. <P>SOLUTION: In the gallium nitride based field effect transistor 100 having a gate insulating film 108, a part or the whole of a material composing the gate insulating film 108 is a dielectric with dielectric constant of 9 or more and 22 or less, and a heterojunction is composed of a semiconductor crystal layer A104 that contacts the gate insulating film 108, and a semiconductor crystal layer B103 that adjoins the semiconductor crystal A104 and has electron affinity bigger than that of the semiconductor crystal layer A104. It is preferable that a part or the whole of the material composing the gate insulating film 108 is designed to contain hafnium oxide such as HfO<SB>2</SB>, HfAlO, HfAlON or HfSiO. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor field effect transistor, a semiconductor integrated circuit, and a manufacturing method thereof.

  Field effect transistors are widely used as electronic components such as amplifiers and switches, and are classified into several types according to the form of a current path (channel). Although one type uses a two-dimensional electron gas (2DEG), a field effect transistor using 2DEG is divided into two types depending on the form of the interface forming the 2DEG. One is formed at the oxide film / semiconductor crystal interface, and the other is formed at the same semiconductor crystal / semiconductor crystal interface. A typical example of the former is a Si-MOS field effect transistor, and a typical example of the latter is a GaN-based high electron mobility field effect transistor (GaN-HEMT).

  The Si-MOS field effect transistor is configured to form a channel with reversed polarity at the Si oxide film / Si semiconductor crystal interface by controlling the gate bias. If applied to a positive voltage), more carriers can be induced at the interface within the range of the breakdown voltage of the oxide film, and a higher current density can be obtained. Yes. However, since electrons travel through different interfaces of the crystal system, they are scattered by the disorder of the crystal lattice at the interface, and sufficient electron travel speed cannot be obtained, and there is a limit to amplification of high-frequency signals and high-speed switching. Has a problem.

On the other hand, in the case of GaN-HEMT, an AlGaN layer and a GaN layer, which are similar semiconductor crystals having different affinities, are joined to induce carriers at the joining interface to form a channel. Since this interface is a heterojunction interface of similar crystals, electron scattering is small and a high electron traveling speed can be realized, which is suitable for amplification of high-frequency signals and high-speed switching. However, in the case of GaN-HEMT, it is almost impossible to improve the drain current density by applying a forward gate bias. This is because the difference in electron affinity between similar crystals is small, and so-called gate leakage occurs in which induced carriers easily pass through the crystal with low electron affinity and flow into the gate electrode. In order to improve this problem, a technique for increasing the difference in electron affinity between the AlGaN layer and the GaN layer by increasing the Al composition of the AlGaN layer is known (Non-Patent Document 1). As another method for reducing the forward gate leakage, a method of stacking a film made of a material having an electron affinity smaller than that of the semiconductor crystal layer is also known (Non-patent Document 2).
Masataka higashiwaki et al., Japanese journal of applied physics, Vol44.No16,2005 Narihiko maeda et al., Applied physics letter 87,073504,2005

  However, according to the method of increasing the Al composition of the AlGaN layer, problems such as an increase in alloy dispersion at the interface and deterioration of crystallinity due to the expansion of lattice mismatch at the interface occur, and the expected effect cannot be obtained.

  Also, according to the method of laminating a film made of a material having an electron affinity smaller than that of the semiconductor crystal layer in contact with the semiconductor crystal layer, the reverse leakage current can be greatly reduced, but the effect of reducing the forward leakage current is Therefore, a sufficient forward gate bias cannot be applied, and there is a limit to practical use.

  Thus, according to the prior art, it has been difficult to produce a field effect transistor having a high electron traveling speed, a high gain, and a high drain current density.

  An object of the present invention is to provide a high-performance gallium nitride field effect transistor that can solve the above-mentioned problems in the prior art.

  Another object of the present invention is to provide a gallium nitride field effect transistor that has good current hysteresis characteristics and can reduce forward gate leakage.

  Another object of the present invention is to provide a gallium nitride field effect transistor capable of realizing a high electron velocity, a high gain, and a high drain current density.

  In order to solve the above problems, a field effect transistor according to the present invention uses carriers induced at a heterointerface between a gallium nitride semiconductor crystal layer A and a semiconductor crystal layer B as a channel. A gate insulating film is provided between the gate electrode and at least a part of the material of the gate insulating film contains hafnium oxide.

  According to the first aspect of the present invention, there is provided a gallium nitride field effect transistor having a gate insulating film, wherein the semiconductor crystal layer A is in contact with the gate insulating film, and has a higher electron affinity than the semiconductor crystal A. And has a heterojunction composed of a semiconductor crystal layer B provided close to the semiconductor crystal layer A, and a part or all of the material constituting the gate insulating film has a relative dielectric constant of 9 or more and 22 A semiconductor field effect transistor characterized by the following dielectric is proposed.

According to the invention of claim 2, in the invention of claim 1, the semiconductor crystal layer A is an Al _x In _y Ga _(1-xy) N-based crystal (0 ≦ x, y ≦ 1, x + y ≦ 1). A semiconductor field effect transistor is proposed.

  According to a third aspect of the invention, there is proposed a semiconductor field effect transistor according to the first or second aspect of the invention, wherein a part or all of the material constituting the gate insulating film contains hafnium oxide.

According to a fourth aspect of the present invention, in the first, second, or third aspect of the present invention, part or all of the material constituting the gate insulating film is Hf _x Al _1-x O _y (0 <x <1, 1 A semiconductor field effect transistor including ≦ y ≦ 2) is proposed.

  According to the invention of claim 5, in the invention of claim 1, 2, 3, or 4, the thickness of the lower part of the gate of the semiconductor layer A is thinner than the thickness of other parts of the semiconductor layer A A field effect transistor is proposed.

  According to the invention of claim 6, there is proposed a semiconductor integrated circuit characterized in that the semiconductor field effect transistor according to any one of claims 1 to 5 is a constituent element.

  According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor field effect transistor according to any one of the first to fifth aspects, a heat treatment is performed at 300 ° C. or higher after forming the gate insulating film. A method of manufacturing a field effect transistor is proposed.

  According to an eighth aspect of the present invention, there is proposed a method for manufacturing a semiconductor field effect transistor according to the seventh aspect of the present invention, wherein the heat treatment is performed after the formation of the gate electrode.

  According to a ninth aspect of the present invention, in the seventh or eighth aspect of the present invention, the semiconductor field effect transistor further comprises a step of making the thickness of the lower part of the gate of the semiconductor layer A thinner than the thickness of the other part of the semiconductor layer A. A manufacturing method is proposed.

  According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor field effect transistor according to the first, second, third, fourth, fifth, seventh, eighth or ninth aspect, wherein the semiconductor layer is in contact with a gate metal or a gate insulating film. A method for manufacturing a semiconductor field effect transistor is proposed, which includes a step of exposing the surface of the substrate to a plasma containing at least a chlorine-based gas.

  According to the invention of claim 11, in the method of manufacturing a semiconductor integrated circuit according to claim 6, after the gate insulating film is formed, a heat treatment is performed at 300 ° C. or higher. Is proposed.

  According to a twelfth aspect of the invention, there is proposed a method of manufacturing a semiconductor integrated circuit according to the eleventh aspect of the invention, wherein the heat treatment is performed after the formation of the gate electrode.

  According to a thirteenth aspect of the present invention, in the semiconductor device according to the eleventh or twelfth aspect, the semiconductor integrated circuit further includes a step of making the thickness of the lower portion of the gate of the semiconductor layer A thinner than the thickness of other portions of the semiconductor layer A. A circuit manufacturing method is proposed.

  According to a fourteenth aspect of the present invention, there is provided the semiconductor integrated circuit manufacturing method according to the sixth, eleventh, twelfth or thirteenth aspect of the present invention, wherein the semiconductor layer surface in contact with the gate metal or the gate insulating film is plasma containing at least a chlorine-based gas. A method for manufacturing a semiconductor integrated circuit is proposed, which is characterized by exposure to the following.

  According to the present invention, a gate insulating film having a high mobility and an optimum dielectric constant is disposed on the surface of the crystal layer by forming the channel layer at the interface of the semiconductor crystal layer with the same electron scattering property. Thus, a high-performance field effect transistor that can apply a large forward gate bias and thereby realize a very large drain current density can be provided, and its industrial significance is extremely great.

Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional view of an example of an embodiment of a field effect transistor according to the present invention. In this embodiment mode, a case of a semiconductor integrated circuit in which a plurality of GaN-HEMTs, which are gallium nitride field effect transistors having a gate insulating film according to the present invention, are formed over a base substrate 101 will be described as an example. However, the present invention is not limited to the GaN-HEMT, and is not limited to the semiconductor integrated circuit.

  The semiconductor integrated circuit 1 shown in FIG. 1 includes a plurality of field effect transistors 100 according to the present invention formed on a base substrate 101. In FIG. 1, only one field effect transistor 100 is shown for simplicity. Has been. Of course, various devices other than the field effect transistor 100 may be provided in the semiconductor integrated circuit 1, but a configuration in which only a plurality of field effect transistors 100 are provided may be employed. Here, the field effect transistor 101 is configured as a GaN-HEMT which is a gallium nitride field effect transistor.

  Hereinafter, the configuration and operation of one field effect transistor 100 will be described with reference to FIG. 1, but the same applies to other field effect transistors not shown. The field effect transistor 100 is formed on a substrate in which a buffer layer 102 is formed on a base substrate 101.

  As the base substrate 101, a single crystal substrate having a small or almost no lattice multiplier difference with an epitaxial layer formed on the base substrate 101, such as a SiC substrate, a sapphire substrate, a Si substrate, or a GaN substrate, can be used. . The base substrate 101 is preferably semi-insulating, but may be used even if it is conductive. Various sizes are available on the market, but there is no limit on the size. Various off-angles and off-azimuths are commercially available, but there is no limitation on them, and any one can be used. The surface orientation of the base substrate 101 can be used with no limitation on whether it is a polar surface or a nonpolar surface. As described above, a commercially available substrate can be used as the base substrate 101.

  The buffer layer 102 provided on the base substrate 101 reduces strain caused by a difference in lattice constant between the various semiconductor crystal layers provided on the base substrate 101 and the base substrate 101, and the base substrate 101. It has been introduced for the purpose of preventing the influence of impurities contained in. As the material of the buffer layer 102, AlN, AlGaN, GaN or the like can be used. The buffer layer 102 can be formed by stacking these materials on the base substrate 101 by the MOVPE method, the MBE method, the HVPE method, or the like. As the raw material to be used, since a raw material suitable for each growth method is commercially available, it is preferable to use this. Although there is no restriction | limiting in particular in the thickness of the buffer layer 102, Usually, it is the range of 3000 to 20 micrometers.

  A semiconductor crystal layer B103 is formed on the buffer layer 102, and another semiconductor crystal layer A104 is formed on the semiconductor crystal layer B103. The semiconductor crystal layer A104 is in contact with the gate insulating film 108, has a higher electron affinity than the semiconductor crystal layer A104, and forms a heterojunction with the semiconductor crystal layer B103 provided close to the semiconductor crystal layer A104. ing. In the example shown in FIG. 1, one surface of the semiconductor crystal layer B103 is in direct contact with one surface of the semiconductor crystal layer A104, and the interface between the semiconductor crystal layer B103 and the semiconductor crystal layer A104 when a gate bias is applied. Thus, a channel can be formed on the semiconductor crystal layer B103 side.

  In order to form the channel, the semiconductor crystal layer B103 needs to have higher electron affinity than the semiconductor crystal layer A104. Hereinafter, the two semiconductor crystal layers B103 and the semiconductor crystal layer A104 provided to constitute the channel will be described in detail.

  GaN can be used as the material of the semiconductor crystal layer B103. The semiconductor crystal layer B103 can be stacked using the MOVPE method, the MBE method, the HVPE method, or the like, as in the case of the buffer layer 102. The raw material to be used can be used since the raw material is commercially available according to each growth method, as in the case of the buffer layer 102. The thickness of the semiconductor crystal layer B103 is not particularly limited, but is in the range of 3000 to 5 μm, more preferably in the range of 5000 to 3 μm, and still more preferably in the range of 700 to 2 μm.

  The semiconductor crystal layer A104 can be formed by crystal growth of AlGaN or AlInGaN on the semiconductor crystal layer B103, and the crystal growth method of the semiconductor crystal layer B103 is the same as that of the semiconductor crystal layer B103. When AlGaN is grown as the semiconductor crystal layer A104, a lattice constant difference is generated between the semiconductor crystal layer B103 and the semiconductor crystal layer A104, thereby generating a piezo electric field, which is an interface at the side of the semiconductor crystal layer B103 ( Free carriers can be induced on the GaN layer side).

  On the other hand, when AlInGaN is grown as the semiconductor crystal layer A104, the composition ratio of Al and In is adjusted, and the semiconductor crystal layer B103 and the semiconductor crystal layer A104 are lattice-matched to prevent the generation of a piezoelectric field, A field effect transistor can be manufactured in a state where free carriers are not generated at zero gate bias and a channel is not formed, that is, an E-mode operation.

  The semiconductor crystal layer A104 of the field effect transistor according to the present invention may be any, but in any case, a channel is formed on the semiconductor crystal layer B103 side of the interface between the semiconductor crystal layer B103 and the semiconductor crystal layer A104 when a gate bias is applied. It is important to select a material system and a composition so that the semiconductor crystal layer B103 has an electron affinity higher than that of the conductor crystal layer A104.

  In the semiconductor crystal layer A104, the Al composition is preferably increased so that the semiconductor crystal layer A104 has a sufficiently small electron affinity compared to the semiconductor crystal layer B103. However, as described above, if the Al composition is increased, the crystallinity of the AlGaN layer is deteriorated, and the performance of the obtained field-effect transistor is deteriorated or malfunctions. It is necessary to choose the optimum value. For these reasons, the Al composition range is usually preferably 0.1 to 0.6, more preferably 0.15 to 0.5, and still more preferably 0.2 to 0.4. It is a range.

  The semiconductor crystal layer A104 can be stacked using the MOVPE method, the MBE method, the HVPE method, or the like, similarly to the buffer layer 102 and the semiconductor crystal layer B103. Since the raw material to be used is commercially available according to each growth method, it is preferable to use this. The thickness of the semiconductor crystal layer A104 is not particularly limited, but is in the range of 30 to 600 mm, more preferably in the range of 100 to 500 mm, and still more preferably in the range of 150 to 400 mm.

  In this embodiment mode, the semiconductor crystal layer A104 is a single layer. However, the semiconductor crystal layer A104 may have a repeated stacked structure of a GaN layer and an AlGaN layer having a thickness within the elastic deformation limit, or a repeated stacked structure of InGaN and AlGaN.

  On the semiconductor crystal layer A 104, a source electrode 105 and a drain electrode 106 are formed, and a gate electrode 109 is formed via a gate insulating film 108. Reference numeral 107 denotes an isolation layer for element isolation. By providing the isolation layer 107, the plurality of field effect transistors 100 having the above-described layer structure on the substrate do not interfere electrically with each other. It is formed in this way.

  By providing the gate insulating film 108, a leakage current when a forward bias voltage is applied to the gate electrode 109 can be reduced, so that a large forward voltage can be applied. In this case, the leakage current can be suppressed as the thickness of the gate insulating film 108 is increased. However, when the thickness of the gate insulating film 108 is increased, electrons are formed at the interface between the gate insulating film 108 and the semiconductor crystal layer A104. The intermediate level is easily formed, causing current hysteresis.

  Therefore, as a result of intensive studies on the material of the gate insulating film of the gallium nitride field effect transistor, the present inventor has suppressed the generation of current hysteresis by using a material containing hafnium oxide as the material of the gate insulating film. The present inventors have found that a high-performance gallium nitride field effect transistor that can reduce the leakage current when a forward bias voltage is applied can be realized.

On the semiconductor crystal layer A104, a dielectric having a dielectric constant greater than 9 and less than or equal to 22 is formed as a gate insulating film. When deviating from this range, the forward leakage current cannot be effectively suppressed. A dielectric having a relative dielectric constant of 9 or more and 22 or less is effective, but even in this range, the range of 13 to 18 is more preferable for reducing gate leakage. Materials having a dielectric constant greater than 9 and less than or equal to 22 include Cr ₂ O ₃ , CuO, FeO, PbCO ₃ , PbCl ₂ , PbSO ₄ , SnO ₂ , ZrO ₂ , ZrSiO ₄ , Ta ₂ O ₅ , TiO ₂ , BaTiO, There are HfSiO ₂ , HfAlO, La ₂ O ₃ , CaHfO, HfAlON, and the like. All of these material systems are effective, but La ₂ O ₃ , CuO, ZrSiO ₄ , HfSiO ₂ , HfO ₂ , HfAlO, and CaHfO are more preferable, and HfO ₂ , HfAlON, HfAlO and HfSiO are more preferable, and HfAlO is most preferable.

  The crystal system of these materials is preferably amorphous or single crystal for use as the gate insulating film 108 for reasons such as small leakage, and more preferably amorphous for ease of film formation.

As described above, when part or all of the material forming the gate insulating film 108 contains hafnium oxide, for example, part or all of the material forming the gate insulating film is Hf _x Al _1-x O _y (0 < When x <1, 1 ≦ y ≦ 2), the leakage current can be effectively reduced and the adjustment can be made possible.

  The gate insulating film 108 may have a stacked structure of the above material and another material. For example, a stacked structure in which SiN, which is known as an insulating film capable of suppressing the current collapse phenomenon, is inserted with a thickness of 1 nm to 10 nm between the above materials exemplified as being usable for the gate insulating film 108. Can be adopted. In this case, there is no limitation on the type of insulating film material to be combined. The thickness is preferably in the range of 3 nm to 40 nm, more preferably in the range of 5 nm to 30 nm, and most preferably in the range of 7 nm to 20 nm in consideration of effective leakage current suppression, mutual conductance, hysteresis, and the like.

  Alternatively, a structure (recess structure) in which part of the semiconductor crystal layer B103 and / or the semiconductor crystal layer A104 is removed by etching may be used. Thus, the E-mode operation can be performed by improving the gain of the field effect transistor or adjusting the threshold voltage to be positive.

  As a method for forming the gate insulating film 108, a thermal CVD method, a plasma CVD method, an ALCVD method, an MOCVD method, an MBE method, an evaporation method, a sputtering method, or the like can be used.

  After forming the gate insulating film 108 by these methods, the current hysteresis can be reduced by annealing. Therefore, when the semiconductor integrated circuit 1 shown in FIG. 1 is manufactured, or when the field effect transistor 100 having the configuration shown in FIG. 1 is manufactured alone, the gate insulating film 108 is formed in order to improve the current hysteresis characteristics. Thereafter, it is effective to perform an annealing treatment.

  This annealing process may be performed at an appropriate timing between the formation of the gate insulating film 108 and the device sealing. The annealing treatment is performed at a temperature of 300 ° C. or higher and within the heat resistance range of the gate insulating film 108 (a range in which the amorphous state can be maintained), but is usually in the range of 300 ° C. to 900 ° C. By performing the annealing temperature in the range of 300 ° C. to 900 ° C., the current hysteresis characteristics can be further improved as compared with the case where the annealing is not performed. The annealing treatment time is not particularly limited, but is preferably in the range of 10 seconds to 60 minutes from the viewpoint of balance between effects and industrial efficiency. The atmosphere is preferably nitrogen and / or Ar, more preferably nitrogen.

  As materials for the gate electrode 109, the source electrode 105, and the drain electrode 106 formed on the gate insulating film 108, materials and methods used in ordinary GaN-HEMT devices can be used as they are. That is, the material of the gate electrode 108 is Ni / Au, Pt, or the like. The material of the source electrode 105 and the drain electrode 106 is Ti / Al, Ti / Mo, or the like. Their formation can be performed by sputtering, vapor deposition, CVD, or the like.

  The annealing process may be performed after the gate electrode is formed. In that case, the process is performed in a temperature range in which hysteresis can be reduced and the gate electrode material is not damaged. Such a temperature range is determined in consideration of the heat resistance of the gate electrode material, but is generally in the range of 300 to 600.

  In the above, the present invention has been described based on an example of the embodiment. However, the embodiment of the present invention disclosed above is merely an example, and the technical scope of the present invention is limited to these embodiments. It is not limited. The technical scope of the present invention is defined by the scope of claims, and further includes the meaning equivalent to the description of the scope of claims and all modifications within the scope.

  The present invention will be described in more detail with reference to the following examples. However, the examples shown below are merely examples, and the present invention is not limited thereto.

Example 1
A GaN-HEMT having the configuration shown in FIG. 1 was prepared as follows.
A semi-insulating SiC substrate prepared as the base substrate 101 is cleaned with a mixed solution of sulfuric acid and hydrogen peroxide solution, and then heated to 600 ° C. in a MOCVD furnace, and hydrogen is 60 SLM, ammonia is 40 SLM as a carrier gas, TMA was flowed at 40 sccm from a container set to a constant temperature bath temperature of 30 ° C., and AlN was grown as a buffer layer 102 to grow 500 kg.

  Next, the temperature of the base substrate 101 is changed to 1150 ° C., the TMA flow rate is set to 0 sccm, TMG is flowed from a container set to a constant temperature bath temperature of 30 ° C., and 40 μcm of TMG is flown over the buffer layer 102 as a semiconductor crystal layer B103 to 2 μm Laminated.

  Next, the flow rate of TMG was changed to 100 sccm, TMA was flown from a vessel having a high temperature bath temperature of 30 ° C., and 33 μcm of ud-AlGaN having an Al composition of 0.20 was grown as a semiconductor crystal layer A104. Next, after the temperature of the base substrate 101 was lowered to near room temperature, it was taken out from the reaction furnace.

  Thereafter, resist openings were formed in the shape of the source electrode and the drain electrode by a photolithography method, and a Ti / Al / Ni / Au metal film was laminated to a thickness of 200 / 1,500 / 250/500 by EB vapor deposition. Subsequently, the metal film other than the opening was removed by a lift-off method to form the source electrode 105 and the drain electrode 106. Subsequently, RTA treatment was performed at 800 ° C. for 30 seconds in a nitrogen atmosphere in order to improve ohmic properties.

After the substrate was taken out and a resist pattern was formed by photolithography, the separation layer 107 was formed to a depth of 3000 mm by using this as a mask and ion implantation of N ⁺ ions. The dose amount of N ⁺ ions was 2 × 10 ¹⁴ / cm ² . After the ion implantation, the resist was removed.

Thereafter, a resist opening was provided in a region where a gate insulating film was to be formed by photolithography, and the opening was then washed with a diluted HCl aqueous solution. Transferred to a sputtering apparatus, an RF sputtering method to deposit the Hf _0.6 Al _0.4 O _2. Regarding the film thickness, samples of three levels of 8 nm (sample 1), 16 nm (sample 2), and 24 nm (sample 3) were produced. Ar was used as a gas for sputtering the base substrate 101. The sputtering power was 0.48 kW. The reactor pressure during sputtering was 0.45 Pa. As a sputtering target, a sintered body of Hf _0.6 Al _0.4 O ₂ was used. Thereafter, a gate insulating film 108 was formed by lift-off.

  Next, after forming a gate electrode-shaped opening by the same photolithography method, a Ni / Au metal film is formed to a thickness of 200 mm / 1000 mm by electron beam evaporation, and lifted off by the same method as the source electrode. 109 was formed.

  Next, the base substrate 101 treated as described above was transferred to an annealing furnace and annealed in nitrogen at 500 ° C. for 30 minutes.

  In this way, three GaN-HEMTs, GaN-HEMT1 (gate insulating film 8 nm), GaN-HEMT2 (gate insulating film 16 nm), which have a gate length of 2 μm and a gate width of 30 μm but differ only in the thickness of the gate insulating film, GaN-HEMT3 (gate insulating film 24 nm) was produced.

  CV measurement was performed on the Schottky diode manufactured by the same processing process for GaN-HEMT1, and the relative dielectric constant of the gate insulating film was determined to be 16.

  For each of the GaN-HEMT1, GaN-HEMT2, and GaN-HEMT3 produced as described above, the gate current density-gate voltage characteristics were measured under the condition that the drain electrode is grounded and has two terminals. The measurement results are shown in FIG.

  Furthermore, the transition characteristics of the drain current density were measured for each of GaN-HEMT1, GaN-HEMT2, and GaN-HEMT3 under the condition that the source electrode is grounded and three terminals. At this time, a bias of 20 V was applied to the drain electrode. The measurement results are shown in FIG.

  The hysteresis characteristic of the drain current density-drain voltage curve of GaN-HEMT1 was measured. At this time, −2 V was applied to the gate electrode. The measurement results are shown in FIG.

(Comparative Example 1)
FIG. 2 is a schematic cross-sectional view of a semiconductor integrated circuit including a GaN-HEMT manufactured as a comparative example. The structural difference between the embodiment of the present invention shown in FIG. 1 and the comparative example shown in FIG. 2 is that the gate insulating film is not provided in each field effect transistor in the comparative example. The other structures are the same for both. In FIG. 2, 201 is a base substrate, 202 is a buffer layer, 203 is a semiconductor crystal layer B, 204 is a semiconductor crystal layer A, 205 is a source electrode, 206 is a drain electrode, 207 is a separation layer, and 208 is a gate electrode.

  In the same manner as in Example 1, a SiC substrate is used as a base substrate 201, an AlN layer is formed as a buffer layer 202 to a thickness of 500 mm, and a GaN layer is formed as a semiconductor crystal layer B203 to a thickness of 2 μm. Then, a ud-AlGaN layer having an Al composition of 0.20 was formed as a semiconductor crystal layer A204 with a thickness of 400 mm. Next, after the temperature of the base substrate 201 processed as described above was lowered to near room temperature, it was taken out from the reactor as an epitaxial substrate.

  After the source electrode 205, the drain electrode 206, and the separation layer 207 are formed on the epitaxial substrate taken out from the reaction furnace by the same method as in Example 1, an opening is formed in the gate electrode shape by the lithography method without stacking the gate insulating film. The opening was washed with diluted aqueous HCl. Next, the gate electrode 208 was formed by the same method as in Example 1. In this way, a GaN-HEMT 4 having a gate length of 2 μm and a gate width of 30 μm was produced.

  For this GaN-HEMT4, the gate current density-gate voltage characteristics were measured under the condition of two terminals with the drain electrode grounded. The measurement results are shown in FIG.

  Further, for GaN-HEMT4, the transition characteristics of the drain current density were measured under the condition of three terminals with the source electrode grounded. At this time, a bias of 20 V was applied to the drain electrode. The measurement results are shown in FIG.

(Comparative Example 2)
In the same manner as in Example 1, on the SiC substrate as the base substrate 201, the AlN buffer layer 202 is 500 mm, the GaN semiconductor crystal layer B203 is 2 μm, and the ud-AlGaN semiconductor crystal layer A204 is Al composition 0.20. 400 liters of growth.

  Next, the separation layer 207, the source electrode 205, the drain electrode 206, the gate insulating film (thickness 8 nm), and the gate electrode 208 are formed on the base substrate 201 processed as described above in the same manner as in Example 1, and then required. The electrode was formed. Annealing treatment was not performed. In this way, a GaN-HEMT5 having a gate length of 2 μm and a gate width of 30 μm was produced.

  The hysteresis characteristic of the drain current density-drain voltage curve of GaN-HEMT5 was measured. At this time, −2 V was applied to the gate electrode. The measurement results are shown in FIG.

  Referring to FIG. 3, the gate current of GaN-HEMT1, GaN-HEMT2, and GaN-HEMT3 produced in Example 1 was significantly reduced as compared with GaN-HEMT4 of Comparative Example 1. In particular, it can be seen that the effect of suppressing the gate current when applying a forward gate bias is remarkably improved. As can be seen from FIG. 3, the forward voltage application width can be expanded to + 8V for GaN-HEMT1 and GaN-HEMT2, and to + 9V for GaN-HEMT3.

  On the other hand, in the GaN-HEMT4, when the gate voltage exceeds 0V, a large leak current is generated, so that a gate voltage higher than 0V cannot be applied.

  Referring to FIG. 4, when each maximum drain current density of GaN-HEMT1, GaN-HEMT2, and GaN-HEMT3 of Example 1 is compared with that of GaN-HEMT4 of Comparative Example 1, it is about 95% in GaN-HEMT1. GaN-HEMT2 improved by 105% and GaN-HEMT3 improved by 115%.

  The difference when the sweep direction of the drain current density-drain voltage curve of the GaN-HEMT 1 of Example 1 in FIG. 6 is changed is significantly smaller than that in the GaN-HEMT 4 shown in FIG. It was confirmed that was significantly reduced.

(Example 2)
A GaN-HEMT having the configuration shown in FIG. 7 was prepared as follows. In addition, the same code | symbol is attached | subjected to the part corresponding to each part of FIG. 1 among each part of FIG. From the cleaning of the base substrate 101 to N + implantation by the same method as shown in Example 1, a resist opening was provided in the region where the gate insulating film was formed by the same method as in Example 1.

  Thereafter, the substrate was transferred to an ICP plasma apparatus, and the semiconductor substrate exposed to the opening was etched with a discharge gas (plasma) of a mixed gas of argon, dichloromethane (CH2Cl2), and chlorine. That is, etching was performed by exposing the surface of the semiconductor crystal layer A104, which is a semiconductor layer in contact with the gate metal or the gate insulating film, to plasma containing at least a chlorine-based gas. At that time, etching was performed so that the thickness of the semiconductor crystal layer A104 in the portion where the gate insulating film 108 is provided is thinner than the thickness of the other portion of the semiconductor crystal layer A104. By such an etching process, a step of making the thickness of the lower part of the gate of the semiconductor crystal layer A104 thinner than the thickness of the other part of the semiconductor crystal layer A104 is performed. As a result, at the position where the gate electrode 109 of the semiconductor crystal layer B103 is provided. A recess was formed.

  Thereafter, the substrate is taken out from the ICP plasma apparatus, and after taking out the substrate, a gate insulating film and a gate electrode are formed by the same method as shown in Example 1, and then the same processing as shown in Example 1 is performed, -HEMT5 was produced. Therefore, in the case of Example 2, as shown in FIG. 7, the gate insulating film 108 is formed in the recess formed at the position where the gate electrode 109 of the semiconductor crystal layer A104 is disposed, and the gate insulation in the recess is formed. A gate electrode 109 is formed on the film 108. In the example of FIG. 7, the lower portion of the gate electrode 109 is formed in the recess, and the upper portion of the gate electrode 109 is projected from the surface of the semiconductor crystal layer A104.

  The transition characteristics of the drain current density of the GaN-HEMT of Example 2 obtained in this way were evaluated. The drain current density was zero at a gate voltage of 0 V (intrinsic enhancement mode). The threshold voltage was + 1.9V. Further, the maximum current density was 273 mA / mm at a gate voltage of +3.6 V, and showed a very large value as a GaN-HEMT having the characteristic of the intrinsic enhancement mode.

1 is a schematic sectional view showing an embodiment of the present invention. The schematic sectional drawing of the device of a comparative example. The figure which shows the gate current density-gate voltage characteristic of Example 1 and Comparative Example 1. The figure which shows the transition characteristic of the drain current density of Example 1 and Comparative Example 1. The figure which shows the hysteresis characteristic of the drain current-drain voltage curve of the comparative example 2. FIG. 4 is a diagram illustrating hysteresis characteristics of a drain current-drain voltage curve according to the first embodiment. FIG. 4 is a schematic cross-sectional view of a device according to Example 2.

Explanation of symbols

101, 201 Base substrate 102, 202 Buffer layer 103, 203 Semiconductor crystal layer B
104, 204 Semiconductor crystal layer A
105, 205 Source electrode 106, 206 Drain electrode 107, 207 Separation layer 108 Gate insulating film 109, 208 Gate electrode

Claims (14)

A gallium nitride field effect transistor having a gate insulating film,
A heterojunction comprising a semiconductor crystal layer A in contact with the gate insulating film and a semiconductor crystal layer B having a higher electron affinity than the semiconductor crystal A and provided in the vicinity of the semiconductor crystal layer A Have
A semiconductor field effect transistor, wherein a part or all of a material constituting the gate insulating film is a dielectric having a relative dielectric constant of 9 or more and 22 or less. The semiconductor field effect transistor according to claim 1, wherein the semiconductor crystal layer A is an Al _x In _y Ga _(1-xy) N-based crystal (0 ≦ x, y ≦ 1, x + y ≦ 1).   3. The semiconductor field effect transistor according to claim 1, wherein a part or all of a material constituting the gate insulating film contains hafnium oxide. 4. The semiconductor field effect according to claim 1, wherein a part or all of a material constituting the gate insulating film includes Hf _x Al _1-x O _y (0 <x <1, 1 ≦ y ≦ 2). Transistor.   5. The semiconductor field effect transistor according to claim 1, wherein a thickness of a lower portion of the gate of the semiconductor layer A is thinner than thicknesses of other portions of the semiconductor layer A. 6.   6. A semiconductor integrated circuit comprising the semiconductor field effect transistor according to claim 1 as a constituent element.   6. The method of manufacturing a semiconductor field effect transistor according to claim 1, wherein a heat treatment is applied at 300 [deg.] C. or higher after forming the gate insulating film.   The method of manufacturing a semiconductor field effect transistor according to claim 7, wherein the heat treatment is performed after forming the gate electrode.   9. The method of manufacturing a semiconductor field effect transistor according to claim 7, further comprising a step of making a thickness of a lower part of the gate of the semiconductor layer A thinner than a thickness of another part of the semiconductor layer A. 10.   10. The method of manufacturing a semiconductor field effect transistor according to claim 1, wherein the surface of the semiconductor layer in contact with the gate metal or the gate insulating film is at least chlorine-based gas. A method for producing a semiconductor field effect transistor, comprising the step of exposing to a plasma containing the semiconductor field effect transistor.   7. The method for manufacturing a semiconductor integrated circuit according to claim 6, wherein after the gate insulating film is formed, heat treatment is performed at 300 [deg.] C. or higher.   12. The method of manufacturing a semiconductor integrated circuit according to claim 11, wherein the heat treatment is performed after forming the gate electrode.   13. The method of manufacturing a semiconductor integrated circuit according to claim 11, further comprising a step of making a thickness of a lower portion of the gate of the semiconductor layer A thinner than a thickness of another portion of the semiconductor layer A.   14. The method of manufacturing a semiconductor integrated circuit according to claim 6, 11, 12 or 13, wherein the surface of the semiconductor layer in contact with the gate metal or the gate insulating film is exposed to plasma containing at least a chlorine-based gas. A method of manufacturing an integrated circuit.

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