JP2013162078A - Nitride semiconductor device including hetero junction and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device which has improved voltage with standing and reduced leakage current.SOLUTION: A nitride semiconductor device comprises an AlGaN layer (3) and an AlGaN layer (0≤x<y≤1) (4) which are sequentially stacked on a buffer layer (2); and further local GaN layer parts (5) formed on the AlGaN layer (4) so as to individually cover a plurality of penetration dislocations (PD) occurring on an upper surface of the AlGaN layer (4).

Description

  The present invention relates to an improvement in a nitride semiconductor device including a heterojunction and a manufacturing method thereof.

  Compared to Si-based and GaAs-based semiconductors, nitride semiconductors such as GaN and AlGaN have the advantages of a high dielectric breakdown electric field, excellent heat resistance, and high electron saturation drift speed, so they operate at high temperatures. It is expected that an electronic device having excellent characteristics in high power operation and the like can be provided.

  In an HFET (heterojunction field effect transistor) which is an example of an electronic device manufactured using such a nitride semiconductor, a two-dimensional electron gas layer resulting from a heterojunction included in the nitride semiconductor multilayer structure is formed. It is well known that the current is controlled by the gate electrode having a Schottky junction with respect to the nitride semiconductor layer between the source electrode and the drain electrode.

FIG. 14 is a schematic cross-sectional view showing a typical example of a conventional HFET. In this HFET, a buffer layer 2, an Al _x Ga _1-x N layer 3, and an Al _y Ga _1-y N layer 4 (0 ≦ x <y ≦ 1) are sequentially stacked on a substrate 1. A gate electrode G that forms a Schottky junction is formed on the Al _y Ga _1-y N layer 4. On both sides of the gate electrode G, a source electrode S and a drain electrode D that are electrically connected to the heterointerface HI between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 are gate electrodes. It is formed apart from G.

At the hetero interface HI between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4, a two-dimensional electron gas (2DEG) is generated due to the polarization characteristic difference between the two layers and lattice distortion. Is done. The Al _x Ga _1-x N layer 3 functions as an electron transit layer, and the Al _y Ga _1-y N layer 4 functions as an electron supply layer.

  In the HFET as shown in FIG. 14, when the source / drain current having the channel layer of 2DEG at the heterointerface HI between the source electrode S and the drain electrode D is controlled by the gate electrode G, the gate electrode There is a problem that a leakage current unrelated to control by G flows through the buffer layer 2. The problem of leakage current flowing through the buffer layer as described above is also described in, for example, Japanese Patent Application Laid-Open No. 2007-251144.

JP 2007-251144 A

In the HFET as shown in FIG. 14, the buffer layer 2, the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 on the substrate 1 are generally formed by well-known MOCVD (organometallic gas). In this case, threading dislocations PD extending from the buffer layer 2 to the upper surface of the Al _y Ga _1-y N layer 4 are included as each layer grows. In FIG. 14, an example of such threading dislocation is indicated by a broken line PD. In this figure, one threading dislocation PD is shown between each of the source electrode D and the gate electrode G and between the gate electrode G and the drain electrode D. include.

  When dislocations are present in the 2DEG region, electrons tend to be trapped in those dislocations. Therefore, when a high electric field is applied to the HFET, electrons may concentrate on dislocations and the HFET may be destroyed. Further, since electrons easily move along the dislocation lines and the dislocations can become a leak path, a leak current is likely to occur through the threading dislocation PD and the buffer layer 2.

  Due to the undesired action of threading dislocation PD as described above, there is a problem that the withstand voltage of the HFET is lowered and the leakage current is increased.

  In view of such a problem, the main object of the present invention is to provide a nitride semiconductor device having a high withstand voltage and a reduced leakage current.

A nitride semiconductor device according to one aspect of the present invention includes an Al _x Ga _1-x N layer and an Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1) sequentially stacked on a buffer layer. further comprising the _Al y _{Ga 1-y} N that _Al y _{Ga 1-y} N plurality of local GaN layer portion formed on layer so as to cover a plurality of threading dislocations on appearing on the surface of the layer It is characterized by that.

The upper surface of the local GaN layer portion is preferably oxidized. The nitride semiconductor device further includes a source electrode and a drain electrode that are electrically connected to a heterointerface between the Al _x Ga _1-x N layer and the Al _y Ga _1-y N layer, the source electrode and the drain electrode And a gate electrode formed in the gate region between. The gate electrode may be formed in contact with the _Al y _{Ga 1-y} N layer may be formed on the _Al y _{Ga 1-y} N layer through an additional GaN layer. The gate electrode may be electrically connected to the source electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a nitride semiconductor device comprising an Al _x Ga _1-x N layer, an Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1) and a GaN layer on a buffer layer Are sequentially deposited, and a plurality of threading dislocations extending from within the Al _y Ga _1-y N layer are selectively oxidized to a plurality of local regions in which a plurality of local regions appear on the upper surface of the GaN layer. And selectively removing the GaN layer by etching in a region not masked by the plurality of local oxide films.

  The selective oxidation of the local region may be performed in a hydrogen peroxide solution or a solution containing hydrogen peroxide solution, or may be performed using natural oxidation, thermal oxidation, or oxygen plasma. The selective etching of the GaN layer can be performed by reactive ion etching using a chlorine-based gas or a mixed gas containing a fluorine-based gas and an oxygen gas.

  According to the present invention as described above, a nitride semiconductor device having a high withstand voltage and a reduced leakage current can be provided.

It is typical sectional drawing which shows the preparation process of HFET by one Embodiment of this invention. FIG. 2 is a schematic cross-sectional view showing a manufacturing process following FIG. 1. FIG. 3 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 2. FIG. 4 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. 3. (A) is an AFM (Atomic Force Microscope) photograph showing threading dislocations appearing as black spots on the surface of the GaN layer, and (B) is after selectively oxidizing a dislocation region as shown in (A). It is an AFM photograph which shows the oxidation area | region which remains after RIE (reactive ion etching) and appears white. (A) is an AFM photograph showing threading dislocations appearing as black spots on the surface of the GaN layer, and (B) is the surface after RIE without selective oxidation of the dislocation regions as shown in (A). It is an AFM photograph shown. Is a schematic energy band diagram showing a situation where the 2DEG is generated in the hetero-interface Al _x Ga _1-x N layer and the _Al y _{Ga 1-y} N layer and (0 ≦ x <y ≦ 1 ). FIG. 8 is a schematic energy band diagram showing an energy structure when a GaN layer is stacked on an Al _y Ga _1-y N layer in FIG. 7. It is an imaginary figure showing typically the situation where 2DEG is excluded by the effect of a local GaN layer in the vicinity of threading dislocation PD. It is typical sectional drawing which shows the preparation process of HFET by other embodiment of this invention. FIG. 11 is a schematic cross-sectional view showing a manufacturing process following FIG. 10. FIG. 12 is a schematic cross-sectional view showing a manufacturing process following FIG. 11. FIG. 13 is a schematic cross-sectional view showing a manufacturing process following FIG. 12. It is typical sectional drawing of a typical example of the conventional HFET.

  1 to 4 are schematic cross-sectional views showing a process of manufacturing a normally-on HFET according to an embodiment of the present invention.

In FIG. 1, the buffer layer 2, the Al _x Ga _1-x N layer 3, the Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1) 4 and the GaN layer 5 are formed on the substrate 1 by MOCVD. Or it deposits sequentially by MBE. At this time, threading dislocations (indicated by broken lines) PD are inevitably introduced into the nitride semiconductor stacked bodies 2 to 5. Although only two threading dislocations are typically shown in FIG. 1, more threading dislocations are actually introduced.

As the substrate 1, Si, sapphire, SiC, or AlN can be used. As the buffer layer 2, for example, when the substrate is Si, an AlN layer or a superlattice layer of an AlN layer and a GaN layer can be used. The thicknesses of the Al _x Ga _1-x N layer 3, the Al _y Ga _1-y N layer 4 and the GaN layer 5 can be set to, for example, 1000 nm, 20 nm and 50 nm, respectively. The Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 have a relationship of 0 ≦ x <y ≦ 1, that is, the Al _y Ga _1-y N layer 4 is an Al _x Ga _1-x N layer. Compared with the layer 3, it has a large Al composition ratio. As a specific example, x = 0.05 and y = 0.22 can be set.

In FIG. 2, the local oxide film 6 is formed by selectively oxidizing only the vicinity of the threading dislocation PD appearing on the surface of the GaN layer 5. Such selective oxidation can be performed by immersing the GaN layer in a hydrogen peroxide solution or a solution containing the hydrogen peroxide solution. Note that selective oxidation can also be performed by natural oxidation, thermal oxidation, oxygen plasma irradiation, or the like. Thus, the selective oxidation is possible because the crystalline GaN layer is difficult to oxidize while the crystal structure in the vicinity of the threading dislocation PD is incomplete and the oxidation is easy. It is believed that there is. After the selective oxidation, the GaN layer 5 is removed by selective RIE in a region not masked by the local oxide film 6. Such selective RIE can be performed as plasma etching using a chlorine-based gas or a mixed gas containing a fluorine-based gas and an oxygen gas. In RIE using such a mixed gas, the etching rate of an oxide layer or a layer of a material that easily oxidizes becomes extremely slow. Therefore, the etching rate of the oxide film 6 on the GaN layer 5 and the Al _y Ga _1-y N layer 4 (Al is easy to oxidize) under the GaN layer 5 is about 1/30 slower than the GaN layer 5 ( That is, the selection ratio is 30 times), and substantially no etching is performed.

FIG. 5 is an AFM photograph demonstrating that selective oxidation and selective RIE of the GaN layer as shown in FIG. 2 can be performed. The lower line segment in FIG. 5 represents a scale of 500 nm. The AFM photograph of FIG. 5 (A) shows the surface state of the GaN layer directly deposited on the substrate before selective oxidation, and threading dislocations appearing on the surface are observed as black spots. In this AFM photograph, the white spots are observed as contaminants on the surface. The upper surface of the GaN layer was selectively oxidized by immersing in hydrogen peroxide water for 10 minutes. Thereafter, selective RIE was performed using a mixed gas containing 30 sccm of Cl ₂ gas and 3 sccm of O ₂ gas under conditions of a gas pressure of 5 Pa and RF (radio frequency) power of 100 W. The surface state after such a selective RIE treatment is shown in the AFM photograph of FIG. In this AFM photograph, what is observed as a white spot is a local oxide film remaining even after RIE. That is, the GaN layer under the local oxide film formed near the upper part of the threading dislocation appearing on the surface of the GaN layer is also left.

  FIG. 6 shows an AFM photograph similar to FIG. 5, but no selective oxidation treatment is performed in FIG. That is, FIG. 6 (A) shows the surface of the GaN layer before selective oxidation as in FIG. 5 (A), but FIG. 6 (B) shows the state after RIE treatment without selective oxidation treatment. The surface state is shown. As seen in FIG. 6B, it can be seen that the GaN layer whose surface was not selectively oxidized was uniformly removed by RIE.

Referring again to FIG. 2, in the region where the GaN layer 5 is removed by RIE without being masked by the local oxide film 6, as described above, the Al _x Ga _1-x N layer 3 and the Al _y Ga ₁₋ 2DEG is generated at the heterointerface HI with the _yN layer 4 due to the polarization characteristic difference between the two layers and lattice distortion. However, 2DEG is not generated or the generation of 2DEG is suppressed below the region where the GaN layer 5 remains under the local oxide film 6 (that is, the region where threading dislocation PD exists). This is because the GaN layer 5 acts so as to relieve the polarization characteristic difference between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4.

FIGS. 7 and 8 show energy band diagrams based on simulation results in the case where the GaN layer is not present and in the case where it is present. That is, in each graph of FIG. 7 and FIG. 8, the horizontal axis represents the distance in the thickness direction of the nitride semiconductor multilayer structure, and the vertical axis represents the electron energy level. The symbol Ev represents the upper limit of the valence band, Ef represents the Fermi level, and Ec represents the lower limit of the conduction band. In the simulations in these drawings, the thicknesses of the Al _x Ga _1-x N layer 3, the Al _y Ga _1-y N layer 4 and the GaN layer 5 are set to 1000 nm, 10 nm and 50 nm, respectively, and x = 0.05 and y = 0.22 are set.

As shown in the simulation results of FIG. 7, when the GaN layer 5 does not exist on the Al _y Ga _1-y N layer 4, the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 near the heterojunction HI, a part of the lower limit Ec of the conduction band becomes equal to or lower than the Fermi level Ef, where 2DEG may occur. On the other hand, as shown in FIG. 8, when the GaN layer 5 exists on the Al _y Ga _1-y N layer 4, the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 are present. In the vicinity of the heterojunction HI, the conduction band is above the Fermi level Ef, where 2DEG does not occur.

FIG. 9 is an imaginary plan view schematically showing a situation in which 2DEG is excluded in the vicinity of the threading dislocation PD as shown in FIG. That is, in the heterojunction HI between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4, 2DEG is used in a region where the GaN layer 5 does not exist on the Al _y Ga _1-y N layer 4. However, 2DEG is not generated in the vicinity of the threading dislocation PD below the region where the GaN layer 5 is locally present.

In the manufacturing process of FIG. 3 subsequent to FIG. 2, the gate electrode G is formed on the Al _y Ga _1-y N layer 4 exposed by removing the GaN layer 5 by RIE. As a material of the gate electrode G having a Schottky barrier with respect to the Al _y Ga _1-y N layer 4, for example, TiN or WN can be used.

In the manufacturing process of FIG. 4 following FIG. 3, the source electrically connected to the heterointerface HI between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 on both sides of the gate electrode G. An electrode S and a drain electrode D are formed separately from the gate electrode G. As a material of the source electrode S and the drain electrode D that can be ohmic-bonded to 2DEG at the hetero interface HI, a Ti / Al alloy, an HfAlMoAu alloy, or the like can be preferably used.

As described above, a normally-on type HFET with improved withstand voltage and reduced leakage current is completed by eliminating 2DEG from the vicinity of threading dislocation PD. In order to suppress a known current collapse phenomenon in the HFET, the surface of the Al _y Ga _1-y N layer 4 may be covered with a silicon nitride film having a thickness of 20 nm, for example. A well-known field plate electrode may be provided in order to alleviate electric field concentration near the gate electrode and increase the withstand voltage of the HFET. Furthermore, the HFET of FIG. 4 can be modified into a diode by electrically connecting the gate electrode G and the source electrode S.

  10 to 13 are schematic cross-sectional views showing a process of manufacturing a normally-off HFET according to another embodiment of the present invention.

Also in FIG. 10, as in the case of FIG. 1, a buffer layer 2, an Al _x Ga _1-x N layer 3, an Al _y Ga _1-y N layer 4, and a GaN layer 5 are sequentially deposited on the substrate 1. The The thicknesses of the Al _x Ga _1-x N layer 3, the Al _y Ga _1-y N layer 4, and the GaN layer 5 can be set to, for example, 1000 nm, 10 nm, and 50 nm, respectively.

  In FIG. 11, the gate electrode G is formed on the GaN layer 5. The gate electrode G can be formed as a TiN layer having a thickness of 70 nm, for example.

In FIG. 12, as in the case of FIG. 2, the local oxide film 6 is formed by selectively oxidizing only the vicinity of the threading dislocation PD appearing on the surface of the GaN layer 5. Thereafter, the GaN layer 5 is removed by selective RIE in a region not masked by the local oxide film 6 or the gate electrode G of TiN. At this time, the thickness of the gate electrode G of TiN is reduced from about 70 nm to about 50 nm. In the region in which the GaN layer 5 is removed by RIE without being masked by the local oxide film 6 or the TiN gate electrode G, the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4 are interposed. 2DEG is generated at the heterointerface HI. However, 2DEG is generated below the region where the GaN layer 5 remains under the local oxide film 6 or the TiN gate electrode G (that is, the region where the threading dislocation PD exists and the region below the gate electrode G). Or generation of 2DEG is suppressed.

In FIG. 13, as in the case of FIG. 4, the both sides of the gate electrode G are electrically connected to the hetero interface HI between the Al _x Ga _1-x N layer 3 and the Al _y Ga _1-y N layer 4. A source electrode S and a drain electrode D are formed separately from the gate electrode G.

As described above, a normally-off HFET having improved withstand voltage and reduced leakage current is completed by eliminating 2DEG from the vicinity of threading dislocation PD. That is, the HFET of FIG. 13 is a normally-off type in which when no voltage is applied to the gate electrode G, 2DEG does not exist below the gate electrode and is off. In the HFET of FIG. 13 as well, the surface of the Al _y Ga _1-y N layer 4 may be covered with a silicon nitride film in order to suppress a known current collapse phenomenon. Moreover, a well-known field plate electrode may be provided. Furthermore, it can also be modified to a diode by electrically connecting the gate electrode G and the source electrode S of the HFET of FIG.

  As described above, according to the present invention, it is possible to provide a nitride semiconductor device having a high withstand voltage and a reduced leakage current.

1 substrate, 2 buffer layer, 3 Al _x Ga _1-x N layer, 4 Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1), 5 GaN layer, HI heterointerface, 2DEG two-dimensional electron gas, S source electrode, D drain electrode, G gate electrode, PD threading dislocation.

Claims (9)

An Al _x Ga _1-x N layer and an Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1) sequentially stacked on the buffer layer;
Further comprising the _Al y _{Ga 1-y} N layer and the plurality of through-dislocations appearing on the upper surface so as to cover the individual _Al y _{Ga 1-y} N multi formed on layer locally GaN layer portion A nitride semiconductor device.   The nitride semiconductor device according to claim 1, wherein an upper surface of the local GaN layer portion is oxidized. A source electrode and a drain electrode electrically connected to a heterointerface between the Al _x Ga _1-x N layer and the Al _y Ga _1-y N layer, and a gate between the source electrode and the drain electrode A nitride semiconductor device comprising a gate electrode formed in a region. The nitride semiconductor electronic device according to claim 3, wherein the gate electrode is formed in contact with the Al _y Ga _1-y N layer. The nitride semiconductor electronic device according to claim 3, wherein the gate electrode is formed on the Al _y Ga _1-y N layer via an additional GaN layer.     The nitride semiconductor device according to claim 3, wherein the gate electrode is electrically connected to the source electrode. An Al _x Ga _1-x N layer, an Al _y Ga _1-y N layer (0 ≦ x <y ≦ 1) and a GaN layer are sequentially deposited on the buffer layer,
Forming a plurality of local oxide films by selectively oxidizing a plurality of local regions in which a plurality of threading dislocations extending from within the Al _y Ga _1-y N layer appear on the upper surface of the GaN layer;
A method of manufacturing a nitride semiconductor device, comprising selectively removing the GaN layer by etching in a region not masked by the plurality of local oxide films.   The production according to claim 7, wherein the oxidation is performed in a hydrogen peroxide solution or a solution containing the hydrogen peroxide solution, or is performed using natural oxidation, thermal oxidation, or oxygen plasma. Method.   9. The manufacturing method according to claim 7, wherein the etching is performed by reactive ion etching using a chlorine-based gas or a mixed gas containing a fluorine-based gas and an oxygen gas.