JP2011233695A - NORMALLY-OFF TYPE GaN-BASED FIELD EFFECT TRANSISTOR - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a normally-off type GaN-based FET having high gate voltage resistance and reduced on-resistance.SOLUTION: A normally-off type GaN-based FET comprises: a channel layer 4 composed of a first type GaN-based semiconductor; a pair of electron supply layers 5 composed of a second type GaN-based semiconductor, which are separately formed of the channel layer each other; a gate insulating film 7 covering the channel layer between the electron supply layers; a source electrode and a drain electrode ohmically contacting the channel layer; and a gate electrode formed on the gate insulating film. The gate insulating film comprises a first and second insulating layers sequentially deposited on the channel layer. A first insulating layer 7a is composed of any of Si oxide, nitride, and oxynitride, and has a thickness of 5 nm or less. A second insulating layer 7b has a large ε×Ecompared with the first insulating layer, where ε represents a dielectric constant and Erepresents a breakdown electric field.

Description

  The present invention relates to a GaN-based field effect transistor (FET), and more particularly, to both a high gate withstand voltage and a low on-resistance of a normally-off GaN-based FET.

  A FET using a GaN-based semiconductor, which is a typical example of a nitride semiconductor, uses a two-dimensional electron gas generated at the AlGaN / GaN interface as a channel due to the characteristics of the material, thereby making it a conventional FET using Si. In comparison, it is considered promising as a transistor capable of high withstand voltage characteristics and large current operation. Among these, normally-off type FETs are in high demand especially in the field of power devices that handle large currents from the viewpoint of safety at the time of failure. Note that a normally-off FET refers to a transistor that is off when no voltage is applied to the gate (normal time) and that is on when a voltage is applied to the gate.

  The schematic cross-sectional view of FIG. 10 shows a normally-off type FET disclosed in International Publication WO 03 / 071607A1 of Patent Document 1. In the drawings of the present application, dimensional relationships such as length, width, and thickness are appropriately changed for clarity and simplification of the drawings, and do not represent actual dimensional relationships.

  In the FET of FIG. 10, a buffer layer 12, a GaN channel layer 13, and a pair of AlGaN electron supply layers 14a and 14b are sequentially stacked on a substrate 11. In this case, a two-dimensional electron gas 6 represented by a broken line in the figure is generated at the heterointerface between the GaN channel layer 13 and the AlGaN electron supply layers 14a and 14b. A source electrode S and a drain electrode D are formed on the channel layer 13 via the GaN contact layers 16a and 16b outside the pair of AlGaN electron supply layers 14a and 14b. A gate electrode G is formed on the channel layer 13 between the pair of AlGaN electron supply layers 14 a and 14 b via an insulating film 15. In such an FET, the two-dimensional electron gas 6 does not exist in the channel layer 13 below the gate electrode G, and the off state is maintained when no voltage is applied to the gate electrode G. However, if a voltage is applied to the gate electrode G, the inversion layer generated on the upper surface of the channel layer 13 below the gate electrode G is connected to the two-dimensional electron gas below the AlGaN electron supply layers 14a and 14b, and the source electrode of the FET Between S and the drain electrode D can be turned on and can be energized.

International Publication WO03 / 071607A1

When the inventors of the present invention related characteristics to the gate portion G ₀ of the normally-off GaN-based FET as shown in Figure 10 was examined intensively, in case of using a general SiO ₂ as a gate insulating film, SiO _Since the value of the product ε × E _c of the dielectric constant ε of _{2 and} the dielectric breakdown electric field E _c is small, it has been found that the characteristics of the GaN-based FET cannot be fully utilized.

In view of this, the present inventors examined the use of a high dielectric film, which is generally called a high-k film, as the gate insulating film. As a result, when a high-k gate insulating film is used instead of the SiO ₂ gate insulating film in the GaN-based FET as shown in FIG. 10, the product ε × E _c of the dielectric constant and the breakdown electric field is The value was found to be sufficient. However, since the gate insulating film 15 is formed in direct contact with the GaN channel layer 13, it has been found that the electron mobility in the channel at the interface between the GaN layer and the High-k insulating film is lowered. In other words, it has been found that when a high-k gate insulating film is used, the characteristics of the GaN-based FET that can operate at a large current cannot be fully utilized.

Problems related to the gate insulating film as described above will be described in more detail with reference to FIGS. FIG. 11A shows a cross-sectional structure in which the SiO ₂ insulating film 15a and the gate electrode G are sequentially stacked on the GaN channel layer 13, and FIG. 11B shows a case where an ON voltage is applied to the gate electrode G. The electron energy band figure when there is is shown. That is, in FIG. 11B, the vertical direction represents the energy level, and the horizontal direction represents the thickness direction of the stacked structure in FIG. A curve e in the figure schematically represents the electron concentration distribution. In the example of FIG. 11B, an Al _0.05 Ga _0.95 N layer is provided under the GaN channel layer 13. FIG. 12 is similar to FIG. 11 except that the SiO ₂ insulating film 15a is changed to the High-k insulating film 15b. Note that Hf _0.7 Al _0.3 O _x is used as the high-k insulating film 15b.

In both cases of FIGS. 11 and 12, when an on-voltage is applied to the gate electrode G, it is indicated by a curve e representing the electron concentration distribution at the interface between the GaN channel layer 13 and the gate insulating films 15a and 15b. As a result, an inversion layer is formed. However, the electron concentration at the interface between the GaN channel layer and the gate insulating film is higher when the High-k gate insulating film is used than when the SiO ₂ gate insulating film 15a is used. A high electron concentration means that the FET can pass a larger current.

Further, the inventors have actually measured that the SiO ₂ gate insulating film has a relative dielectric constant ε _r of 4 and a dielectric breakdown electric field E _c of 10 MV / cm, and an Hf _0.7 Al _0.3 O _x gate. the insulating film relative dielectric constant of 18 at a dielectric breakdown electric field _{E c} was 5 MV / cm. Therefore, when the same electron concentration is to be obtained under the gate insulating film, the Hf _0.7 Al _0.3 O _x gate insulating film is used as the gate electrode of the FET using the SiO ₂ gate insulating film. A gate voltage that is 4.5 times higher than that of must be applied, but the SiO ₂ gate insulating film is broken down at a gate voltage that is about twice as high.

On the other hand, according to the measurement by the present inventors, the electron mobility at the interface between the SiO ₂ gate insulating film and the GaN channel layer is about 100 cm ² V ⁻¹ s ⁻¹ , but the HfAlO gate insulating film and the GaN channel layer are The electron mobility at the interface with is only about 20 cm ² V ⁻¹ s ⁻¹ . In this case, as shown in FIG. 10, in the normally-off type FET having a structure in which the gate insulating film is formed in contact with the GaN channel layer, there is no heterointerface that generates a two-dimensional electron gas under the gate electrode. A decrease in electron mobility under the gate insulating film greatly impairs the characteristics of the FET.

  Accordingly, an object of the present invention is to provide a normally-off GaN-based FET having a high breakdown voltage of a gate insulating film and a low on-resistance with reduced channel resistance.

A normally-off type GaN-based FET according to the present invention includes a channel layer made of a first-type GaN-based semiconductor, a pair of electron supply layers made of a second-type GaN-based semiconductor that are spaced apart from each other on the channel layer, and these A gate insulating film covering the channel layer between the pair of electron supply layers; a source electrode and a drain electrode that are in ohmic contact with the channel layer outside the pair of electron supply layers; and a gate formed on the gate insulating film The gate insulating film includes first and second insulating layers sequentially deposited on the channel layer, and the first insulating layer is made of any one of an oxide, a nitride, and an oxynitride of Si. And the second insulating layer has a larger ε × E _c than the first insulating layer, where ε represents a dielectric constant, and E _c represents a breakdown electric field. As a feature That.

  Note that the second insulating layer can be formed using an oxide, nitride, or oxynitride containing one or more of Hf, Zr, Ta, Al, Ti, Pr, and Si. The gate insulating film may further include a third insulating layer deposited on the second insulating layer, and the third insulating layer, like the first insulating layer, is also an oxide, nitride and oxynitride of Si. It is preferably made of any one of the materials and has a thickness of 5 nm or less. The thickness of the first and third insulating layers is more preferably 3 nm or less. The channel layer is preferably made of GaN, and the electron supply layer is preferably made of AlGaN.

  In the normally-off GaN-based FET according to the present invention as described above, a high breakdown voltage of the gate insulating film can be obtained, and the channel resistance can be suppressed to obtain a low on-resistance.

(A) is a schematic cross-sectional view showing a gate structure in a normally-off GaN-based FET according to the present invention, and (B) is an electron energy band diagram of the gate structure when the FET is in an ON state. It is typical sectional drawing which shows an example of the manufacturing process of normally-off type GaN-type FET by this invention. FIG. 3 is a schematic cross-sectional view showing a manufacturing process following FIG. 2. FIG. 4 is a schematic cross-sectional view showing the manufacturing process following FIG. 3. FIG. 5 is a schematic cross-sectional view showing the manufacturing process following FIG. 4. FIG. 6 is a schematic cross-sectional view showing the manufacturing process following FIG. 5. FIG. 7 is a schematic cross-sectional view showing the manufacturing process following FIG. 6. (A) is a schematic cross-sectional view showing a gate structure in a normally-off type GaN-based FET according to the present invention, and (B) is an energy band diagram when a reverse bias electric field is applied to the gate structure of the FET. (A) is a schematic cross-sectional view showing another example of a gate structure in a normally-off GaN-based FET according to the present invention, and (B) is an energy band diagram when a reverse bias electric field is applied to the gate structure of the FET. It is. It is typical sectional drawing which shows the normally-off type GaN-type FET by a prior art. (A) is a schematic cross-sectional view showing a gate structure in a conventional normally-off GaN-based FET including a SiO ₂ gate insulating film, and (B) is an energy band when a reverse bias electric field is applied to the gate structure of the FET. FIG. (A) is a schematic cross-sectional view showing a gate structure in a conventional normally-off GaN-based FET including an HfAlO gate insulating film, and (B) is an energy band diagram when a reverse bias electric field is applied to the gate structure of the FET. It is.

In a normally-off GaN-based FET, in order to realize a low on-resistance, it is desired that the sheet conductivity of the channel included in the FET is high. The highest sheet conductivity σ _s in the channel is when the dielectric constant of the gate insulating film is ε, the breakdown electric field of the gate insulating film is E _c , and the electron mobility in the channel under the gate insulating film is μ In addition, it can be expressed using a well-known approximate expression (1).

σ _s = ε × E _c × μ (1)
This approximate expression is σ _s = Q _s × μ = C _g × (V _g −V _th ) × μ = (ε / t) × (V _g −V _th ) × μ≈ (ε / t) × V _g Xμ = ε × (V _g / t) × μ = ε × E _c × μ. Note that Q _s represents channel charge, C _g represents gate capacitance, V _g represents gate voltage, V _th represents the threshold voltage of the FET, and t represents the thickness of the insulating film. Note that in this derivation, Vg»V _th as a condition when the maximum sheet conductivity sigma _s is obtained is _assumed, has been carried out approximation of _{(V g -V th) ≒ V} g.

Here, when the maximum sheet conductivity σ _s in the gate structure of FIG. 11 is obtained, the relative dielectric constant ε _r of the SiO ₂ gate insulating film 15a measured by the inventors is 4, and the dielectric breakdown electric field E _c is Since it is 10 MV / cm and the electron mobility μ in the channel is about 100 cm ² V ⁻¹ s ⁻¹ , σ _s = ε × E _c × μ = 3.54 × 10 ⁻⁴ S. The dielectric constant is represented by ε = ε _r × ε ₀ , and ε ₀ represents the dielectric constant of vacuum. Further, when the highest sheet conductivity σ _s in the gate structure of FIG. 12 is obtained, the relative dielectric constant ε _r of the Hf _0.7 Al _0.3 O _x gate insulating film 15a measured by the inventors is 18, Since the breakdown electric field E _c is 5 MV / cm and the electron mobility μ in the channel is about 20 cm ² V ⁻¹ s ⁻¹ σ _s = ε × E _c × μ = 1.59 × 10 ^{− 4} S. From this, it can be seen that it is more preferable to use the SiO ₂ film than the Hf _0.7 Al _0.3 O _x film as the gate electrode from the viewpoint of the sheet conductivity σ _s .

However, as described above, in the SiO ₂ gate insulating film, the relative dielectric constant ε _r is 4, the dielectric breakdown electric field E _c is 10 MV / cm, and in the Hf _0.7 Al _0.3 O _x gate insulating film, since the dielectric constant is 18 in a dielectric breakdown electric field E _c is at 5 MV / cm, in order to obtain a same electron concentration under the gate insulating film, a gate electrode of the FET using SiO ₂ gate insulating film It is necessary to apply a gate voltage 4.5 times higher than that in the case of using the Hf _0.7 Al _0.3 O _x gate insulating film, but the SiO ₂ gate insulating film has a gate voltage about twice as high. Will be broken down.

In view of the above situation, the present inventors have devised a gate structure as shown in FIG. 1A schematically shows a gate structure included in a normally-off GaN-based FET according to an embodiment of the present invention, and FIG. 1B shows an electron energy band of the gate structure when the FET is on. Is schematically shown. More specifically, the gate insulating film 7 and the gate electrode G are sequentially stacked on the GaN channel layer 4. However, in this gate insulating film 7, a very thin SiO ₂ layer 7a having a thickness of about 3 nm and a high-k layer 7b of Hf _0.7 Al _0.3 O _x having a thickness of about 50 nm are stacked in this order. ing. An Al _0.05 Ga _0.95 N layer is provided under the GaN channel layer 4.

With respect to the gate structure of FIG. 1, since the Hf _0.7 Al _0.3 O _x layer 7b occupies most of the thickness of the gate insulating film 7, in the above approximate expression (1), the dielectric constant ε and Regarding the dielectric breakdown electric field E _c , values of the relative dielectric constant ε _r = 18 of the Hf _0.7 Al _0.3 O _x layer 7b and the dielectric breakdown electric field E _c = 5 MV / cm can be used. On the other hand, as the value of the electron mobility μ in the channel layer under the gate insulating film 7, μ≈100 cm ² V ⁻¹ s ⁻¹ value related to the SiO ₂ layer 7a can be used. If Equation (1) is calculated using these values, the value of σ _s = ε × E _c × μ = 7.97 × 10 ⁻⁴ S is obtained as the highest sheet conductivity of the channel with respect to the gate structure of FIG. can get. That is, compared with σ _s = 3.54 × 10 ⁻⁴ S in the gate structure in FIG. 11 and σ _s = 1.59 × 10 ⁻⁴ S in the gate structure in FIG. 12, the gate structure in FIG. It can be seen that high sheet conductivity is obtained. As a result, the on-resistance can be significantly reduced in the normally-off GaN-based FET including the gate structure of FIG.

By the way, in the gate insulating film 7 including the SiO ₂ layer 7a and the Hf _0.7 Al _0.3 O _x layer 7b, there is a concern whether the SiO ₂ layer 7a does not break down. This will be discussed below. A voltage V is applied to the two-layer insulating film including the HfAlO layer (relative permittivity ε _r = 18) and the SiO ₂ layer (relative permittivity ε _r = 4), and an electric field of E = 22 MV / cm is generated in the insulating film. Think about what you are doing. In this case, the electric field generated in each dielectric layer included in the insulating film is inversely proportional to the relative dielectric constant, an electric field of 22 × 4 / (18 + 4) = 4 MV / cm is generated in the HfAlO layer, and 22 in the SiO ₂ layer. An electric field of x18 / (18 + 4) = 18 MV / cm is generated. Thus, while the breakdown electric field of HfAlO layer as described above is about 5 MV / cm, usually because the breakdown electric field of thick SiO ₂ layer is about 10 MV / cm as a gate insulating film, the SiO ₂ layer Will break down. If the SiO ₂ layer breaks down, the HfAlO layer breaks down and the entire FET breaks down.

However, when the thickness of the dielectric layer becomes very thin, the breakdown electric field E _c of the dielectric layer that increases known empirically general. This can be considered as follows. That is, when a high voltage is applied to the dielectric layer, the electrons move while being accelerated, and when the speed exceeds a certain limit, the electrons flow in an avalanche-like manner, thereby causing dielectric breakdown. it is conceivable that. However, when the dielectric layer is extremely thin, it is considered that electrons do not pass through the dielectric layer before being sufficiently accelerated, and an avalanche of electron flow does not occur. Thus considering empirical fact that breakdown electric field E _c when the thickness of the dielectric layer becomes very thin increases, SiO ₂ layer thickness of less than or equal to 3nm and more reliably below a thickness of 5nm The breakdown electric field of can be 18 MV / cm or more. As a whole, the gate insulating film 7 can withstand the electric field of E _c = 22 MV / cm in the above-described example, can achieve a high sheet conductivity σ _s = εEμ, and can reduce the channel resistance. it can. The voltage V applied to the gate electrode is V = (electric field E generated in the HfAlO layer) × (thickness of the HfAlO layer) + (electric field E generated in the SiO ₂ layer) × (thickness of the SiO ₂ layer). expressed.

  The schematic cross-sectional views of FIGS. 2 to 7 show an example of the manufacturing process of a normally-off GaN-based FET including a gate structure as shown in FIG.

First, in FIG. 2, a buffer layer 2, an Al _0.05 Ga _0.95 N layer 3 having a thickness of 1000 nm, and a GaN channel layer having a thickness of 40 nm on a substrate 1 such as Si, Al ₂ O ₃ , SiC, or AlN. 4 and Al _0.25 Ga _0.75 N electron supply layer 5 are sequentially stacked using, for example, the well-known MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy). When the AlGaN electron supply layer 5 is laminated on the GaN channel layer 4 in this way, a two-dimensional electron gas 6 is generated at the heterointerface due to both actions of spontaneous polarization and piezoelectric polarization.

  Next, in FIG. 3, in order to form a gate region, a part of the electron supply layer 5 is removed using RIE (reactive ion etching) or ICP (high frequency inductively coupled plasma), and the GaN channel layer 4 A part of the upper surface of the substrate is exposed. As a result, the two-dimensional electron gas 6 generated between the GaN channel layer 4 and the AlGaN electron supply layer 5 stops in the exposed region of the GaN channel layer 4.

In FIG. 4, a SiO ₂ insulating layer 7a having a thickness of 5 nm or less, preferably 3 nm or less and a Hf _0.7 Al _0.3 O _x insulating layer 7b having a thickness of 50 nm, for example, are deposited by sputtering, and these insulating layers are further deposited. The unnecessary region is removed by etching, whereby the gate insulating film 7 is formed.

  In FIG. 5, the electron supply layer 5 is removed by etching using RIE or ICP in a region not covered with the gate insulating film 7. Thereby, the upper surface of the GaN channel layer 4 is exposed outside the pair of electron supply layers 5.

  In FIG. 6, the source electrode S and the drain electrode D are deposited on the GaN channel layer 4 exposed outside the pair of electron supply layers 5, and an annealing process for ohmic junction is performed. Note that the etching of the electron supply layer 5 in FIG. 5 is an example of a method for more reliably performing ohmic contact between the source electrode S and the drain electrode D in FIG. As another ohmic junction forming method, there is, for example, a method of facilitating the ohmic junction by performing ion implantation in the same region instead of etching the electron supply layer 5 in FIG.

  Finally, in FIG. 7, a gate electrode G is formed on the gate insulating film 7, thereby completing a normally-off type GaN-based FET. As a result, the normally-off GaN-based FET thus obtained can achieve both a high withstand voltage of the gate electrode and a low on-resistance of the channel layer.

  Next, the effect of the gate insulating film 7 on reverse bias leakage of electrons when a reverse bias electric field is generated in the gate insulating film 7 will be examined.

FIG. 8A shows a gate structure including the gate insulating film 7 as in FIG. However, unlike FIG. 1B, FIG. 8B shows an energy band diagram when a reverse bias electric field is generated in the gate structure of FIG. 8A. In this case, what acts as a main barrier against reverse bias leakage is a barrier due to a difference in electron energy between the gate electrode G and the Hf _0.7 Al _0.3 O _x insulating layer 7. However, there is a concern that this energy barrier may occur in some cases from the viewpoint of more reliable prevention of reverse bias leakage.

FIG. 9 shows an example of a gate structure for eliminating the concern about such reverse bias leakage. FIG. 9A shows a gate structure similar to FIG. 8A, but an SiO ₂ insulating layer 7c is added between the gate electrode G and the Hf _0.7 Al _0.3 O _x insulating layer 7b. In terms of inclusion. The thickness of the SiO ₂ insulating layer 7c included in the gate insulating film 7A in FIG. 9A also has a thickness of 5 nm or less like the SiO ₂ insulating layer 7a from the viewpoint of the dielectric breakdown electric field, It has a thickness of 3 nm or less.

FIG. 9B shows an energy band diagram when a reverse bias electric field is generated in the gate structure of FIG. 9A. As apparent from the comparison between FIG. 9B and FIG. 8B, the gate electrode is larger than the energy barrier at the interface between the gate electrode G and the Hf _0.7 Al _0.3 O _x insulating layer 7b. It can be seen that the energy barrier at the interface between G and the SiO ₂ insulating layer 7c is high and can act to reliably prevent reverse bias leakage.

In the above embodiment of the present invention, an example in which an SiO ₂ layer enabling an electron mobility μ of about 100 cm ² V ⁻¹ s ⁻¹ is used as an insulating layer in contact with the GaN channel layer has been shown. In our measurements, the SiN _x layer also allows a high electron mobility of about 120 cm ² V ⁻¹ s ⁻¹ , so it is clear that the SiN _x layer may be used as an insulating layer in contact with the GaN channel layer. It will be apparent that an insulating layer of Si oxynitride, which is an intermediate material, may be used.

Further, in the above embodiment of the present invention, an example in which HfAlO is used as the High-k insulating film stacked on the insulating layer in contact with the GaN channel layer has been shown. However, such a High-k insulating film is a GaN channel. may be Re has a large epsilon × _{E c} as compared to the insulating layer in contact with the layer, an oxide containing Hf, Zr, Ta, Al, Ti, Pr, and Si and one or more as such High-k dielectric film An insulating film made of nitride or oxynitride can be used. In particular, a complex oxide, nitride, or oxynitride containing at least one of Hf and Zr and at least one of Al and Si has a particularly large ε × Ec and excellent heat resistance. Preferred as a high-k film.

  As described above, according to the present invention, it is possible to provide a normally-off GaN-based FET having a high breakdown voltage of the gate insulating film and a low on-resistance with a suppressed channel resistance.

1 substrate, 2 buffer layer, 3 AlGaN layer, 4 GaN channel layer, 5 AlGaN electron supply layer, 6 two-dimensional electron gas, 7 gate insulating film, 7a SiO ₂ insulating layer, 7b HfAlO insulating layer, 7c SiO ₂ insulating layer, 7A Gate insulating film, S source electrode, G gate electrode, D drain electrode.

Claims (7)

A normally-off GaN-based field effect transistor,
A channel layer made of a first-type GaN-based semiconductor;
A pair of electron supply layers made of a second-type GaN-based semiconductor provided apart from each other on the channel layer;
A gate insulating film covering the channel layer between the pair of electron supply layers;
A source electrode and a drain electrode that are in ohmic contact with the channel layer;
A gate electrode formed on the gate insulating film,
The gate insulating layer includes first and second insulating layers sequentially deposited on the channel layer;
The first insulating layer is made of any one of Si oxide, nitride and oxynitride and has a thickness of 5 nm or less,
The second insulating layer has a larger ε × E _c than the first insulating layer, where ε represents a dielectric constant and E _c represents a breakdown electric field.   2. The transistor according to claim 1, wherein the second insulating layer is made of an oxide, nitride, or oxynitride containing one or more of Hf, Zr, Ta, Al, Ti, Pr, and Si. .   3. The transistor according to claim 1, wherein the first insulating layer has a thickness of 3 nm or less.   The gate insulating film further includes a third insulating layer deposited on the second insulating layer, and the third insulating layer is formed of an Si oxide, a nitride and an acid in the same manner as the first insulating layer. 4. The transistor according to claim 1, wherein the transistor is made of any one of nitrides and has a thickness of 5 nm or less.   The transistor according to claim 4, wherein the third insulating layer has a thickness of 3 nm or less.   2. The transistor according to claim 1, wherein the second insulating layer is made of an oxide, nitride, or oxynitride containing two or more of Hf, Zr, Ta, Al, Ti, Pr, and Si. .   The transistor according to claim 1, wherein the channel layer is made of GaN, and the electron supply layer is made of AlGaN.

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