JP2010045073A - Field effect transistor and method of manufacturing field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor having low on resistance and a high breakdown voltage and channel mobility, and to provide a method of manufacturing the field effect transistor. <P>SOLUTION: The field effect transistor has a MOS structure and includes a nitride-based compound semiconductor. The field effect transistor has: a semiconductor layer that is formed on a substrate and has a prescribed conductivity type; a contact layer that is formed between the semiconductor layer, and source and drain electrodes by epitaxial growth and has a conductivity type opposite to the prescribed one; and a field relaxing layer that is formed between a contact layer at the side of the drain electrode and the semiconductor layer by epitaxial growth while the field relaxing layer is superposed on the gate electrode via a gate insulation film, and has a conductivity type opposite to the prescribed one and a carrier concentration lower than that of the contact layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor made of a nitride compound used as a power electronics device or a high frequency amplification device, and a method for manufacturing the same.

  Wide band gap semiconductors typified by group III-V nitride-based compounds have high breakdown voltage, good electron transport characteristics, and good thermal conductivity, so they are materials for semiconductor devices for high temperature, high power, or high frequency. As very attractive. For example, in a field effect transistor (FET) having an AlGaN / GaN heterostructure, a two-dimensional electron gas is generated at the interface due to the piezoelectric effect. This two-dimensional electron gas has high electron mobility and carrier density, and has attracted much attention. In addition, a heterojunction FET (HFET) using an AlGaN / GaN heterostructure has a low on-resistance and a high switching speed, and can operate at a high temperature. These features are very suitable for power switching applications.

  A normal AlGaN / GaN HFET is a normally-on type device in which a current flows when a bias is not applied to the gate, and the current is interrupted by applying a negative potential to the gate. On the other hand, in power switching applications, in order to ensure safety when the device breaks, normally-off type devices in which current does not flow when a bias is not applied to the gate and current flows by applying a positive potential to the gate Is preferred.

In order to realize a normally-off type device, it is necessary to adopt a MOSFET structure. FIG. 10 is a schematic sectional view of a conventional MOSFET (see Non-Patent Document 1). In this MOSFET 800, a p-GaN layer 803 is formed on a substrate 801 with a buffer layer 802 interposed therebetween. Further, n ⁺ -GaN regions 805a and 805b are formed in a part of the p-GaN layer 803 by ion implantation as a contact layer for taking ohmic contact between the source / drain regions. Further, between the gate and drain are to mitigate the local electric field concentration between the gate and drain in order to improve the breakdown voltage of the device, called the electric field relaxation layer or RESURF (REduced SURface Field) layer ⁿ - -GaN region 804 is formed by an ion implantation method. An oxide film 806 made of SiO ₂ or the like is formed as a gate insulating film, and a gate electrode 807 made of metal such as poly-Si, Ni / Au, or WSi is formed on the oxide film 806. A source electrode 808 and a drain electrode 809 are formed on the n ⁺ -GaN regions 805b and 805a, respectively. As the source electrode 808 and the drain electrode 809, a metal such as Ti / Al or Ti / AlSi / Mo that forms an ohmic contact with n ⁺ -GaN is used.

By the way, in the MOSFET, in order to improve the channel mobility, it is important to keep the interface state at the interface between the oxide film and the semiconductor low. In a normal Si-based MOSFET, a SiO ₂ thermal oxide film formed by thermally oxidizing Si is used as an oxide film, and a very good interface with a low interface state is realized. On the other hand, in the case of a nitride-based compound MOSFET, a good thermal oxide film cannot be obtained, and therefore an oxide film made of SiO ₂ or the like is generally formed by PCVD.

Here, as described above, conventionally, an ion implantation method is used to form the n ⁺ -GaN region and the n ⁻ -GaN region. In the ion implantation method, after the implantation of predetermined impurity ions, annealing for recovering crystal defects and activating the implanted impurities is performed. When the semiconductor material is, for example, GaN, the crystal bond is strong, so that it is necessary to perform annealing at a high temperature of 1200 ° C. or higher.

Matocha. K, Chow. T.P, Gutmann. R.J., “High-voltage normally off GaN MOSFETs on sapphire substrates”, IEEE Transaction on Electron Devices. Vol. 52, No. 1 2005 pp. 6-10

  However, if the activation of impurities by annealing is insufficient, the leakage current increases due to inactive impurities, the electron mobility of the RESURF layer deteriorates, the on-resistance increases, and the withstand voltage is increased. There is a problem of lowering.

  On the other hand, if high-temperature and long-time annealing is performed to sufficiently activate the impurities, pits are generated on the surface of the GaN layer where the oxide film should be formed, and the quality of the GaN / oxide interface is insufficient. Thus, there is a problem that the mobility of the channel deteriorates.

  The present invention has been made in view of the above, and an object of the present invention is to provide a field effect transistor having a low on-resistance, high withstand voltage and high channel mobility, and a method for manufacturing the field effect transistor.

  In order to solve the above-described problems and achieve the object, a field effect transistor according to the present invention is a field effect transistor having a MOS structure and made of a nitride-based compound semiconductor, which is formed on a substrate. A contact layer having a conductivity type opposite to the predetermined conductivity type formed between the semiconductor layer and each of the source electrode and the drain electrode by epitaxial growth; and It is formed between the contact layer on the drain electrode side and the semiconductor layer so as to overlap with the gate electrode through a gate insulating film, and has a conductivity type opposite to the predetermined conductivity type and more than the contact layer. And an electric field relaxation layer having a low carrier concentration.

  In the field effect transistor according to the present invention, in the above invention, the field relaxation layer is formed so that the sheet resistance increases stepwise or continuously from the drain electrode side to the gate electrode side. Features.

  In the field effect transistor according to the present invention, in the above invention, the electric field relaxation layer is formed so that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. Features.

  The field effect transistor according to the present invention is a field effect transistor having a MOS structure and made of a nitride compound semiconductor, and a semiconductor layer having a predetermined conductivity type formed on a substrate, and the above-described semiconductor layer by epitaxial growth. A contact layer formed between the semiconductor layer and each of the source electrode and the drain electrode and having a conductivity type opposite to the predetermined conductivity type; and the contact layer on the drain electrode side and the semiconductor layer formed by epitaxial growth. An electric field relaxation region forming layer having a band gap energy different from that of the semiconductor layer, which is formed so as to overlap with the gate electrode with a gate insulating film interposed therebetween, and the electric field relaxation region forming layer of the semiconductor layer, It has an electric field relaxation region formed by a two-dimensional electron gas generated in the vicinity of the interface.

  In the field effect transistor according to the present invention as set forth in the invention described above, the electric field relaxation region forming layer is formed such that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. It is characterized by that.

Further, in the field effect transistor according to the present invention, in the above invention, the substrate has an n-type conductivity, and a back electrode is formed on the back surface.
The source electrode is formed to electrically connect the substrate and the contact layer.

  The field effect transistor manufacturing method according to the present invention is a method for manufacturing a field effect transistor having a MOS structure and made of a nitride compound semiconductor, wherein a semiconductor layer having a predetermined conductivity type is formed on a substrate. A semiconductor layer forming step, an electric field relaxation layer forming step of forming an electric field relaxation layer having a conductivity type opposite to the predetermined conductivity type by epitaxial growth in a partial region on the semiconductor layer; Contact layer formation for forming a contact layer having a conductivity type opposite to the predetermined conductivity type and having a carrier concentration higher than that of the electric field relaxation layer on the region of the electric field relaxation layer on which the source electrode and the drain electrode are formed A gate insulating film forming step of forming a gate insulating film in a partial region on the semiconductor layer; and the gate insulating film Characterized in that it comprises a gate electrode forming step of forming a gate electrode so that the electric field relaxation layer and partially overlaps the upper.

  The field effect transistor manufacturing method according to the present invention is a method for manufacturing a field effect transistor having a MOS structure and made of a nitride compound semiconductor, wherein a semiconductor layer having a predetermined conductivity type is formed on a substrate. Forming a semiconductor layer, forming an electric field relaxation region forming layer having a band gap energy different from that of the semiconductor layer by epitaxial growth in a partial region on the semiconductor layer, the semiconductor layer or A contact layer forming step of forming a contact layer having a conductivity type opposite to the predetermined conductivity type by epitaxial growth on a region for forming the source electrode and the drain electrode of the electric field relaxation region forming layer; A gate insulating film forming step for forming a gate insulating film in a partial region; and the electric field relaxation on the gate insulating film. Characterized in that it comprises a gate electrode forming step of forming a gate electrode so as to overlap a part and a region formation layer.

  According to the present invention, it is possible to realize a field effect transistor having low on-resistance, high withstand voltage, and high channel mobility.

  Hereinafter, embodiments of a field effect transistor and a method for manufacturing a field effect transistor according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a MOSFET according to Embodiment 1 of the present invention. In this MOSFET 100, a buffer layer 102 and a p-GaN layer 103, which are formed by alternately laminating AlN layers and GaN layers, are formed on a substrate 101 made of sapphire, SiC, Si, or the like. Furthermore, n ⁻ -GaN layers 104 a and 104 b are formed in partial regions on the p-GaN layer 103. Further, n ⁺ -GaN layers 105a and 105b, which are contact layers, are formed on the n ⁻ -GaN layers 104a and 104b, respectively, and a source electrode 108 and a drain electrode are respectively formed on the n ⁺ -GaN layers 105b and 105a. 109 is formed. Further, between the source electrode 108 and the drain electrode 109, an SiO ₂ film 106 that is a gate insulating film is formed over the n ⁺ -GaN layer 105b, the p-GaN layer 103, and the n ⁻ -GaN layer 104a. Yes. A gate electrode 107 is formed on the SiO ₂ film 106. The n ⁻ -GaN layer 104 a is formed so as to partially overlap the gate electrode 107 in the stacking direction via the SiO ₂ film 106 between the n ⁺ -GaN layer 105 a and the p-GaN layer 103. It functions as a RESURF layer that increases pressure resistance.

This MOSFET100 is RESURF layer ⁿ - -GaN layer 104a and ^n, - -GaN layer ^104b, n + -GaN layer 105a, 105b is formed by epitaxial growth, the layers are very few inactive impurities. As a result, the electron mobility is high, the leakage current is small, and the on-resistance is low. Furthermore, since this MOSFET 100 does not use an ion implantation method in the manufacturing process, high-temperature and long-time annealing for sufficiently activating the impurities is unnecessary, so that generation of pits on the surface of the GaN crystal is suppressed, Channel mobility is not degraded.

Next, a method for manufacturing MOSFET 100 will be described with reference to FIGS. First, as shown in FIG. 2, the buffer layer 102, the p-GaN layer 103, the n ⁻ -GaN layer 104, and the n ⁺ -GaN layer 105 are sequentially epitaxially grown on the substrate 101 by, for example, the MOCVD method. The dopant added to the n ⁻ -GaN layer 104 and the n ⁺ -GaN layer 105 is, for example, Si, and the addition concentrations are about 1 × 10 ¹⁷ cm ⁻³ and 1 × 10 ¹⁹ cm ⁻³ , respectively. Further, the dopant added to the p-GaN layer 103 is, for example, Mg, and the addition concentration is about 5 × 10 ¹⁵ to 1 × 10 ¹⁷ cm ⁻³ .

Next, a part of the n ⁺ -GaN layer 105 is patterned by photolithography. Then, using this patterning as a mask, a part of the n ⁺ -GaN layer 105 is removed by etching to form n ⁺ -GaN layers 105a and 105b. ^Further, n + -GaN layer 105a, ⁿ and exposed 105b - patterning formed on a part of the -GaN layer 104, the patterning as a ^mask, n - the part of -GaN layer 104 is removed by etching, n ^- The GaN layers 104a and 104b are formed, and a part of the surface of the p-GaN layer 103 is exposed (see FIG. 3). Note that it is preferable to use a dry etching method such as ICP (Inductively Coupled Plasma) for etching.

Next, as shown in FIG. 4, an SiO ₂ film 106 for forming a MOS structure is deposited to 100 nm on the entire surface. Next, in order to reduce the interface state, annealing is performed for 30 minutes in a N ₂ atmosphere at a temperature of 900 ° C. Next, 650 nm of poly-Si serving as a gate electrode is deposited. Thereafter, the substrate is annealed in a POCl ₃ atmosphere for 20 minutes in a furnace with an in-furnace temperature of 900 ° C., so that poly Si is doped with P to make the poly Si n ⁺ type. Further, photolithography for defining the gate region is performed, unnecessary poly-Si is removed by etching by RIE, and the gate electrode 107 is formed. The gate electrode 107 is formed so as to partially overlap the n ⁻ -GaN layer 104 a with the SiO ₂ film 106 interposed therebetween.

Further, a part of the SiO ₂ film 106 on the n ⁺ -GaN layers 105a and 105b is removed by etching to form the source electrode 108 and the drain electrode 109, whereby the MOSFET 100 is completed.

In MOSFET 100, n ⁺ -GaN layer 105b may be formed directly on p-GaN layer 103 without forming n ⁻ -GaN layer 104b. In this case, for example, after the n ⁻ -GaN layer 104 is epitaxially grown, a part thereof is removed by etching to form the n ⁻ -GaN layer 104a, and then the n ⁺ -GaN layers 105a and 105b are selectively grown. .

  As described above, MOSFET 100 according to the first embodiment is a MOSFET having low on-resistance, high withstand voltage, and high channel mobility.

(Embodiment 2)
Next, a MOSFET according to the second embodiment of the present invention will be described. MOSFET 200 according to the second embodiment has a configuration similar to that of MOSFET 100, but is formed so that the thickness of the electric field relaxation layer gradually decreases from the drain electrode side to the gate electrode side.

FIG. 5 is a schematic sectional view of a MOSFET according to the second embodiment of the present invention. Similar to the MOSFET 100, the MOSFET 200 includes a substrate 201, a buffer layer 202, a p-GaN layer 203, n ⁻ -GaN layers 204a and 204b, n ⁺ -GaN layers 205a and 205b, a source electrode 208, and a drain electrode 209. ing. In addition, an SiO ₂ film 206 and a gate electrode 207 are sequentially formed between the source electrode 208 and the drain electrode 209. In addition, the n ⁻ -GaN layer 204 a is formed so as to partially overlap the gate electrode 207 in the stacking direction via the SiO ₂ film 206 between the n ⁺ -GaN layer 205 a and the p-GaN layer 203. , Function as a RESURF layer.

This MOSFET200 is, ⁿ is RESURF layer - -GaN layer 204a and ^n, - -GaN layer ^204b, n + -GaN layer 205a, since 205b are formed by epitaxial growth, as well as the MOSFET 100, a high electron mobility The leakage current is small and the on-resistance is low. Furthermore, this MOSFET 200 does not require high-temperature and long-time annealing in the manufacturing process, so that pits are not reliably generated on the surface of the GaN crystal and channel mobility is not deteriorated.

^Further, n - -GaN layer 204a ^{is, n} positioned immediately below the n + -GaN layer 205a - composed of two layers of a -GaN layer 204ab - and -GaN layer ^204aa, n - adjacent to -GaN layer 204aa ⁿ Has been. Here, although the n ⁻ -GaN layer 204aa and the n ⁻ -GaN layer 204ab have the same carrier density, the n ⁻ −GaN layer 204ab is formed thinner than the n ⁻ −GaN layer 204aa. Yes. Accordingly, the sheet resistance of the n ⁻ -GaN layer 204ab is higher than that of the n ⁻ −GaN layer 204aa. As a result, the n ⁻ -GaN layer 204a which is a RESURF layer has a higher sheet resistance from the drain side to the gate side, and the local concentration of the electric field is further relaxed. Therefore, the MOSFET 200 has higher withstand voltage.

The MOSFET 200 can be manufactured by the same method as the MOSFET 100 described above. n ^- the -GaN layer 204a is initially ⁿ of uniform thickness - forming a -GaN layer, then forming the ⁿ - the layer thickness was thin and partially etching the gate side of the -GaN layer, n ^- This can be realized by forming the -GaN layer 204ab.

Further, the n ⁻ -GaN layer 204a included in the MOSFET 200 is configured by two layers having different layer thicknesses, so that the sheet resistance increases from the drain electrode side to the gate electrode side. However, the n ⁻ -GaN layer serving as the RESURF layer may be composed of two layers having the same thickness and different carrier concentrations, and the sheet resistance may be increased from the drain side to the gate side. It may be configured.

(Embodiment 3)
Next, a MOSFET according to the third embodiment of the present invention will be described. MOSFET 300 according to the third embodiment has a heterostructure of AlGaN and GaN having different band gap energies.

FIG. 6 is a schematic sectional view of a MOSFET according to the third embodiment of the present invention. In the MOSFET 300, as with the MOSFET 100, a buffer layer 302 and a p-GaN layer 303 are formed on a substrate 301. However, unlike the MOSFET 100, AlGaN layers 311a and 311b are formed on a part of the p-GaN layer 303. Furthermore, n ⁺ -GaN layers 305a and 305b are formed on the AlGaN layers 311a and 311b, respectively, and a source electrode 308 and a drain electrode 309 are formed on the n ⁺ -GaN layers 305b and 305a, respectively. An SiO ₂ film 306 is formed between the source electrode 308 and the drain electrode 309 over the n ⁺ -GaN layer 305b, the p-GaN layer 303, and the AlGaN layer 311a, and a gate is formed on the SiO ₂ film 306. An electrode 307 is formed. The AlGaN layer 311a is formed so that a part thereof overlaps with the gate electrode 307 with the SiO ₂ film 306 interposed therebetween.

  In this MOSFET 300, a heterostructure of AlGaN / GaN is formed at the interface between the AlGaN layers 311a, 311b and the p-GaN layer 303 formed by epitaxial growth. As a result, regions 303a and 303b in which two-dimensional electron gas is generated by spontaneous polarization and piezoelectric polarization are formed near the interfaces of the p-GaN layer 303 with the AlGaN layers 311a and 311b. In the MOSFET 300, the region 303a functions as a RESURF region, and local concentration of the electric field between the gate and the drain is alleviated. That is, the AlGaN layer 311a functions as an electric field relaxation region layer. As a result, the MOSFET 300 is a MOSFET having high withstand voltage, extremely high electron mobility, low leakage current, low on-resistance, and high channel mobility.

The MOSFET 300 can be manufactured by the same method as the MOSFET 100 described above. The AlGaN layers 311a and 311b can be formed by epitaxially growing an AlGaN layer instead of the n ⁻ -GaN layer 104 and removing a part thereof.

(Embodiment 4)
Next, a MOSFET according to a fourth embodiment of the present invention will be described. MOSFET 400 according to the fourth embodiment has the same configuration as MOSFET 300, but is formed such that the thickness of the AlGaN layer gradually decreases from the drain electrode side to the gate electrode side, as in MOSFET 200. ing.

FIG. 7 is a schematic cross-sectional view of a MOSFET according to Embodiment 4 of the present invention. Similar to the MOSFET 300, the MOSFET 400 includes a buffer layer 402, a p-GaN layer 403, AlGaN layers 411a and 411b, n ⁺ -GaN layers 405a and 405b, a source electrode 408, a drain electrode 409, and a SiO ₂ film on the substrate 401. 406 and a gate electrode 407 are formed. The AlGaN layer 411a is formed so as to partially overlap the gate electrode 407 with the SiO ₂ film 406 interposed therebetween. In addition, regions 403a and 403b in which two-dimensional electron gas is generated are formed in the vicinity of the interfaces between the p-GaN layer 403 and the AlGaN layers 411a and 411b.

Further, like the MOSFET 300, the AlGaN layer 411a is composed of two layers of an AlGaN layer 411aa located immediately below the n ⁺ -GaN layer 405a and an AlGaN layer 411ab adjacent to the AlGaN layer 411aa. The AlGaN layer 411ab is formed thinner than the AlGaN layer 411aa. As a result, the region 403a is also composed of a region 403aa located immediately below the AlGaN layer 411aa and a region 403ab located directly below the AlGaN layer 411ab. Regarding the density of the two-dimensional electron gas, the region 403aa is higher than the region 403ab, so that the region 403a which is the RESURF region has a higher sheet resistance from the drain side to the gate side. As a result, in the MOSFET 400, the local concentration of the electric field is further reduced, and the withstand voltage is higher.

(Embodiment 5)
Next, a MOSFET according to a fifth embodiment of the present invention will be described. MOSFET 500 according to the fifth embodiment has the same configuration as MOSFET 100, but the conductivity type of the substrate is n-type, the back electrode is formed on the back surface of the substrate, and the source electrode is n-type with the substrate. The contact layer is formed so as to be electrically connected.

FIG. 8 is a schematic sectional view of a MOSFET according to the fifth embodiment of the present invention. The MOSFET 500 includes a substrate 501 made of a Si semiconductor having an n ⁺ conductivity type, and a back electrode 512 made of a metal that is formed on the entire back surface of the substrate 501 and is in ohmic contact with the substrate 501. Further, like the MOSFET 100, on the substrate 501, the buffer layer 502, the p-GaN layer 503, the n ⁻ -GaN layers 504a and 504b, the n ⁺ -GaN layers 505a and 505b, the drain electrode 509, the SiO ₂ film 506, the gate An electrode 507 is formed. The n ⁻ GaN layer 504 a is formed so as to partially overlap the gate electrode 507 with the SiO ₂ film 506 interposed therebetween. Further, a source electrode 508 is formed so as to electrically connect the n ⁺ -GaN layer 505b and the substrate 501. As a result, the back electrode 512 and the source electrode 508 are also electrically connected.

  Like the MOSFET 100, the MOSFET 500 has high electron mobility, small leakage current, low on-resistance, and high channel mobility. Furthermore, since this MOSFET 500 can use the back electrode 512 as a source electrode, it is not necessary to form a bonding pad for connecting the source electrode 208, so that the chip area can be reduced. Further, in this MOSFET 500, since the back electrode 512 has the same potential as the source electrode 508, the back electrode 512 reduces the local concentration of the electric field between the gate and the drain and further improves the pressure resistance.

The MOSFET 500 can be manufactured in the same manner as the manufacturing method of the MOSFET 100 described above. However, the source electrode 508 and the back electrode 512 are formed as follows. That is, after a part of the ⁿ + -GaN layer 505b of the SiO ₂ film 506 is removed by etching, further ⁿ + -GaN layer ^505b, n - -GaN layer 504b, p-GaN layer 503, and each buffer layer 502 A part of this is removed by etching to form an opening reaching the surface of the substrate 501, and then a source electrode 508 is formed. Further, after the drain electrode 509 is formed, the back surface of the substrate 501 is polished, and a metal film is deposited on the polished back surface to form the back electrode 512.

(Embodiment 6)
Next, a sixth embodiment of the present invention will be described. The sixth embodiment is a semiconductor integrated circuit including a MOSFET having a configuration similar to that of the MOSFET according to the second embodiment.

FIG. 9 is a schematic sectional view of a semiconductor integrated circuit according to the sixth embodiment of the present invention. In this semiconductor integrated circuit 600, a transistor T, which is a MOSFET, and a diode D are integrated on the same substrate 601. In the transistor T portion, a buffer layer 602 and a p-GaN layer 603 are formed on a substrate 601. Further, AlGaN layers 611a and 611b are formed in part of the p-GaN layer 603. Also, AlGaN layer 611a, respectively ⁿ + -GaN layer 605a is on ^611b, n + -GaN layer 605b is formed, further ⁿ + -GaN layer ^605a, n + -GaN layer respectively on 605b drain electrode 609, A source electrode 608 is formed. Further, a SiO ₂ film 606 is formed on the surface of the p-GaN layer 603 between the source electrode 608 and the drain electrode 609 and a part on the AlGaN layers 611a and 611b. Further, a gate electrode 607 is formed on the SiO ₂ film 606.

On the other hand, the diode D portion shares the substrate 601, the buffer layer 602, the p-GaN layer 603, and the AlGaN layer 611 a with the transistor T. On the AlGaN layer 611a, a cathode electrode 613 made of a metal such as Ni / Au and Schottky bonded to the AlGaN layer 611a is formed. Further, an anode electrode 614 made of a metal such as Ti / Al is formed on the AlGaN layer 611a. The anode electrode 614 is in ohmic contact with the two-dimensional electron gas layer generated near the interface between the p-GaN layer 603 and the AlGaN layer 611a through the n ⁺ -GaN layer 605c and the AlGaN layer 611a as contact layers.

  In this semiconductor integrated circuit 600, the AlGaN layers 611a and 611b and the p-GaN layer 603 are formed by epitaxial growth. As a result, the transistor T has high electron mobility, low leakage current, low on-resistance, and high channel mobility.

Further, in this semiconductor integrated circuit 600, the threshold value of the transistor T can be controlled by the layer thickness of the AlGaN layer 611a, the film thickness of the SiO ₂ film 606, and the carrier concentration of the p-GaN layer 603. Therefore, the semiconductor integrated circuit 600 is a semiconductor integrated circuit including the transistor T with high threshold controllability.

  When manufacturing the semiconductor integrated circuit 600, the transistor T and the diode D can be manufactured in a single process by using an appropriate mask pattern in a manufacturing method similar to the MOSFET 300, for example.

  Further, in this semiconductor integrated circuit 600, if a depletion type HEMT is formed instead of the diode D, an E / D type inverter integrated circuit can be realized.

  Conventionally, a normally-off HEMT is known in which an AlGaN layer is formed on an i-GaN layer, a part of the AlGaN layer is recess-etched, and a gate electrode is formed on the formed recess structure. In such a HEMT, the threshold value varies depending on the thickness of the AlGaN layer in the recess structure. However, since the AlGaN layer originally has a thin thickness of about 1 μm, the control of the etching depth when this is recess-etched is controlled. As a result, the controllability of the HEMT threshold was low.

  However, the transistor T included in the semiconductor integrated circuit 600 has high threshold controllability as described above.

  In the above embodiment, the semiconductor layer formed on the buffer layer may be made of an i-type nitride compound semiconductor. In the above embodiment, the MOSFET is n-type. However, the present invention is not limited to this, and can be applied to a p-type MOSFET.

1 is a schematic cross-sectional view of a MOSFET according to a first embodiment of the present invention. It is a figure explaining the manufacturing method of MOSFET shown in FIG. It is a figure explaining the manufacturing method of MOSFET shown in FIG. It is a figure explaining the manufacturing method of MOSFET shown in FIG. It is the cross-sectional schematic of MOSFET which concerns on Embodiment 2 of this invention. It is the cross-sectional schematic of MOSFET which concerns on Embodiment 3 of this invention. It is a section schematic diagram of MOSFET concerning Embodiment 4 of the present invention. It is a section schematic diagram of MOSFET concerning Embodiment 5 of the present invention. FIG. 7 is a schematic cross-sectional view of a semiconductor integrated circuit according to a sixth embodiment of the present invention. It is the cross-sectional schematic of the conventional MOSFET.

Explanation of symbols

100-500 MOSFET
101-601 Substrate 102-602 Buffer layer 103-603 p-GaN layer 104a, 104b, 204a, 204b, 204aa, 204ab, 504a, 504b n ^-- GaN layer 105a-605a, 105b-605b, 605c n ⁺ -GaN layer 106-606 SiO ₂ film 107-607 Gate electrode 108-608 Source electrode 109-609 Drain electrode 311a, 311b, 411a, 411b, 411aa, 411ab, 611a, 611b AlGaN layer 303a, 303b, 403a, 403b, 403aa, 403ab 2 Region where dimensional electron gas is generated 512 Back electrode 600 Semiconductor integrated circuit 613 Cathode electrode 614 Anode electrode D Diode T Transistor

Claims (8)

A field effect transistor having a MOS structure and made of a nitride compound semiconductor,
A semiconductor layer having a predetermined conductivity type formed on the substrate;
A contact layer formed between the semiconductor layer and each of the source electrode and the drain electrode by epitaxial growth and having a conductivity type opposite to the predetermined conductivity type;
The contact layer has a conductivity type opposite to the predetermined conductivity type and is formed so as to overlap the gate electrode through a gate insulating film between the contact layer on the drain electrode side and the semiconductor layer by epitaxial growth. An electric field relaxation layer having a carrier concentration lower than that of the layer;
A field effect transistor comprising:   2. The field effect transistor according to claim 1, wherein the field relaxation layer is formed so that the sheet resistance increases stepwise or continuously from the drain electrode side to the gate electrode side.   3. The field effect transistor according to claim 2, wherein the field relaxation layer is formed so that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. 4. A field effect transistor having a MOS structure and made of a nitride compound semiconductor,
A semiconductor layer having a predetermined conductivity type formed on the substrate;
A contact layer formed between the semiconductor layer and each of the source electrode and the drain electrode by epitaxial growth and having a conductivity type opposite to the predetermined conductivity type;
An electric field relaxation region forming layer having a band gap energy different from that of the semiconductor layer formed by epitaxial growth so as to overlap the gate electrode through a gate insulating film between the contact layer on the drain electrode side and the semiconductor layer; ,
And a field effect transistor formed by a two-dimensional electron gas generated in the vicinity of the interface between the semiconductor layer and the field relaxation region formation layer.   5. The field effect transistor according to claim 4, wherein the electric field relaxation region forming layer is formed so that the layer thickness decreases stepwise or continuously from the drain electrode side to the gate electrode side. The substrate has an n-type conductivity and has a back electrode formed on the back surface.
The field effect transistor according to claim 1, wherein the source electrode is formed so as to electrically connect the substrate and the contact layer. A method of manufacturing a field effect transistor having a MOS structure and made of a nitride compound semiconductor,
A semiconductor layer forming step of forming a semiconductor layer having a predetermined conductivity type on the substrate;
An electric field relaxation layer forming step of forming an electric field relaxation layer having a conductivity type opposite to the predetermined conductivity type by epitaxial growth in a partial region on the semiconductor layer;
A contact layer having a conductivity type opposite to the predetermined conductivity type by epitaxial growth and having a carrier concentration higher than that of the electric field relaxation layer is formed on the semiconductor layer or the region where the source electrode and the drain electrode of the electric field relaxation layer are formed. A contact layer forming step to be formed;
Forming a gate insulating film in a partial region on the semiconductor layer; and
Forming a gate electrode so as to partially overlap the electric field relaxation layer on the gate insulating film;
A method of manufacturing a field effect transistor comprising: A method of manufacturing a field effect transistor having a MOS structure and made of a nitride compound semiconductor,
A semiconductor layer forming step of forming a semiconductor layer having a predetermined conductivity type on the substrate;
An electric field relaxation region forming layer forming step of forming an electric field relaxation region forming layer having a band gap energy different from that of the semiconductor layer by epitaxial growth in a partial region on the semiconductor layer;
A contact layer forming step of forming a contact layer having a conductivity type opposite to the predetermined conductivity type by epitaxial growth on a region where the source electrode and the drain electrode of the semiconductor layer or the electric field relaxation region forming layer are formed;
Forming a gate insulating film in a partial region on the semiconductor layer; and
Forming a gate electrode so as to partially overlap the electric field relaxation region forming layer on the gate insulating film;
A method of manufacturing a field effect transistor comprising:

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