JP5534701B2 - Semiconductor device - Google Patents

Description

The present invention heterojunction semiconductor device using a nitride semiconductor (especially high electron mobility transistors: HEMT = High Electron Mobility Transistor like) about the.

  A HEMT using a nitride semiconductor is expected to be a device that operates at high frequency and high output because it has a high breakdown electric field and high electron mobility.

  In the conventional HEMT, there is a problem of “current collapse” in which the current decreases due to the influence of the trap on the semiconductor surface, and as a report having a structure in which the surface of the semiconductor layer is protected with a thin film in order to reduce this, for example, A structure in which the surface of an AlGaN electron supply layer as in Non-Patent Document 1 is covered with AlN has been proposed.

“Surface Passion of AlGaN / GaN HEMTs Using AlN Layer Deposition by Reactive Magnetron Sputtering”. Liu et al., Phys. stat. sol. (C) 0, No1, p. p. 69-73, 2002

  FIG. 1A of Non-Patent Document 1 shows the drain voltage dependence of the drain current in a structure without a protective film, and FIG. 1B adopts a structure in which the AlGaN surface is covered with an AlN protective film as described above. Thus, the trap of the AlN protective film and the AlGaN interface is reduced, and the problem of current collapse due to the trap is improved.

  However, as described in the text of this document, covering with the AlN protective film decreased the maximum drain current and increased the sheet resistance and contact resistance. As a result, there is a problem that the on-resistance increases.

The present invention has been made based on recognition of such a problem, and has improved the on-resistance while maintaining current collapse and withstand voltage, and based on this knowledge, a high electron mobility electric field that operates at high voltage and high frequency. and to provide a semiconductor equipment of effect transistor or the like.

Such a semiconductor device in the first aspect of this invention, there is provided a nitride semiconductor device of the heterojunction, a channel layer made of a nitride semiconductor formed on a substrate, formed on the channel layer wherein An electron supply layer made of a nitride semiconductor having a larger band gap than the channel layer, a gate electrode selectively formed on the electron supply layer, and the gate electrode sandwiched and separated on the electron supply layer formed source, and a drain electrode, the source electrode, between the drain electrode, is formed on the electron supply layer, the channel layer, that acting on the two-dimensional electron gas concentration formed on the electron supply layer interface and a thin film, the thin film, the a thin film band gap energy is smaller than the electron supply layer, before Symbol thin film, contact to the drain electrode side of the gate electrode The thickness formed in a first region except for the drain electrode around the edge of the gate electrode Te, and the film thickness formed in said second region of the drain electrode around the edge of the gate electrode is different.
A semiconductor device according to a second aspect of the present invention is a heterojunction nitride semiconductor device, a channel layer made of a nitride semiconductor formed on a substrate, and the channel formed on the channel layer An electron supply layer made of a nitride semiconductor having a larger band gap than the layer; a gate electrode selectively formed on the electron supply layer; and the gate electrode on the electron supply layer with the gate electrode interposed therebetween And a thin film that is formed on the electron supply layer between the source electrode and the drain electrode and that acts on the channel layer and the electron supply layer interface and that acts on the two-dimensional electron gas concentration. The thin film is formed in a first region excluding the vicinity of the drain electrode side end portion of the gate electrode on the drain electrode side of the gate electrode. And the film thickness formed in the second region near the drain electrode side end portion of the gate electrode is different from the film thickness formed in the second region. Thin film thickness.
A semiconductor device according to a third aspect of the present invention is a heterojunction nitride semiconductor device, a channel layer made of a nitride semiconductor formed on a substrate, and the channel formed on the channel layer An electron supply layer made of a nitride semiconductor having a larger band gap than the layer; a gate electrode selectively formed on the electron supply layer; and the gate electrode on the electron supply layer with the gate electrode interposed therebetween And a thin film that is formed on the electron supply layer between the source electrode and the drain electrode and that acts on the channel layer and the electron supply layer interface and that acts on the two-dimensional electron gas concentration. The thin film is formed in a first region excluding the vicinity of the drain electrode side end portion of the gate electrode on the drain electrode side of the gate electrode. When, different from the thickness formed in said second region of the drain electrode around the edge of the gate electrode, the thin film is GaN film.

Such a semiconductor device in the first aspect of this invention, there is provided a nitride semiconductor device of the heterojunction, a channel layer made of a nitride semiconductor formed on a substrate, formed on the channel layer wherein An electron supply layer made of a nitride semiconductor having a larger band gap than the channel layer, a gate electrode selectively formed on the electron supply layer, and the gate electrode sandwiched and separated on the electron supply layer formed source, and a drain electrode, the source electrode, between the drain electrode, is formed on the electron supply layer, the channel layer, that acting on the two-dimensional electron gas concentration formed on the electron supply layer interface and a thin film, the thin film, the a thin film band gap energy is smaller than the electron supply layer, before Symbol thin film, contact to the drain electrode side of the gate electrode The film thickness formed in the first region excluding the vicinity of the drain electrode side end portion of the gate electrode is different from the film thickness formed in the second region near the drain electrode side end portion of the gate electrode. Due to the difference in action due to the difference in film thickness, the two-dimensional electron gas concentration outside the vicinity of the gate electrode (especially the first region on the drain electrode side) is high, so the on-resistance can be reduced and current collapse can be reduced. Since the two-dimensional electron gas concentration in the vicinity (second region) is low, the breakdown voltage can be maintained.
A semiconductor device according to a second aspect of the present invention is a heterojunction nitride semiconductor device, a channel layer made of a nitride semiconductor formed on a substrate, and the channel formed on the channel layer An electron supply layer made of a nitride semiconductor having a larger band gap than the layer; a gate electrode selectively formed on the electron supply layer; and the gate electrode on the electron supply layer with the gate electrode interposed therebetween And a thin film that is formed on the electron supply layer between the source electrode and the drain electrode and that acts on the channel layer and the electron supply layer interface and that acts on the two-dimensional electron gas concentration. The thin film is formed in a first region excluding the vicinity of the drain electrode side end portion of the gate electrode on the drain electrode side of the gate electrode. And the film thickness formed in the second region near the drain electrode side end portion of the gate electrode is different from the film thickness formed in the second region. Due to the thin film thickness, the on-resistance is reduced and the current collapse is reduced due to the high two-dimensional electron gas concentration outside the vicinity of the gate electrode (especially the first region on the drain electrode side) due to the difference in action due to the difference in film thickness. In addition, since the two-dimensional electron gas concentration in the vicinity of the gate electrode (second region) is low, the breakdown voltage can be maintained.
A semiconductor device according to a third aspect of the present invention is a heterojunction nitride semiconductor device, a channel layer made of a nitride semiconductor formed on a substrate, and the channel formed on the channel layer An electron supply layer made of a nitride semiconductor having a larger band gap than the layer; a gate electrode selectively formed on the electron supply layer; and the gate electrode on the electron supply layer with the gate electrode interposed therebetween And a thin film that is formed on the electron supply layer between the source electrode and the drain electrode and that acts on the channel layer and the electron supply layer interface and that acts on the two-dimensional electron gas concentration. The thin film is formed in a first region excluding the vicinity of the drain electrode side end portion of the gate electrode on the drain electrode side of the gate electrode. And the film thickness formed in the second region in the vicinity of the drain electrode side end portion of the gate electrode, and the thin film is a GaN film. Since the two-dimensional electron gas concentration outside the vicinity (especially the first region on the drain electrode side) is high, the on-resistance can be reduced to reduce current collapse, and the two-dimensional electron gas concentration near the gate electrode (second region) is low. Therefore, the withstand voltage can be maintained.

It is a longitudinal cross-sectional view which shows the structure of the semiconductor device which concerns on Embodiment 1 of this invention. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 1 is a longitudinal sectional view showing a structural example of a semiconductor device according to a first embodiment. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a longitudinal sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. FIG. 1 is a top view illustrating a structure of a semiconductor device according to a first embodiment. FIG. 6 is a longitudinal sectional view showing a structure of a semiconductor device according to a second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 6 is a longitudinal sectional view showing a structural example of a semiconductor device according to a second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the second embodiment. FIG. 6 is a longitudinal sectional view showing a structural example of a semiconductor device according to a second embodiment. FIG. 6 is a longitudinal sectional view showing a structure of a semiconductor device according to a third embodiment. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. FIG. 10 is a longitudinal sectional view showing a structural example of a semiconductor device according to a third embodiment. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. 12 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to the third embodiment. FIG. FIG. 10 is a longitudinal sectional view showing a structural example of a semiconductor device according to a third embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fourth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a fifth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a sixth embodiment. FIG. 10 is a longitudinal sectional view showing the structure of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a structural example of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a structural example of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment. FIG. 10 is a longitudinal sectional view showing a manufacturing process of a semiconductor device according to a seventh embodiment.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is a longitudinal sectional view showing a configuration example of the nitride semiconductor device according to the first embodiment. The nitride semiconductor device shown in FIG. 1 is a heterojunction field effect transistor (HEMT: high electron mobility transistor) using a group III nitride semiconductor.

  As shown in FIG. 1, the device is formed on a substrate 1, a channel layer 2 made of a first group III nitride semiconductor formed on the upper surface of the substrate 1, and an upper surface of the channel layer 2. An electron supply layer 3 is formed of a second group III nitride semiconductor having a larger band gap than the first group III nitride semiconductor, and forms a heterojunction with the channel layer 2. .

  Further, in this apparatus, the gate electrode 5 formed by Schottky junction selectively formed on the surface of the electron supply layer 3 and the surface of the electron supply layer 3 so as to face each other with the gate electrode 5 interposed therebetween. The source electrode 4a and the drain electrode 4b by the ohmic contact formed are provided.

  Here, as described above, the gate electrode 5 and the electron supply layer 3 form a Schottky junction. The source electrode 4a, the drain electrode 4b, and the electron supply layer 3 are in ohmic contact.

  The device is formed inside the electron supply layer 3 and the channel layer 2 located below the source electrode 4a and the drain electrode 4b in order to reduce the contact resistance between the source electrode 4a and the drain electrode 4b. Further, a corresponding n-type high concentration impurity region (for example, the high concentration impurity region 7 shown in FIG. 8) may be provided.

  Furthermore, the surface of the electron supply layer 3 in the vicinity (second region) from the end of the gate electrode 5 between the gate electrode 5 and the drain electrode 4b is covered with a thin film 6 as a second thin film, and the electron supply layer not covered with the thin film 6 3 (particularly the first region on the drain electrode side) is covered with a thin film 8 as a first thin film different from the thin film 6.

  Here, the thin film 6 as the second thin film and the thin film 8 as the first thin film used as the protective film on the surface of the electron supply layer 3 are composed of a material and a film thickness having an effect of increasing or decreasing the two-dimensional electron gas concentration. The thin film 6 disposed in the vicinity of the drain side of the gate electrode 5 which is the second region has an electron supply in a region which reduces the two-dimensional electron gas concentration and which is not covered by the thin film 6 which is the first region. The thin film 8 covering the surface of the layer 3 is desirably formed with a material and a film thickness that increase the two-dimensional electron gas concentration. If at least the increase in the two-dimensional electron gas concentration by the thin film 6 is smaller than the increase in the two-dimensional electron gas concentration by the thin film 8, the two-dimensional electron gas concentration in the region covered by the thin film 6 is in the region covered by the thin film 8. It can be lower than the two-dimensional electron gas concentration.

  Here, the two-dimensional electron gas is a layered region in which electrons can flow at high speed, and free electrons with high mobility spread in an extremely thin layer. A HEMT (High Electron Mobility Transistor) forms a two-dimensional electron gas layer at an interface by bonding different kinds of semiconductor materials having different band gaps. Increasing the two-dimensional electron gas concentration is increasing the drain current of the transistor.

<A-2. Manufacturing process>
Next, a method for manufacturing the nitride semiconductor device of FIG. 1 according to an example of the first embodiment will be described.

  2 to 27 are longitudinal sectional views showing the method of manufacturing the nitride semiconductor device according to the present embodiment in the order of steps.

  First, as shown in FIG. 2, a substrate 1 made of, for example, sapphire, SiC (silicon carbide), GaN, or Si is prepared.

  Next, as shown in FIG. 3, the channel layer 2, the electrons are formed on the main surface of the substrate 1 by, for example, MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition). The supply layer 3 is laminated in this order.

Here, the channel layer 2 is made of Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, xy ≠ 1) as the first group III nitride semiconductor. On the other hand, the electron supply layer 3 is made of Al _m In _n Ga _1-mn N (0 ≦ m) as a second group III nitride semiconductor having a larger band gap width than the first group III nitride semiconductor. ≦ 1, 0 ≦ n ≦ 1, mn ≠ 1).

  The thickness of the channel layer 2 may be at least a thickness that allows electrons to flow (50 nm to 3000 nm), and the impurity concentration in the channel layer 2 is not limited. In addition, as described above, the electron supply layer 3 has a wider band gap than the channel layer 2.

For example, the combination of the channel layer 2 and the electron supply layer 3 includes Al _m Ga _1-m N electron supply layer / GaN channel layer (when x = y = 0, n = 0), or Al _m Ga _{1 -m} N electron supply layer / In _y Ga _1-y N channel layer (when x = 0, n = 0) and the like are conceivable.

The impurity concentration of the electron supply layer 3 is set to 1 × 10 ¹⁸ cm ⁻³ or less in order to make the electron supply layer 3 a high breakdown voltage layer. Here, the conductivity type of the impurity is always n-type. In the case of nitride semiconductors, even when impurities are not intentionally introduced (non-doped), impurities enter the nitride semiconductor from the growth furnace or atmospheric gas, and the nitride semiconductor contains n-type impurities. It becomes. For this reason, even if it is non-doped in crystal growth, it is sufficient if the actual impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or less.

  Next, as shown in FIG. 4, a resist pattern 9a is formed on the surface region of the electron supply layer 3 other than the source / drain electrode formation region by photolithography. Then, using the resist pattern 9a as a mask, an ohmic metal (for example, a laminated film of Ti and Al, a laminated film of Ti, Al, Mo, Au, etc.) is deposited, and then the resist pattern 9a is removed to form a source electrode 4a and the drain electrode 4b are formed on the source / drain electrode formation region in the surface of the electron supply layer 3 (lift-off method) (FIG. 5).

  At this time, even if the source and drain electrodes are formed by forming regions having a high concentration of n-type impurities in the electron supply layer 3 and the channel layer 2 which are semiconductor layers immediately below the source electrode 4a and the drain electrode 4b. good. The manufacturing method is as follows.

  That is, a resist pattern 9b is formed by photolithography in the surface of the electron supply layer 3 (FIG. 6). This resist pattern 9b is a mask for ion implantation in the next process. The thickness of the resist pattern 9b may be about 1 μm to 6 μm (thickness at which ions do not reach the electron supply layer 3). If the implanted ions can be blocked, a film such as an oxide film may be used instead of the resist pattern 9b. Alternatively, the resist pattern 9b may be formed after a nitride film or an oxide film having a thickness of about 10 nm to 100 nm is formed on the surface of the electron supply layer 3. This nitride film or oxide film suppresses atoms (Al, Ga, N, In, etc.) constituting the electron supply layer 3 from being blown into the vacuum by ions during ion implantation.

Thereafter, ion implantation is performed by irradiating ions 10 accelerated by an electric field using an ion implantation apparatus (FIG. 7). The ions 10 may be atoms that are n-type impurities. Specifically, it is O, C, Si, S, Ge, Se, Sn, Te, Pb, etc., but Si or Ge having a shallow impurity level is desirable. Furthermore, the electrical activation of n-type impurities may be increased by simultaneously implanting p-type impurities such as Mn, Mg, Cu, and Be. The acceleration energy and implantation concentration of ion implantation are set so that the impurity concentration in the region where the high-concentration n-type impurity region 7 is formed in the region of the electron supply layer 3 exceeds 1 × 10 ¹⁸ cm ^−3. Just do it.

  Thereafter, the resist pattern 9b is peeled off, and a heat treatment for activating the implanted ions 10 is performed. The heat treatment is performed in order to replace the implanted ions and crystal constituent atoms, and to recover the damage formed by the ion implantation. For this reason, it is desirable to process at a temperature of 1000 ° C. or higher for a time of 5 seconds or longer. As for the atmosphere, in order to prevent nitrogen atoms from escaping from the surface of the electron supply layer 3, it is desirable to perform the heat treatment in a gas containing nitrogen such as nitrogen gas or ammonia gas. Furthermore, in order to prevent nitrogen atoms from escaping from the surface of the electron supply layer 3, heat treatment may be performed after covering the surface of the electron supply layer 3 with a film such as a nitride film, an oxide film, or aluminum nitride. .

  Thereafter, the source / drain electrodes 4a and 4b are formed on the surface of the high-concentration impurity region 7 by the ohmic electrode formation method described above (FIG. 8). The source electrode 4a and the drain electrode 4b may be alloyed by annealing at a predetermined temperature after laminating these ohmic metals. In order to further reduce the contact resistance, it is desirable to remove part of the electron supply layer 3 below the source / drain electrode region or the interface with the channel layer 2 to form the source / drain electrodes 4a and 4b.

  Next, a resist pattern 9c is formed on a region other than the gate formation region 11 where the gate electrode 5 is formed by a method similar to the method of forming the source electrode 4a and the drain electrode 4b (FIG. 9). A gate electrode 5 by Schottky junction is formed in the resist opening (FIG. 10), a gate metal is laminated and a resist 9c is removed by a method similar to the method of forming the source electrode 4a and the drain electrode 4b (lift-off method). ), The gate electrode 5 is formed (FIG. 11). Here, the metal constituting the gate electrode 5 (gate metal) may be any metal that forms a Schottky junction with the electron supply layer 3. For example, a metal having a high work function such as Pt or Ni, or a metal nitride such as silicide, WN, or TaN is in contact with the electron supply layer 3. Further, annealing may be performed at a predetermined temperature after forming the gate electrode 5.

  Next, the surface of the electron supply layer 3 is a second thin film made of a nitride or oxide containing Al, an oxynitride, or an oxide of Ga, Ti, V, Nb, Zr, Hf, or Ta. A certain thin film 6 is formed. Further, the thin film 8 which is a first thin film made of nitride, oxide or oxynitride containing at least one of Si, C, Ge, Sn, Pb, S, Se, Te is excluded from the vicinity of the gate electrode 5. Form in the area.

  Here, a case where AlN is used as the thin film 6 which is a protective film will be described. After the gate electrode 5 is formed, AlN is deposited by electron beam evaporation, CVD, MBE, or sputtering.

  Here, the case where it forms by sputtering deposition, for example is demonstrated. As sputtering deposition, AlN is deposited by using direct current sputtering, high frequency sputtering, magnetron sputtering, ion beam sputtering, electron cyclone (ECR) resonance sputtering, etc. (FIG. 12). , Nitrogen and argon are used.

  A resist pattern 9d that covers the region where the thin film 6 is to be formed is formed by photolithography (FIG. 13), and the AlN in the region not masked by etching is removed using the resist pattern 9d as a mask. For etching AlN, wet etching or dry etching may be used.

  The resist pattern 9d is peeled off and an AlN thin film 6 is formed (FIG. 14).

  Here, the thin film 6 is formed by etching away unnecessary portions after depositing AlN. However, the thin film 6 is formed at a predetermined position by using the lift-off method used for forming the source / drain electrodes 4a and 4b and the gate electrode 5. May be.

  Here, AlN used for the thin film 6 has a larger band gap than the band gap of the electron supply layer 3.

  Here, the thin film as the protective film is formed after the gate electrode is formed, but it may be formed after the source / drain electrode is formed (before the gate electrode is formed) or before the source / drain electrode is formed.

  Before the formation of the source / drain electrodes 4a and 4b, AlN is deposited on the epitaxial substrate formed up to the electron supply layer 3 by electron beam evaporation, CVD, MBE, or sputter evaporation, and the thin film 6 is formed by the above-described process. Alternatively, an epitaxial substrate formed by epitaxially growing an AlN layer following the electron supply layer during crystal growth of the epitaxial substrate may be used.

  Next, the thin film 8 is formed on the surface on which the source / drain electrodes 4a and 4b, the gate electrode 5, and the thin film 6 made of AlN are formed. Here, the case where SiN is used as the thin film 8 will be described.

  SiN is deposited by electron beam evaporation, CVD, MBE, or sputter evaporation (FIG. 15).

  A resist pattern 9e is formed by photolithography so as to cover the thin film 8 deposited on the surface of the electron supply layer 3 (FIG. 16).

  The thin film 8 in a region not covered with the resist is removed by wet etching or dry etching. Thereafter, the resist is peeled and removed (FIG. 17).

  Although the manufacturing process of the nitride semiconductor device according to the first embodiment has been described in the order of formation of the source / drain electrodes 4a and 4b, formation of the gate electrode 5, formation of the thin film 6, and formation of the thin film 8, the formation of the thin film 6 and the thin film 8 May be manufactured in the order of formation, source / drain electrodes 4a and 4b, and gate electrode 5 formation, source / drain electrodes 4a and 4b formation, thin film 6 formation, thin film 8 formation, gate electrode 5 formation, and thin film 6 formation, source / drain electrodes 4a and 4b formation, gate electrode 5 formation, thin film 8 formation, source / drain electrodes 4a and 4b formation, thin film 6 formation, gate electrode 5 formation, thin film 8 formation, and thin film 8 thin film 6 It may be in the order of forming earlier.

  Here, the manufacturing process in the order of forming the thin film 6, forming the source / drain electrodes 4a and 4b, forming the thin film 8, and forming the gate electrode 5 will be described. Here, a case where an epitaxial substrate formed by epitaxially growing an AlN layer as the thin film 6 following the electron supply layer 3 during crystal growth will be described.

  First, a resist pattern 9f having an opening in a region where the source / drain electrodes 4a and 4b are to be formed is formed (FIG. 18). Similarly to the above, the source / drain electrodes 4a and 4b are formed by the lift-off method. However, since the band gap of AlN is large, a low contact resistance cannot be obtained. Therefore, it is desirable to first remove AlN in the source / drain electrode formation region by wet etching or dry etching, and then form the source / drain electrodes 4a and 4b by a lift-off method (FIG. 19).

  In order to further reduce the contact resistance, the electrode metal may be formed after the high-concentration n-type impurity region is formed in the source / drain regions as described above. At this time, an ion species that becomes an n-type impurity such as Si may be implanted with AlN attached, and this AlN may also be used as a cap layer in the active heat treatment (FIG. 20).

  Subsequently, the source / drain electrodes 4a and 4b are formed by a lift-off method. Since AlN in this region is doped with n-type impurities at a high concentration, a low contact resistance can be obtained without removing AlN. In order to further reduce the contact resistance, AlN in the source / drain electrode region is further removed as well as a part of the electron supply layer 3 or the interface with the channel layer 2 below the source / drain electrode region. It is desirable to form 4a and 4b (FIG. 21).

  Next, an AlN region having a function as the thin film 6 and a resist pattern 9g covering the source / drain electrodes 4a and 4b are formed, unnecessary AlN regions are removed by wet etching or dry etching, and the thin film 6 made of AlN. (FIG. 22). Following the resist removal, SiN, which is the thin film 8, is formed (FIG. 23).

  Next, a resist pattern 9h having openings on the gate electrode forming region 11 and the thin film 8 region on the thin film 6 and the source / drain electrodes 4a and 4b is formed (FIG. 24), and unnecessary by wet etching or dry etching. After removing the SiN region and removing the resist, a resist pattern having an opening in the gate electrode formation region 11 is formed again, and the gate electrode 5 is formed by a lift-off method (FIG. 25A).

  Although the resist pattern was formed again for forming the gate electrode 5, the gate electrode 5 can be formed by self-alignment by depositing the gate electrode metal after removing the unnecessary region of SiN with the previous resist pattern 9h. Since the gate electrode is provided in the field plate structure, the current collapse can be suppressed and the breakdown voltage can be improved (FIG. 25B).

In FIG. 26, the length L _i1 of the thin film 6 from the gate electrode end 5eg on the drain electrode side toward the drain electrode is preferably ½ or less of the gate-drain distance L _gd . Furthermore, it is preferable that L _i1 is as short as possible because the on-resistance can be reduced. However, if L _i1 = 0, the two-dimensional electron gas concentration under the gate electrode end on the drain side where the electric field concentrates increases, and the breakdown voltage decreases. Therefore, it is necessary to cover at least the gate electrode end on the drain side with the thin film 6. Further, as shown in FIG. 27 of the element top view, the length in the gate width direction is the same as that of the element activation region 12 (FIG. 27A) or over the element isolation region 13 which is larger than that. Good (FIG. 27B).

  In the first embodiment, the thin film 8 and the thin film 6 are described as having the same film thickness. However, when the band gap energy of the thin film 6 and the thin film 8 is larger than that of the electron supply layer 3, the thin film is thick. Then, the piezo effect is increased by increasing the stress with the semiconductor, and the two-dimensional electron gas concentration is increased. Therefore, it is more desirable that the thickness of the thin film 8 is thicker than that of the thin film 6 because the effect becomes larger.

<A-3. Operation>
It operates as a high electron mobility transistor realizing a high breakdown electric field and a high electron mobility by reducing current collapse and maintaining a withstand voltage. By using a two-dimensional electron gas, high electron mobility is realized.

<A-4. Effect>
According to the first embodiment of the present invention, in the semiconductor device, the semiconductor device according to the present invention is a heterojunction nitride semiconductor device, and is a channel layer made of a nitride semiconductor formed on the substrate 1 2, an electron supply layer 3 made of a nitride semiconductor having a larger band gap than the channel layer 2 formed on the channel layer 2, a gate electrode 5 selectively formed on the electron supply layer 3, On the supply layer 3, the source and drain electrodes 4 a and 4 b formed with the gate electrode 5 sandwiched therebetween, and the drain electrode side end of the gate electrode 5 on the drain electrode side of the gate electrode 5 on the electron supply layer 3 A thin film 8 which is a first thin film which is formed in the first region excluding the vicinity and which acts on the two-dimensional electron gas concentration formed at the interface between the channel layer 2 and the electron supply layer 3 corresponding to the first region; A two-dimensional electron gas concentration formed in the second region near the drain electrode side end of the gate electrode 5 on the electron supply layer 3 and formed at the interface between the channel layer 2 and the electron supply layer 3 corresponding to the second region. And the thin film 6 that is the second thin film that lowers the concentration below that corresponding to the first region, and the action of the different thin film 8 and thin film 6 makes the area other than the vicinity of the gate electrode 5 (especially the drain electrode). Since the two-dimensional electron gas concentration in the first region) is high, the on-resistance can be reduced and current collapse can be reduced, and the breakdown voltage is maintained because the two-dimensional electron gas concentration in the vicinity of the gate electrode 5 (second region) is low. It becomes possible.

  In addition, since the concentration of the two-dimensional electron gas in the vicinity of the gate electrode (second region) and other regions is adjusted by the type and arrangement of the thin film covering the semiconductor surface, it can be formed with good controllability and reproducibility.

According to the first embodiment of the present invention, in the semiconductor device, the channel layer 2 and the electron supply layer 3 include at least two layers of Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1,0). ≦ y ≦ 1, 0 ≦ x + y ≦ 1, x and y do not take 1 at the same time) to form a two-dimensional structure formed at the interface between the channel layer 2 and the electron supply layer 3 A high electron mobility transistor using an electron gas can be realized.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the thin films 8 and 6 that are the first and second thin films are thin films having a band gap energy larger than that of the electron supply layer 3. , 6 can be increased, the two-dimensional electron gas concentration in the corresponding region can be increased, the on-resistance can be reduced, and the current collapse can be reduced.

  According to the first embodiment of the present invention, in the semiconductor device, the thin film 8 that is the first thin film is thicker than the thin film 6 that is the second thin film. Can be formed, the on-resistance can be reduced, and the current collapse can be reduced.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the thin film 8 as the first thin film is a nitride containing any of Si, C, Ge, Sn, Pb, S, Se, Te, The thin film 6 which is an oxide or oxynitride thin film and is the second thin film is a nitride, oxide or oxynitride containing Al, or Ga, Ti, V, Nb, Zr, Hf, Ta Therefore, the on-resistance is reduced by increasing the two-dimensional electron gas concentration by the action of the thin film 8, the current collapse is reduced, and the two-dimensional electron gas by the action of the thin film 6. The breakdown voltage can be maintained by making the concentration lower than that of the thin film 8.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the high concentration impurity region 7 which is an impurity region formed in the channel layer 2 and the electron supply layer 3 below the source and drain electrodes 4a and 4b is further provided. By providing, the on-resistance can be further reduced.

  Further, according to the first embodiment of the present invention, in the semiconductor device, the second region is at least half of the distance from the gate electrode 5 to the drain electrode 4b, thereby realizing a higher breakdown voltage. it can.

  In addition, according to the first embodiment of the present invention, in the method of manufacturing a semiconductor device, a method of manufacturing a heterojunction nitride semiconductor device, comprising: (a) a channel layer made of a nitride semiconductor on a substrate 1; 2, (b) forming an electron supply layer 3 made of a nitride semiconductor having a larger band gap than the channel layer 2 on the channel layer 2, and (c) a gate on the electron supply layer 3. A step of selectively forming the electrode 5; (d) a step of forming the source and drain electrodes 4a and 4b with the gate electrode 5 sandwiched and separated on the electron supply layer 3; Two-dimensional electrons formed at the interface between the channel layer 2 and the electron supply layer 3 corresponding to the first region in the first region excluding the vicinity of the drain electrode side end of the gate electrode 5 on the drain electrode side of the gate electrode 5 A step of forming a thin film 8 that is a first thin film that affects the gas concentration, and (f) a second region in the vicinity of the drain electrode side end of the gate electrode 5 on the electron supply layer 3 corresponds to the second region. Forming a thin film 6 that is a second thin film that acts on the two-dimensional electron gas concentration formed at the interface between the channel layer 2 and the electron supply layer 3 and lowers the concentration below that corresponding to the first region. By providing the two-dimensional electron gas concentration other than the vicinity of the gate electrode 5 (especially the first region on the drain electrode side) due to the action of the different thin film 8 and thin film 6, the on-resistance can be reduced and the current collapse can be reduced, and Since the two-dimensional electron gas concentration in the vicinity of the gate electrode 5 (second region) is low, the breakdown voltage can be maintained.

<B. Second Embodiment>
<B-1. Configuration>
In the second embodiment, as described in the first embodiment, the two-dimensional electron gas concentration is not adjusted by two kinds of thin films (the thin film 6 as the second thin film and the thin film 8 as the first thin film). One type of thin film (third thin film) is used to adjust the two-dimensional electron gas concentration.

  Here, one type of thin film is a nitride or oxide containing Al, an oxynitride, or an oxide of Ga, Ti, V, Nb, Zr, Hf, or Ta, and the drain electrode of the gate electrode 5 The film thickness of the thin film 15 as the third thin film covering the surface of the electron supply layer in the vicinity of the gate electrode end (second region) on the side of this side covers the other surface of the electron supply layer (particularly the first region on the drain electrode side). A case where the structure is thinner than the thickness of the thin film 15 will be described. Since the process up to the formation of each layer (FIG. 3) is the same as that of the first embodiment, the description of that part is omitted, and the subsequent steps will be described. Note that the thin film 15 as the third thin film has a band gap energy larger than that of the electron supply layer 3.

<B-2. Manufacturing process>
In FIG. 28, the thin film 15 covering the surface of the electron supply layer 3 is made of a nitride or oxide containing Al, an oxynitride, or an oxide of Ga, Ti, V, Nb, Zr, Hf, or Ta. Thus, the film thickness of the thin film 15 covering the surface of the electron supply layer 3 in the vicinity of the gate electrode end (second region) on the drain electrode side of the gate electrode is smaller than the film thickness of the thin film covering the other surface of the electron supply layer. It is a longitudinal cross-sectional view in the case of becoming a structure.

In the first embodiment, the structure of two types of thin films (thin film 6 and thin film 8) has been described. Here, a case where one kind of thin film 15 such as Al ₂ O ₃ is used will be described.

When Al ₂ O ₃ as the thin film 15 is formed on the surface of the electron supply layer 3, the two-dimensional electron gas concentration increases. Further, the two-dimensional electron concentration is further increased by increasing the film thickness.

Compared to the conventional case where the surface of the electron supply layer 3 is covered with a uniform film thickness, the surface of the electron supply layer 3 other than the vicinity of the gate electrode end on the drain electrode side of the gate electrode 5 (particularly, the drain electrode side is the first region). The thickness of Al ₂ O ₃ covering the gate electrode is thicker than the thickness of Al ₂ O ₃ covering the surface of the electron supply layer in the vicinity of the gate electrode end (second region). The electric gas concentration increases and the on-resistance can be reduced. That is, by changing the film thickness, the two-dimensional electron gas concentration formed at the interface of the electron supply layer 3 corresponding to the second region is changed to the two-dimensional electron gas formed at the interface of the electron supply layer 3 corresponding to the first region. It can be lower than the concentration.

  The manufacturing method of the nitride semiconductor device according to the present embodiment will be described with reference to FIGS.

FIG. 29 shows the thin film 15 formed on the electron supply layer 3. For example, the deposition is performed by electron beam evaporation, CVD, MBE, or sputtering. Here, the case where it forms by sputtering deposition, for example is demonstrated. Al or Al ₂ O ₃ is used as the target, and oxygen or argon is used as the sputtering gas. The high concentration impurity region 7 and the source / drain electrodes 4a and 4b may be formed by the same process as described in the first embodiment, and the high concentration impurity region is formed before the thin film 15 is formed on the electron supply layer 3. 7 and source / drain electrodes 4 a and 4 b may be formed, and then the thin film 15 may be formed on the electron supply layer 3. Further, before the high concentration impurity region 7 is formed in the Al ₂ O ₃ 15, the high concentration impurity region 7 may be formed after the thin film 15 in the high concentration impurity region is removed by etching. Al ₂ O ₃ 15 below the source / drain electrode region may be removed after forming the electrode, and further, a part of the electron supply layer 3 or even the interface with the channel layer 2 may be removed under the source / drain electrode region. 4a and 4b may be formed.

  Here, the process from the time (FIG. 30) when the formation of the thin film 15 is completed after the high concentration impurity region 7 and the source / drain electrodes 4a and 4b are formed will be described.

A resist pattern 9k having an opening in the vicinity of the gate electrode formation region 11 and the gate electrode end (length L _i2 ) is formed by photolithography (FIG. 31).

  After thinning the thin film 15 at the resist opening by etching (FIG. 32), the resist 9k is peeled off and a resist pattern 9c2 having an opening in the gate electrode formation region 11 is formed.

  The thin film 15 in the gate electrode formation region is removed by etching (FIG. 33). Subsequently, gate metal is deposited by self-alignment, and the gate electrode 5 is formed by lift-off (FIG. 34).

  33, after removing the thin film 15, the resist 9c2 is removed, a resist pattern 9c3 having an opening in the gate electrode formation region 11b is formed (FIG. 35), and the gate electrode 5 is formed by lift-off. A structure in which a part of the gate electrode 5 is disposed on the thin thin film 15 (field plate structure) is formed. Therefore, the electric field concentrated on the drain end of the gate electrode 5 can be relaxed, and a structure capable of improving the breakdown voltage can be formed (FIG. 36).

  In the second embodiment, the thin film 15 is formed by etching a thin region. However, the thin film 15 is removed by etching with the resist pattern 9k of FIG. 31 (FIG. 37), and the thin film 15 is formed thin again on the entire surface to form a gate electrode. The thin thin film 15 in the region may be removed, and the gate electrode 5 may be formed there.

  Further, after the thin film 15 is removed by etching (FIG. 37), a resist pattern is formed in areas other than the region 2 and the gate formation region, and the thin film 15 is thinly formed only in this region. The gate electrode 5 may be formed after forming the pattern and removing the thin film 15 where the gate electrode formation region is thin by etching.

  Further, after the thin film 15 is removed by etching with the resist pattern 9k in FIG. 31, the gate electrode 5 is formed by lift-off using a new resist pattern 9c2 (FIG. 38), and the thin film 15 may be formed thin on the entire surface. (FIG. 39). In this case, when the thin film 15 exists on the source / drain electrodes 4a, 4b and the gate electrode 5 in order to establish conduction with each electrode, it is necessary to etch away all of the thin film 15 or a part of each electrode. There is.

Here, it is desirable that the length L _Al2O3 (L _i2 ) of the thin thin film 15 at the end of the gate electrode is ½ or less of the gate-drain distance L _gd . Furthermore, it is preferable that L _Al2O3 is as short as possible because the on-resistance can be reduced. However, if L _Al2O3 = 0, the two-dimensional electron gas concentration under the gate electrode end on the drain side where the electric field is concentrated increases, and the breakdown voltage decreases. For this reason, it is necessary to reduce the thickness of the thin film 15 at least at the gate electrode end on the drain side. The length in the gate width direction is the same as that of the element activation region 12 (FIG. 27A) as shown in FIG. It may be over the element isolation region 13 as described above (FIG. 27B).

<B-3. Effect>
According to the second embodiment of the present invention, a semiconductor device is a heterojunction nitride semiconductor device, which is formed on a channel layer 2 made of a nitride semiconductor formed on a substrate 1 and on the channel layer 2. An electron supply layer 3 made of a nitride semiconductor having a larger band gap than the formed channel layer 2, a gate electrode 5 selectively formed on the electron supply layer 3, and a gate electrode on the electron supply layer 3 5 is formed on the electron supply layer 3 between the source and drain electrodes 4a and 4b, and the source electrode 4a and drain electrode 4b, which are spaced apart from each other, and is formed at the interface between the channel layer 2 and the electron supply layer 3. A thin film 15 which is a third thin film acting on the two-dimensional electron gas concentration. The thin film 15 excludes the vicinity of the drain electrode side end of the gate electrode 5 on the drain electrode side of the gate electrode 5. The film thickness of the thin film 15 in the first area and the second area is different from the film thickness formed in the first area and the film thickness formed in the second area near the drain electrode side end of the gate electrode 5. The difference in the action causes a difference in action, and since the two-dimensional electron gas concentration in the area other than the vicinity of the gate electrode 5 (especially the first area on the drain electrode side) is high, the on-resistance can be reduced and the current collapse can be reduced. Since the two-dimensional electron gas concentration in the (second region) is low, the breakdown voltage can be maintained.

  According to the second embodiment of the present invention, in the semiconductor device, the thin film 15 as the third thin film is formed at the interface between the channel layer 2 and the electron supply layer 3 corresponding to the first region and the second region, respectively. The concentration corresponding to the second region is lower than the concentration corresponding to the first region, thereby avoiding the concentration of the electric field at the drain end of the gate electrode 5, and the like. In this region, the two-dimensional electron gas concentration can be set higher than the concentration in the second region, and the current collapse can be reduced and the breakdown voltage can be maintained.

  According to the second embodiment of the present invention, in the semiconductor device, the thin film 15 as the third thin film is a thin film having a band gap energy larger than that of the electron supply layer 3, so that the thickness of the thin film 15 is increased. In this case, the two-dimensional electron gas concentration in the corresponding region can be increased, the on-resistance can be reduced by increasing the drain current, and the current collapse can be reduced.

Further, according to the second embodiment of the present invention, in the semiconductor device, the thin film 15 that is the third thin film has a film thickness formed in the first region larger than that formed in the second region. Thus, the two-dimensional electron gas concentration is increased by Al ₂ O ₃ formed as the thin film 15, and the two-dimensional electron concentration is further increased by increasing the film thickness. Therefore, the drain current increases and the on-resistance decreases. Further, an electric field concentrated on the drain end of the gate electrode 5 can be relaxed, and a structure capable of improving the breakdown voltage can be formed.

  According to the second embodiment of the present invention, in the semiconductor device, the thin film 15 as the third thin film is made of nitride, oxide, or oxynitride containing Al, or Ga, Ti, V, Nb, Because it is a thin film of one of the oxides of Zr, Hf, and Ta, the increase in the two-dimensional electron gas concentration in the corresponding region can be adjusted according to the difference in film thickness, reducing current collapse and maintaining the breakdown voltage Can be realized.

  According to the second embodiment of the present invention, in the method for manufacturing a semiconductor device, a method for manufacturing a heterojunction nitride semiconductor device, comprising: (a) a channel layer made of a nitride semiconductor on a substrate 1; 2, (b) forming an electron supply layer 3 made of a nitride semiconductor having a larger band gap than the channel layer 2 on the channel layer 2, and (c) a gate on the electron supply layer 3. A step of selectively forming the electrode 5; (d) a step of forming a space between the source and drain electrodes 4a and 4b on the electron supply layer 3 with the gate electrode 5 interposed therebetween; and (e) a source electrode 4a, Forming a thin film 15 that is a third thin film acting on the two-dimensional electron gas concentration formed on the interface between the channel layer 2 and the electron supply layer 3 on the electron supply layer 3 between the drain electrodes 4b, Process e) shows the film thickness formed in the first region excluding the vicinity of the drain electrode side end portion of the gate electrode 5 on the drain electrode side of the gate electrode 5 and the second region in the vicinity of the drain electrode side end portion of the gate electrode 5. In the step of forming the thin film 15 which is the third thin film having a different thickness from the formed film thickness, a difference in action occurs due to a difference in the film thickness of the thin film 15 in the first region and the second region. Since the two-dimensional electron gas concentration in the other regions (especially the drain electrode side in the first region) is high, the on-resistance can be reduced to reduce current collapse, and the two-dimensional electron gas concentration in the vicinity of the gate electrode 5 (second region) is low. Therefore, the withstand voltage can be maintained.

<C. Embodiment 3>
<C-1. Configuration>
In the third embodiment, as described in the second embodiment, the two-dimensional electron gas concentration is adjusted by one type of thin film, and the thin film includes an element that serves as a donor in the nitride semiconductor. The case where consists of will be described. Since the processes up to the formation of each layer (FIG. 3) are the same as those in the first and second embodiments, the description thereof is omitted.

FIG. 40 shows that the thin film 16 as the third thin film covering the surface of the electron supply layer 3 is a nitride or oxide containing at least one of Si, C, Ge, Sn, Pb, S, Se and Te, or oxynitriding The thin film 16 covering the surface of the electron supply layer 3 near the gate electrode end on the drain electrode side of the gate electrode is thinner than the thin film 16 covering the other surface of the electron supply layer 3. It is a longitudinal cross-sectional view in the case of becoming. In the second embodiment, the thin film is described as having a structure using, for example, Al ₂ O ₃ . Here, the case of SiN made of, for example, Si serving as a donor in a nitride semiconductor will be described. The subsequent steps will be described.

<C-2. Manufacturing process>
When a thin film including an element serving as a donor in the nitride semiconductor, for example, a thin film 16 made of SiN is formed on the surface of the electron supply layer 3, the two-dimensional electron gas concentration is increased by Si in SiN. By increasing the film thickness, the strain between the electron supply layer 3 and the thin film 16 increases, the piezo effect increases, and the two-dimensional electron concentration further increases. Compared to the case where the surface of the electron supply layer 3 is conventionally covered with a uniform film thickness, the film thickness of SiN covering the surface of the electron supply layer other than the vicinity of the gate electrode end on the drain electrode side of the gate electrode is near the gate electrode end. By making the structure thicker than the thickness of SiN covering the surface of the electron supply layer, the two-dimensional gas concentration between the gate and drain electrodes increases, and the on-resistance can be reduced. The manufacturing method of the nitride semiconductor device according to the third embodiment will be described with reference to FIGS.

  FIG. 41 shows the thin film 16 formed on the electron supply layer 3. For example, the deposition is performed by electron beam evaporation, CVD, MBE, or sputtering. Here, the case where it forms by sputtering deposition, for example is demonstrated. Si or SiN is used as the target, and nitrogen or argon is used as the sputtering gas. The high concentration impurity region 7 and the source / drain electrodes 4a and 4b may be formed in the same process as described in the first and second embodiments, and the high concentration before the thin film 16 is formed on the electron supply layer 3. The impurity region 7 and the source / drain electrodes 4 a and 4 b may be formed, and then the thin film 16 may be formed on the electron supply layer 3. Further, before forming the high concentration impurity region 7 in the thin film 16 made of SiN, the high concentration impurity region 7 may be formed after the thin film 16 in the high concentration impurity region is removed by etching.

  Here, the process from the time (FIG. 42) when the formation of the thin film 16 is completed after the high concentration impurity region 7 and the source / drain electrodes 4a and 4b are formed will be described.

A resist pattern 9m having an opening in the vicinity of the gate electrode formation region 11 and the gate electrode end (length L _i2 ) is formed by photolithography (FIG. 43). After thinning the thin film 16 by etching (FIG. 44), the resist 9m is peeled off and a resist pattern 9c3 having an opening in the gate formation region 11 is formed.

  The thin film 16 in the gate electrode formation region is removed by etching (FIG. 45), and then the gate electrode 5 is deposited by self-alignment and formed by lift-off (FIG. 46).

  43, after thinning the thin film 16, the resist pattern 9m is removed, and a resist pattern 9c3 having openings in the gate electrode formation region 11b and a part of the region 2 on the thin film 16 is formed (FIG. 47). By forming the gate electrode 5 by lift-off, a part of the gate electrode 5 is arranged on the thin thin film 16 (field plate structure), so that the electric field concentrated on the drain end of the gate electrode 5 can be relaxed, A structure capable of improving the breakdown voltage can be formed (FIG. 48).

  In the third embodiment, the thin film 16 is formed by etching a thin region. However, the thin film 16 is removed by etching with the resist pattern 9m of FIG. 43 (FIG. 49), and the thin film 16 is formed again on the entire surface to form a gate electrode. The thin film 16 in the region may be removed, and the gate electrode 5 may be formed there.

  Further, the thin film 16 is thinly formed only in the region where the thin film 16 is removed by etching (FIG. 49), a resist pattern is formed outside the gate electrode formation region, and the thin thin film 16 is removed by etching, and then the gate electrode 5 is formed. May be.

  Further, after the thin film 16 is removed by etching with the resist pattern 9m in FIG. 49, the gate electrode 5 is formed by lift-off (FIG. 50), and then the thin film 16 may be thinly formed on the entire surface (FIG. 51).

  In this case, all of the thin film 16 on the source / drain electrodes 4a and 4b and the gate electrode 5 or a part of the thin film 16 of each electrode needs to be etched away in order to establish conduction with each electrode.

Here, the length L _SiN (L _i2 ) of the thin thin film 16 at the end of the gate electrode is desirably set to ½ or less of the gate-drain distance L _gd . Further, it is preferable that L _SiN be as short as possible because the on-resistance can be reduced. However, if L _SiN = 0, the two-dimensional electron gas concentration under the gate electrode end on the drain side where the electric field concentrates increases, and the breakdown voltage decreases. For this reason, it is necessary to reduce the thickness of the thin film 16 at least at the gate electrode end on the drain side. Further, the length in the gate width direction is the same as that of the element activation region 12 as shown in FIG. 27 of the element top view as in the case of the first embodiment (FIG. 27A) or more. May be passed over the element isolation region 13 (FIG. 27B).

<C-3. Effect>
According to the third embodiment of the present invention, in the semiconductor device, the thin film 16 that is the third thin film is a nitride or oxide containing any of Si, C, Ge, Sn, Pb, S, Se, and Te. Or, because it is an oxynitride thin film, it contains an element that becomes a donor in a nitride semiconductor, so that the donor increases the two-dimensional electron gas concentration in the corresponding region, reduces the on-resistance, and reduces the current collapse. it can. Further, by changing the film thickness in the first region and the second region, the two-dimensional electron gas concentration in the second region can be made lower than that in the first region, and the breakdown voltage can be maintained.

<D. Embodiment 4>
<D-1. Configuration>
In the first to third embodiments, the structure in which the two-dimensional electron gas concentration is adjusted according to the type, arrangement, and film thickness of the thin film has been described. In this embodiment, plasma is used as the surface treatment for the surface of the electron supply layer before the thin film is formed. The case where the adjustment of the two-dimensional electron gas concentration is further increased by irradiation will be described.

  The surface of the electron supply layer made of a nitride semiconductor has surface traps and other surface levels due to the influence of nitrogen vacancies, residual oxygen or oxygen, and carbon and hydrogen during crystal growth. Cause an increase in. By irradiating the surface of this electron supply layer with plasma containing nitrogen such as nitrogen or ammonia, it becomes possible to compensate for nitrogen vacancies and suppress current collapse. Moreover, it becomes possible to compensate the surface level by irradiating with a plasma such as fluorine or chlorine which becomes a single negative ion, and current collapse can be suppressed. In addition, the two-dimensional electron gas concentration can be reduced by irradiation with oxygen plasma, and current collapse can be suppressed. These plasma treatments are preferably performed over the entire surface of the electron supply layer, but current collapse can be suppressed by performing at least the surface of the electron supply layer near the gate electrode end on the drain electrode side of the gate electrode.

  On the other hand, increasing the two-dimensional electron gas concentration in the vicinity of the gate electrode end (second region) on the drain electrode side of the gate electrode causes a decrease in breakdown voltage. By increasing the two-dimensional electron gas concentration in the first region), the sheet resistance can be reduced and the on-resistance can be reduced. Therefore, by irradiating the surface of the electron supply layer other than the vicinity of the gate electrode end with at least one plasma of argon and silicon, in the case of argon, nitrogen vacancies on the surface of the electron supply layer increase, and these nitrogen vacancies become donors. As a result, the two-dimensional electron gas concentration increases. Since silicon serves as a donor for an electron supply layer made of a nitride semiconductor, the two-dimensional electron gas concentration can be increased and the on-resistance can be decreased.

<D-2. Manufacturing process>
Next, a pretreatment process before forming a thin film will be described with reference to FIGS. 52 to 56, using a longitudinal sectional view, for describing a method for manufacturing a nitride semiconductor device according to the fourth embodiment. In addition, since the formation process of each layer is common with Embodiment 1-3, description is abbreviate | omitted.

  FIG. 52 shows, for example, a process before covering the surface of the electron supply layer 3 with a thin film, here, after the formation of the high concentration impurity region 7, the formation of the source / drain electrodes 4a and 4b, and the formation of the gate electrode 5. .

A resist pattern 9n having an opening in the vicinity of the gate electrode end (length L _i2 ) is formed by photolithography (FIG. 53). Then, at least one plasma irradiation of nitrogen, fluorine, chlorine, ammonia, and oxygen as the second surface treatment is performed on the second region.

Subsequently, the thin film described in the first to third embodiments is deposited. Here, a case where the thin film 15 of Al ₂ O ₃ is deposited by sputtering will be described. After the plasma irradiation, the thin film 15 is deposited by sputtering, and the thin film 15 is formed near the end of the gate electrode (second region) by lift-off (FIG. 54).

FIG. 55 shows each electrode and thin film covered with a resist pattern 9p. Here, at least one of argon and silicon plasma irradiation is performed as a first surface treatment on a region including the first region, and subsequently, a thin film 15 of Al ₂ O ₃ is deposited by sputtering and formed by lift-off ( FIG. 56). At this time, the thickness of the thin film 15 is larger than that of the thin film 15 as described in the second embodiment.

  Note that at least one plasma irradiation of argon and silicon as the first surface treatment for the first region and at least one plasma irradiation of nitrogen, fluorine, chlorine, ammonia and oxygen as the second surface treatment for the second region are as follows: , Either one may be performed.

  If nitrogen, fluorine, chlorine, ammonia, or oxygen gas can be introduced by a sputtering device, these plasma irradiations can be performed, and the surface is not contaminated without being exposed to the atmosphere between the plasma irradiation process and the thin film deposition process. Thin film deposition becomes possible, and the effect becomes great. By irradiating the surface of the electron supply layer with plasma, current collapse can be suppressed, ON resistance can be reduced, and current collapse can be further suppressed by adopting a structure that adjusts the two-dimensional electron gas concentration according to the type, arrangement, and film thickness of the thin film. The on-resistance can be reduced.

  In the fourth embodiment, the thin film 15 is formed as the third thin film. However, even if the two types of thin films (thin films 6 and 8) shown in the first embodiment are used, the present embodiment is implemented. The same effects can be obtained by performing the first and second surface treatments shown in the fourth embodiment.

  Even when the thin film 14 described later is used, the same effect can be obtained by performing the first and second surface treatments.

<D-3. Effect>
According to the fourth embodiment of the present invention, in the semiconductor device, the electron supply layer 3 includes at least a plasma treatment as a first surface treatment in the first region and a plasma treatment as a second surface treatment in the second region. By having a surface on which any surface treatment is performed, it is possible to compensate for nitrogen vacancies, to suppress surface collapse by compensating for surface states, and to reduce the two-dimensional electron gas concentration.

  According to the fourth embodiment of the present invention, in the semiconductor device, the first surface treatment in the first region is treatment with at least one plasma of argon and silicon, and the second surface treatment in the second region is , Nitrogen, fluorine, chlorine, ammonia, oxygen, and so on. As a result of the first surface treatment, nitrogen vacancies are increased by the first surface treatment, and the nitrogen vacancies act as donors. The concentration increases, and the second surface treatment can compensate for nitrogen vacancies and surface states, reduce current collapse, and reduce the two-dimensional electron gas concentration.

  According to the fourth embodiment of the present invention, in the method of manufacturing a semiconductor device, (e) on the electron supply layer 3, the vicinity of the drain electrode side end of the gate electrode 5 is formed on the drain electrode side of the gate electrode 5. The step of forming the thin film 8 according to the first embodiment, which is the first thin film acting on the two-dimensional electron gas concentration formed at the interface between the channel layer 2 and the electron supply layer 3 corresponding to the first region, except for the first region Is a step of performing a first surface treatment on the first region on the surface of the electron supply layer 3 to form the thin film 8 according to the first embodiment, which is a first thin film. Since the vacancies act as donors, the two-dimensional electron gas concentration can be increased and the on-resistance can be reduced.

  According to the fourth embodiment of the present invention, in the method for manufacturing a semiconductor device, (f) the second region in the vicinity of the drain electrode side end of the gate electrode 5 on the electron supply layer 3 In the first embodiment, the second thin film acts on the concentration of the two-dimensional electron gas formed at the interface between the channel layer 2 corresponding to the region and the electron supply layer 3 and lowers the concentration below that corresponding to the first region. The step of forming the thin film 6 is a step of performing the second surface treatment on the second region on the surface of the electron supply layer 3 to form the thin film 6 in the first embodiment which is the second thin film. By compensating for the above, the current collapse can be suppressed by compensating the surface level, and the two-dimensional electron gas concentration can be reduced.

  According to the fourth embodiment of the present invention, in the method of manufacturing a semiconductor device, (e) the channel layer 2 and the electron supply layer 3 interface on the electron supply layer 3 between the source electrode 4a and the drain electrode 4b. The step of forming the thin film 15 which is the third thin film acting on the two-dimensional electron gas concentration formed on the surface of the electron supply layer 3 includes the first surface treatment in the first region, the second surface treatment in the second region, In the process of forming the thin film 15 as the third thin film by performing at least one of the surface treatments described above, nitrogen vacancies are increased by the first surface treatment, and the nitrogen vacancies act as donors. The dimensional electron gas concentration is increased to compensate for nitrogen vacancies, and the current state is suppressed by compensating the surface level by the second surface treatment, and the two-dimensional electron gas concentration can be reduced.

<E. Embodiment 5>
<E-1. Configuration>
In the fourth embodiment, the case where the current collapse can be suppressed and the on-resistance can be further reduced by performing plasma irradiation on the surface of the electron supply layer before the thin film formation is described. In the fifth embodiment, the electrons before the thin film formation are described. The case where the adjustment of the two-dimensional electron gas concentration is further increased by performing ion implantation as the surface treatment for the surface of the supply layer 3 will be described.

  One method is to increase the two-dimensional electron gas concentration in order to reduce the on-resistance, but the first surface with respect to the surface of the electron supply layer other than the vicinity of the gate electrode end (especially the drain electrode side is the first region). As the treatment, at least one ion of Si, C, O, Ge, Sn, and Pb that acts as a donor in the nitride semiconductor is implanted, and an activation heat treatment is performed, whereby the two-dimensional electron gas concentration can be increased and the on-resistance is reduced. It becomes possible.

<E-2. Manufacturing process>
Next, a manufacturing process of the nitride semiconductor device according to the fifth embodiment will be described using FIG. 57 to FIG. In addition, since the formation process of each layer is common with Embodiment 1-3, description is abbreviate | omitted.

  FIG. 57 shows, for example, a process before covering the surface of the electron supply layer 3 with a thin film, here, after the formation of the high concentration impurity region 7, the formation of the source / drain electrodes 4a and 4b, and the formation of the gate electrode 5. .

A resist pattern 9n having an opening in the vicinity of the gate electrode end (length L _i2 ) is formed by photolithography (FIG. 58).

The thin film described in the first to third embodiments is deposited. Here, a case where the thin film 15 of Al ₂ O ₃ is deposited by sputtering will be described. The thin film 15 is deposited by sputtering, and the thin film 15 is formed near the end of the gate electrode by lift-off (FIG. 59). Here, as described in the fourth embodiment, the effect is enhanced by performing at least one plasma irradiation of nitrogen, fluorine, chlorine, ammonia, and oxygen before the thin film 15 is deposited.

  In FIG. 60, a region where ion implantation is not performed is covered with a resist pattern 9q. Thereafter, at least one ion 10b of Si, C, O, Ge, Sn, and Pb as a first surface treatment is implanted into the region not covered with the resist pattern 9q (FIG. 61).

A thin film 15 of Al ₂ O ₃ is deposited by sputtering and formed by lift-off (FIG. 62). At this time, the thickness of the thin film 15 is larger than that of the thin film 15 as described in the second embodiment. Furthermore, as described in Embodiment 4, the effect is enhanced by performing at least one plasma irradiation of argon and silicon. After removing the resist, heat treatment is performed to activate the implanted ions. As a result, the two-dimensional electron gas concentration in the implanted region can be increased, and the on-resistance can be decreased.

Although the case where a thin film is deposited in the implantation region after implantation has been described here, implantation and heat treatment may be performed after deposition of the thin film. FIG. 63 shows a case where a resist pattern 9q is formed after the thin film 15 of Al ₂ O ₃ is formed. Here, at least one ion 10b of Si, C, O, Ge, Sn, and Pb may be implanted, and activation heat treatment may be performed after the resist is stripped.

  Although the thin film 15 as the third thin film is formed in the fifth embodiment, even if the two types of thin films (thin films 6 and 8) shown in the first embodiment are used, the present embodiment The same effect can be obtained by performing the first and second surface treatments shown in the fifth embodiment.

  Even when the thin film 14 described later is used, the same effect can be obtained by performing the first and second surface treatments. Here, the high concentration impurity layer is formed, and after the formation of the source / drain and gate electrodes, the surface treatment using plasma including ion implantation and the thin film formation are described in this order. The source / drain electrodes including the impurity layer formation and the gate electrode may be formed in this order.

<E-3. Effect>
According to the fifth embodiment of the present invention, in the semiconductor device, the first surface treatment in the first region is a treatment for implanting at least one ion 10b of Si, C, O, Ge, Sn, and Pb. By further performing the activation heat treatment, the two-dimensional electron gas concentration can be increased and the on-resistance can be decreased.

<F. Embodiment 6>
<F-1. Configuration>
In the fifth embodiment, the case where ions that can become donors are implanted into the surface of the electron supply layer 3 and heat treatment is performed to increase the two-dimensional electron gas concentration, suppress current collapse, and reduce the on-resistance. In the sixth embodiment, a case will be described in which the adjustment of the two-dimensional electron gas concentration is further increased by treating with a solution as a surface treatment for the surface of the electron supply layer 3 before forming a thin film.

  One method is to increase the two-dimensional electron gas concentration to reduce the on-resistance. However, the surface of the electron supply layer near the gate electrode end (second region) is treated with nitrogen such as ammonium ions as the second surface treatment. It is possible to compensate for nitrogen vacancies, and to suppress current collapse, and as a second surface treatment, it contains chlorine ions, hydroxide ions, and fluorine ions, which become one negative ion as a second surface treatment. By performing the solution treatment, it becomes possible to compensate for the surface state and suppress the current collapse. These solution treatments are preferably performed over the entire surface of the electron supply layer, but current collapse can be suppressed by performing at least the surface of the electron supply layer near the gate electrode end on the drain electrode side of the gate electrode.

  On the other hand, increasing the two-dimensional electron gas concentration in the vicinity of the gate electrode end on the drain electrode side of the gate electrode causes a decrease in breakdown voltage, so increasing the two-dimensional electron gas concentration in the region other than the vicinity of the gate electrode end It becomes possible to reduce the sheet resistance and the on-resistance. Therefore, the surface of the electron supply layer other than the vicinity of the end of the gate electrode (particularly the first region on the drain electrode side) is treated with a solution containing silicon ions as the first surface treatment, whereby an electron supply layer made of a nitride semiconductor. Therefore, the two-dimensional electron gas concentration can be increased and the on-resistance can be decreased.

<F-2. Manufacturing process>
Next, a pretreatment process before forming a thin film will be described with reference to FIGS. 64 to 68 using a longitudinal sectional view of the method for manufacturing the nitride semiconductor device according to the sixth embodiment. In addition, since the formation process of each layer is common with Embodiment 1-3, description is abbreviate | omitted.

FIG. 64 shows, for example, a step before covering the surface of the electron supply layer 3 with a thin film. Here, the high concentration impurity region 7 is formed, the source / drain electrodes 4a and 4b are formed, and the gate electrode 5 is formed. . A resist pattern 9r having an opening in the vicinity of the gate electrode end (length L _i2 ) is formed by photolithography (FIG. 65).

  Here, the surface of the electron supply layer 3 that is not covered with the resist pattern 9r is immersed in a solution containing at least one of chlorine ions, hydroxide ions, fluorine ions, and ammonium ions as the second surface treatment for the second region. Solution treatment.

Here, a case where an aqueous potassium hydroxide solution is used will be described as an example. After the solution treatment, the film is washed with water, and then the thin film described in the first to third embodiments is deposited. Here, a case where the thin film 15 of Al ₂ O ₃ is deposited by sputtering will be described.

  A thin film 15 is formed in the vicinity of the gate electrode end by lift-off (FIG. 66). FIG. 67 shows each electrode and thin film covered with a resist pattern 9q. The region including the first region not covered with the resist pattern 9q is immersed in a solution containing silicon ions, which is the first surface treatment, and the surface of the electron supply layer not covered with the resist pattern 9q is subjected to solution treatment. Here, the case where a cyclohexane solution is used as an example will be described.

  After the solution treatment, the substrate is washed with water. Subsequently, the thin film 15 is deposited by sputtering and formed by lift-off (FIG. 68). At this time, the thickness of the thin film 15 is larger than that of the thin film 15 as described in the second embodiment.

  Solution processing of the surface of the electron supply layer 3 suppresses current collapse, reduces on-resistance, and further reduces current collapse by adopting a structure that adjusts the two-dimensional electron gas concentration according to the type, arrangement, and film thickness of the thin film. The on-resistance can be reduced. Further, the ion implantation described in the fifth embodiment may be used in combination, and the effect is increased.

  In the sixth embodiment, the thin film 15 as the third thin film is formed. However, even when the two types of thin films (thin films 6 and 8) shown in the first embodiment are used, the present embodiment is implemented. The same effects can be obtained by performing the first and second surface treatments shown in Embodiment 6.

  Even when the thin film 14 described later is used, the same effect can be obtained by performing the first and second surface treatments.

<F-3. Effect>
According to the sixth embodiment of the present invention, in the semiconductor device, the first surface treatment in the first region is treatment with a solution containing silicon ions, and the second surface treatment in the second region is chlorine ions, water. By treatment with a solution containing at least one of oxide ions, fluorine ions, and ammonium ions, surface states can be compensated for and current collapse can be reduced.

<G. Embodiment 7>
<G-1. Configuration>
In the first to sixth embodiments, when the thin film covering the surface of the electron supply layer 3 is one or more and the band gap is larger than that of the electron supply layer, or before the thin film is formed, Although the ion implantation and the treatment with the solution have been described, here, the case where the thin film as the third thin film covering the surface of the electron supply layer 3 is made of GaN smaller than the band gap of the electron supply layer 3 will be described. Since the processes up to the formation of each layer (FIG. 3) are the same as those in the first to sixth embodiments, the description thereof will be omitted, and the subsequent steps will be described.

  FIG. 69 is a longitudinal sectional view when the thin film 14 covering the surface of the electron supply layer 3 is made of GaN. When a thin film 14 made of undoped GaN is stacked on the electron supply layer 3, the two-dimensional electron gas concentration decreases as the GaN film thickness increases. Therefore, by increasing the GaN film thickness in the vicinity of the gate electrode (second region) where the two-dimensional electron gas concentration is desired to be lowered, and reducing the GaN film thickness in other regions (particularly the first region on the drain electrode side) The two-dimensional electric gas concentration can be adjusted.

  FIG. 69 shows an example in which the n-type high concentration impurity region 7 is formed under the source / drain electrodes. FIG. 69 shows an example in which thick GaN is formed in the vicinity of the end of the gate electrode on the drain electrode side, and thin GaN is formed in the other portions, but the gate electrode 5 may be on the thick thin film 14 (FIG. 69). 70 (a) to (c), FIG. 71 (a)), a part of the gate electrode 5 may be on the thin film 14 (FIGS. 71 (b) and (c)).

<G-2. Manufacturing process>
The manufacturing method of the nitride semiconductor device according to the seventh embodiment will be described with reference to the longitudinal sectional views of FIGS. 72 to 79.

  FIG. 72 shows the thin film 14 formed on the electron supply layer 3. For example, MBE (Molecular Beam Epitaxy) or CVD (Chemical Vapor Deposition) is followed by epitaxial crystal growth after the formation of the electron supply layer 3. Is desirable. The thickness is preferably 5 to 500 nm. As described with reference to FIGS. 4 to 8 of the first embodiment, the high concentration impurity region 7 and the source / drain electrodes 4a and 4b are formed.

  Here, an example in which the high concentration impurity region 7 including the thin film 14 is formed is shown (FIG. 73). However, before the high concentration impurity region 7 is formed, the region other than the high concentration impurity region 7 is covered with a photoresist 9i and etched. After removing the thin film 14 in the high concentration impurity region (FIG. 74), the high concentration impurity region 7 may be formed to form the source / drain electrodes 4a and 4b (FIG. 75).

  The formation region of the thin film 14 made of thick GaN and the source / drain electrodes 4a and 4b are covered with a photoresist 9j (FIG. 76), and the thin film 14 other than the vicinity of the gate electrode is thinned by dry etching or wet etching (FIG. 77).

After removing the resist, the region other than the gate electrode formation region 11 is covered with a photoresist 9c. The thin film 14 in the gate electrode formation region 11 is removed by dry etching or wet etching (FIG. 78), and then the gate electrode 5 is formed by lift-off by self-alignment (FIG. 79). Here, it is desirable that the length L _GaN of the thick thin film 14 should be ½ or less of the gate-drain distance L _gd . Furthermore, it is preferable that _LGaN is as short as possible because it can reduce the on-resistance. However, if L _GaN = 0, the two-dimensional electron gas concentration under the gate electrode end on the drain side where the electric field concentrates increases, and the breakdown voltage decreases. Therefore, the thickness of GaN must be increased at least at the gate electrode end on the drain side. Further, the length in the gate width direction is the same as that of the element activation region 12 as shown in FIG. 27 of the element top view as in the case of the first embodiment (FIG. 27A) or more. May be passed over the element isolation region 13 (FIG. 27B). Here, an example in which the etching of GaN 14 is performed after the formation of the source / drain electrodes has been described, but a part of the thin film 14 may be thinned by etching the thin film 14 of GaN before the formation of the source / drain electrodes.

<G-3. Effect>
According to the seventh embodiment of the present invention, in the semiconductor device, the thin film 14 that is the third thin film is a thin film having a smaller band gap energy than the electron supply layer 3, so that the film thickness of the thin film 14 can be increased. For example, the two-dimensional electron gas concentration in the corresponding region decreases, and the two-dimensional electron gas concentration can be adjusted. Therefore, the current collapse can be reduced and the breakdown voltage can be maintained by adjusting the film thickness for each of the first region and the second region.

  Further, according to the seventh embodiment of the present invention, in the semiconductor device, the thin film 14 as the third thin film has a thickness formed in the first region smaller than the thickness formed in the second region. Thus, the two-dimensional electron gas concentration in the second region can be made lower than the two-dimensional electron gas concentration in the first region, and the current collapse can be reduced and the breakdown voltage can be maintained.

  Further, according to the seventh embodiment of the present invention, in the semiconductor device, the thin film 14 as the third thin film is a GaN film, so that if the GaN film thickness is increased, the two-dimensional electrons in the corresponding region are increased. The gas concentration is reduced, and the two-dimensional electron gas concentration can be adjusted. Therefore, the current collapse can be reduced and the breakdown voltage can be maintained by adjusting the film thickness for each of the first region and the second region.

  Although embodiments of the present invention have been disclosed and described in detail, the above description exemplifies aspects to which the present invention can be applied, and the present invention is not limited thereto. In other words, various modifications and variations to the described aspects can be considered without departing from the scope of the present invention.

  The present invention is suitable for application to, for example, a HEMT using a nitride semiconductor.

  1 substrate, 2 channel layer, 3 electron supply layer, 4a source electrode, 4b drain electrode, 5 gate electrode, 5eg gate electrode end, 6, 8, 14, 15, 16 thin film, 7 high concentration impurity region, 9a, 9b, 9c, 9c2, 9c3, 9d, 9e, 9f, 9g, 9h, 9i, 9j, 9k, 9m, 9n, 9p, 9q, 9r resist pattern, 10, 10b ion, 11, 11b gate electrode formation region, 13 element isolation region.

Claims (11)

A heterojunction nitride semiconductor device,
A channel layer made of a nitride semiconductor formed on a substrate;
An electron supply layer made of a nitride semiconductor having a larger band gap than the channel layer formed on the channel layer;
A gate electrode selectively formed on the electron supply layer;
On the electron supply layer, source and drain electrodes formed with the gate electrode interposed therebetween, and
A thin film which is formed on the electron supply layer between the source electrode and the drain electrode and which acts on the channel layer and the electron supply layer interface and which acts on a two-dimensional electron gas concentration;
With
The thin film is a thin film having a smaller band gap energy than the electron supply layer,
The thin film has a film thickness formed in a first region excluding the vicinity of the drain electrode side end of the gate electrode on the drain electrode side of the gate electrode, and a thickness of the gate electrode near the drain electrode side end. The film thickness formed in the two regions is different .
Semiconductor device. A heterojunction nitride semiconductor device,
A channel layer made of a nitride semiconductor formed on a substrate;
An electron supply layer made of a nitride semiconductor having a larger band gap than the channel layer formed on the channel layer;
A gate electrode selectively formed on the electron supply layer;
On the electron supply layer, source and drain electrodes formed with the gate electrode interposed therebetween, and
A thin film which is formed on the electron supply layer between the source electrode and the drain electrode and which acts on the channel layer and the electron supply layer interface and which acts on a two-dimensional electron gas concentration;
With
The thin film has a film thickness formed in a first region excluding the vicinity of the drain electrode side end of the gate electrode on the drain electrode side of the gate electrode, and a thickness of the gate electrode near the drain electrode side end. Unlike the film thickness formed in the two regions,
The thin film has a smaller film thickness formed in the first region than the film thickness formed in the second region .
Semi conductor device. A heterojunction nitride semiconductor device,
A channel layer made of a nitride semiconductor formed on a substrate;
An electron supply layer made of a nitride semiconductor having a larger band gap than the channel layer formed on the channel layer;
A gate electrode selectively formed on the electron supply layer;
On the electron supply layer, source and drain electrodes formed with the gate electrode interposed therebetween, and
A thin film which is formed on the electron supply layer between the source electrode and the drain electrode and which acts on the channel layer and the electron supply layer interface and which acts on a two-dimensional electron gas concentration;
With
The thin film has a film thickness formed in a first region excluding the vicinity of the drain electrode side end of the gate electrode on the drain electrode side of the gate electrode, and a thickness of the gate electrode near the drain electrode side end. Unlike the film thickness formed in the two regions,
The thin film is a GaN film .
Semi conductor device. The third thin film acts on the two-dimensional electron gas concentration formed at the interface between the channel layer and the electron supply layer respectively corresponding to the first region and the second region, and the concentration corresponding to the first region. Lowering the concentration corresponding to the second region than
The semiconductor device according to any one of claims 1 to 3. The channel layer and the electron supply layer include at least two layers of Al _x In _y Ga _{1 -xy} N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1, x and y are 1 at the same time. (Not take) of heterojunction field effect transistor ,
The semiconductor device according to claim 1 . Impurity regions formed in the channel layer and the electron supply layer below the source and drain electrodes ,
The semiconductor device according to any one of claims 1-5. The second region is within a range of at least half of the distance from the gate electrode to the drain electrode ;
The semiconductor device according to any one of claims 1-6. The electron supply layer has a surface on which at least one of the first surface treatment is performed on the first region and the second surface treatment is performed on the second region ,
The semiconductor device according to any one of claims 1-7. The first surface treatment is treatment with at least one plasma of argon and silicon,
The second surface treatment is treatment with at least one plasma of nitrogen, fluorine, chlorine, ammonia, oxygen ,
The semiconductor device according to claim 8 . The first surface treatment is a treatment for implanting at least one ion of Si, C, O, Ge, Sn, and Pb .
The semiconductor device according to claim 8 . The first surface treatment is a treatment with a solution containing silicon ions,
The second surface treatment is a treatment with a solution containing at least one of chlorine ions, hydroxide ions, fluorine ions, and ammonium ions .
The semiconductor device according to claim 8 .

Images