JP5126733B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to an electronic device using a nitride semiconductor material, and more particularly to a field effect transistor having a heterojunction structure of an enhancement type barrier layer and a channel layer and a method for manufacturing the same.

  GaN, which is a nitride semiconductor material having a large band gap, has various characteristics such as a high breakdown voltage and a high saturation drift speed. Therefore, if a GaN material is used, the resistance can be reduced without sacrificing the breakdown voltage characteristics as compared with a silicon-based electronic device. In addition, since it is chemically stable and stable at a high temperature, it can be used as a material for an electronic device that requires high output.

  GaN used for electronic devices is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation. Therefore, if a heterojunction such as an AlGaN / GaN junction is formed in parallel to the c-plane, a space fixed charge can be generated at the heterointerface due to the piezoelectric effect. By utilizing this, a two-dimensional electron gas can be formed at the heterointerface. For this reason, in a transistor or the like, an AlGaN / GaN heterojunction or an InAlN / GaN heterojunction formed in parallel with the c-plane is used to form a channel portion where carriers travel.

Currently, a transistor using a nitride semiconductor mainly produced is an AlGaN / GaN heterojunction field effect transistor. This transistor is manufactured as follows. As a layer structure, about 2 to 3 μm of non-doped GaN is grown on a substrate, and an AlGaN barrier layer is grown thereon to a thickness of about 20 to 40 nm.
The AlGaN barrier layer is n-type doped to reduce ohmic resistance. A metal such as Ti / Al / Au is used for the source electrode and the drain electrode. A metal such as platinum or nickel is used for the gate electrode. The structure in which the gate electrode is formed directly on the AlGaN barrier layer is called a MES structure (MEtal Semiconductor structure). On the other hand, a structure in which a dielectric such as a silicon nitride film or a silicon oxide film is sandwiched between the AlGaN barrier layer and the gate electrode is called a MIS structure (Metal Insulator Semiconductor structure).

  In such a structure, when the gate voltage is zero, electrons exist in the channel immediately below the gate portion, and a current flows. For this reason, the threshold voltage is about −3 to −5 V, which is normally on (depletion type) operating characteristics. Therefore, the application range is limited when used for power conversion of an inverter or the like. There are also disadvantages such as a complicated gate drive circuit.

  As a method for achieving normally-off (enhancement type), first, there is a method using a recess gate (see Non-Patent Documents 1, 2, and 5). In this method, a recess structure is used in which the AlGaN barrier layer just below the gate portion is thinned. If the AlGaN barrier layer is made thin, it is possible to almost exhaust the electrons in the channel directly under the gate portion. The threshold voltage is mainly determined from the relationship between the thickness of the AlGaN barrier layer in the gate portion, the work function of the gate electrode, and the Fermi level of electrons in the channel.

  Since the Fermi level of the gate electrode determined by the work function of the gate electrode material is within the band gap forbidden band of the barrier layer, if the barrier layer is thinned, the Fermi level of electrons in the channel becomes the Fermi level of the gate electrode. Get closer. Thereby, the threshold voltage can be changed to about 0V. However, the threshold voltage is unlikely to be completely positive. Alternatively, it is difficult to accurately control the thickness of the AlGaN barrier layer, and it is difficult to control the threshold voltage.

  The second method is a method using a halogen such as fluorine (see Non-Patent Document 4). In this method, the surface of the AlGaN barrier layer in the gate portion is surface-treated with fluorine plasma or the like to deplete electrons in the channel. This utilizes the large electronegativity of fluorine. However, fluorine has the disadvantage that it is generally not stable. It is also difficult to control the threshold voltage.

The third method is a method using a p-type GaN layer for the gate part (see Non-Patent Document 3). In this method, a p-type GaN layer is grown on an AlGaN barrier layer, leaving only the p-type GaN layer in the gate portion at the time of device fabrication, and removing the p-type GaN layer, so that electrons in the channel only in the gate portion are removed. It is a depleted structure. Thereby, normally-off characteristics are obtained.
However, in order to make the threshold voltage positive, the AlGaN barrier layer must be thinned. As a result, the influence of the electron level on the surface of the barrier layer is increased in portions other than the gate portion, so that there is a problem such as current collapse. is there. In addition, if the AlGaN barrier layer is 10 nm or less, the sheet resistance of the portion excluding the p-type GaN layer increases, so the AlGaN barrier layer must have a certain thickness, and as a result, it is difficult to control the threshold voltage. In addition, since the distance between the gate portion and the channel is large, there is a problem that the gain is lowered. Furthermore, since the etching selectivity between the AlGaN barrier layer and the p-type GaN layer is small, there is a problem that the processing accuracy of the semiconductor element is deteriorated.
T. Kawasaki, K. Nakata, and S. Yaegassi, Normally-off AlGaN / GaN HEMT with Recessed Gate for High Power Applications, Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, I-1-3, Kobe, 2005, pp.206-207. Inada Masaki, Yagi Shuichi, Yamamoto Yuki, Park Crown Tin, Yano Yoshiki, Shimizu Mitsuru, Okumura Moto, Arai Kazuo, Normally-off AlGaN / GaN HEMT, 66th Japan Society of Applied Physics, Lecture 2005, Tokushima University 8p-W-3. Tsuruguchi Tsuoguchi, Hirose Takatoshi, Iwatani Motoaki, Kamiyama Satoshi, Amano Hiroshi, Akazaki Isamu, normally-off type AlGaN / GaN HFE T using p-type GaN gate, 66th Japan Society of Applied Physics Academic Lecture, Autumn 2005 Tokushima University, 8p-W-5. Hiroaki Mizuno, Yutaka Ohno, Shigeru Kishimoto, Koichi Maezawa, Takashi Mizutani, Normally-off type AlGaN / GaN HEMT by fluorine plasma treatment, 53rd Joint Physics Conference on Applied Physics, Spring 2006, Musashi Institute of Technology, 24a-ZE -17. W. Saito, Y. Takada, M. Kuraguchi K. Tsuda, and I. Omura, Recessed-Gate Structure Approach Toward Normally Off High-Voltage AlGaN / GaN HEMT for Power Electronics Applications, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 2, FEBRUARY 2006.

  An object of the present invention is to solve the above-mentioned problems, and to control a threshold voltage and to provide a field effect transistor having a heterojunction made of an enhancement type nitride semiconductor having a normally-off characteristic and a method for manufacturing the same I will provide a.

  In view of the above-mentioned problems, the inventors of the present invention have made extensive studies on a field effect transistor having a conventional heterojunction structure, and as a result, the p-type InGaN layer has a layer structure in which a barrier layer in a gate region is stacked. It has been found that the voltage can be controlled and an element capable of normally-off operation is obtained.

The present invention
1. In a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, the p-type InGaN layer has a structure in which the p-type InGaN layer is stacked on the barrier layer of the gate region, and has a heterojunction structure A field effect transistor is provided.
The present invention also provides:
2. In a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, the gate region of the barrier layer has a recess structure, and a p-type InGaN layer is stacked on the barrier layer of the recess structure portion. A field effect transistor having a heterojunction structure having the above structure can be obtained.
3. In the field effect transistor having the heterojunction structure, the barrier layer / channel layer structure may be a heterostructure such as AlGaN / GaN, AlN / GaN, InAlN / GaN, or AlGaN / InGaN.
4). In the field effect transistor having the heterojunction structure, an MIS structure can be formed by stacking an insulating layer directly under the gate electrode.
5. In the field effect transistor having the heterojunction structure, a termination film (passivation film) can be formed on the barrier layer excluding the source electrode, the drain electrode, and the p-type InGaN layer in the gate region, thereby preventing gate leakage. .
Furthermore, the present invention provides
6). When manufacturing a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, a non- doped barrier layer is stacked on the channel layer, and then a p-type InGaN layer is stacked on the barrier layer. By removing the p-type InGaN layer other than the gate region, a structure in which the p-type InGaN layer is stacked on the barrier layer in the gate region can be formed.
In addition, the present invention
7. When manufacturing a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, after laminating the non-doped barrier layer on the channel layer, the gate layer barrier layer is thinned by etching to make a recess. It is also possible to form a structure and stack a p-type InGaN layer on the barrier layer in the recess structure portion.

  In the field effect transistor having a conventional heterojunction structure, the present invention has a layer structure in which a p-type InGaN layer is stacked on a barrier layer in a gate region, so that a threshold voltage can be controlled and a normally-off operation is performed. Has the excellent effect of becoming possible.

  The nitride semiconductor material that can be used in the present invention is a semiconductor containing nitrogen composed of a group III element and a group V element. The crystal structure is a wurtzite crystal belonging to the hexagonal system capable of high-quality crystal growth, and has polarization in the c-axis direction of the crystal orientation.

A crystal made of two elements such as GaN is suitable for the portion where the two-dimensional electron gas travels in the channel portion. This is because a mixed crystal of three elements, such as AlGaN and InGaN, and a mixed crystal of four elements have a large alloy scattering resulting from a non-uniform composition. However, since the effective mass of electrons can be reduced for In, in the case of InGaN, improvement in mobility can be expected. In this case, since an InGaN material having a large In composition has a small band gap and a breakdown voltage that is significantly inferior to that of GaN, an InGaN material having a small In composition is preferably used.
The heterojunction structure to which the structure of the present invention can be applied is a heterostructure such as GaN / AlGaN, GaN / AlN, GaN / InAlN, InGaN / AlGaN in the order of channel layer / barrier layer.

  The features of the present invention will be specifically described below with reference to the drawings. In addition, the following description is for making an understanding of this invention easy, and is not restrict | limited to this. That is, modifications, embodiments, and other examples based on the technical idea of the present invention are included in the present invention.

Example 1
FIG. 1 shows an AlGaN / GaN heterojunction field effect transistor. As the crystal substrate 1, a GaN substrate was grown by MOCVD or the like. In addition, a sapphire substrate, a SiC substrate, a silicon substrate, or the like can be used as the crystal substrate. Next, after a structure for improving crystallinity such as the low temperature growth GaN buffer layer 2 was formed from the substrate side, the high resistance GaN layer 3 was grown.
Thereafter, the AlGaN barrier layer 4 was grown. At this time, a positive fixed charge is generated at the heterojunction portion of the high-resistance GaN layer 3 and the AlGaN barrier layer 4 due to the piezo effect depending on the aluminum composition of the AlGaN barrier layer 4 to form an n-type channel. Thereafter, the p-type InGaN layer 5 was grown.

  For doping, p-type dopants such as magnesium and zinc were used so that the electrons in the channel could be depleted. At this time, since it is sufficient if there is a level for trapping electrons, a dopant such as iron is also possible. In addition, the p-type dopant such as magnesium may cause a diffusion problem. When the p-type InGaN layer is doped with magnesium or the like, the acceptor concentration can be made higher than that of GaN.

As the thickness of the AlGaN barrier layer 4 is thinner, the p-type InGaN layer 5 increases the resistance of the channel. When the AlGaN barrier layer 4 was undoped and made 15 nm thick, and the p-type InGaN layer 5 was made 10 nm thick with a hole concentration of about 5 × 10 ¹⁸ cm ⁻³ , the channel exhibited a sheet resistance of several tens of thousands Ω or more. The hole concentration of the p-type InGaN layer 5 is a value estimated with reference to the doping conditions for the p-type GaN layer because it is difficult to directly measure.

Next, device fabrication after crystal growth of the p-type InGaN layer will be described. First, after masking only the gate region with a photoresist, the p-type InGaN layer 5 other than the gate region was removed by dry etching using argon plasma, chlorine plasma, or the like. Since the InGaN layer has an etching rate larger than that of the GaN layer or AlGaN layer, it can be removed almost selectively, which is a great advantage in terms of process.
Here, the etching rate was measured by dry etching with argon plasma using an electron cyclotron resonance (ECR) method. When the extraction voltage is 200 V, the RF power of 2.45 GHz is 200 W, and the argon gas pressure is about 1 × 10 ⁻² Pa, the GaN film has an etching rate of 300 nm / hour. It was about twice.

The advantage of first etching the p-type InGaN layer 5 is that it can be confirmed that the resistance actually decreases while using a non-contact sheet resistance measuring device or the like. When the sheet resistance is measured while etching is performed by dry etching using argon plasma under the above dry etching conditions, the resistance which has been several tens of thousands of ohms at the beginning is reduced to about 1000 Ω in 30 seconds etching and 800 Ω in 1 minute etching. In addition, the etching did not change from 800Ω in the etching for 2 minutes.
By this method, it was found that the InGaN layer can be selectively etched using the structure of the present invention, and the process can be performed with good reproducibility.

  Next, a process of electrically insulating each element by mesa formation will be described. Using a photoresist, a rectangular mesa forming resist pattern of 20 μm in the direction in which the source electrode 10, the gate electrode 11, and the drain electrode 12 are arranged and 50 μm in the gate width direction was formed. However, the width and length of the mesa forming pattern can be changed as necessary. Here, the width of the gate electrode 11 and the width of the mesa are the same. Note that an exposure method using a commonly used stepper or the like may be used for forming a photoresist pattern.

  Thereafter, using the photoresist for mesa formation as a mask, the grown substrate was processed into a mesa pattern by dry etching. The etching rate varies depending on the crystal quality of the epitaxial film, the pressure of chlorine plasma, the acceleration energy (plasma extraction voltage), etc., but is set to 200 to 300 nm per hour. Etching was performed to about 100 nm to remove the AlGaN layer and the like other than the mesa.

By forming the mesa, the elements on the same substrate are separated from each other, so that no current flows between the elements. As the dry etching, chlorine plasma etching using the electron cyclotron resonance (ECR) method is also preferable. Dry etching has a direction of etching compared to the wet etching method, and the etching rate is easily controlled.
The element isolation can be performed not only by dry etching using a chlorine-based gas but also by ion implantation. By implanting nitrogen ions or the like at high speed, element isolation can be performed while providing electrical insulation.

After the mesa etching, an insulating film was formed in a portion other than the mesa. As the insulating film, a silicon oxide film, a silicon nitride film, or the like can be used. After an insulating film was formed on the entire wafer surface with a thickness of about 100 nm using plasma CVD or the like, portions other than the mesa were covered with photoresist, and then only the mesa was removed by etching.
When the gate electrode 11 is in contact with the AlGaN / GaN channel structure on the side surface of the mesa at the portion where the gate electrode 11 is located at the edge of the mesa, the gate leakage current increases, so that the mesa side surface is also covered with the insulating film.

  Thereafter, the source electrode 10 and the drain electrode 12 were formed. As the electrode metal of the source electrode 10 and the drain electrode 12, a structure of Ti / Al / Ni / Au (30/220/40/50 nm) was used from the substrate surface side. A high vacuum electron beam evaporation method was used for electrode metal deposition. After the electron beam evaporation, the metal other than the source and drain portions was removed by a lift-off method. Acetone may be used as the lift-off solution. Thereafter, annealing was performed for alloying the electrode metal and the surface layer. Annealing was performed at 800 ° C. for 30 seconds using a high-speed lamp annealing method (RTA).

  Thereafter, the gate electrode 11 was formed. Photolithography is used for patterning the gate. However, when the gate length is short and a fine pattern is used, electron beam lithography can be used. For example, when the gate length is 200 nm or less, an electron beam lithography method is used. As the gate electrode metal, Ni / Au (50/200 nm) was used from the substrate surface side. High vacuum electron beam evaporation was also used to form the gate metal.

  Although not shown in FIG. 1, the surface of the AlGaN barrier layer 4 can be covered with a silicon nitride film or the like as necessary. This is because it is effective to suppress current collapse, which is a phenomenon in which electrons are trapped in the surface level of the AlGaN barrier layer 4 between the drain and the gate and the drain current is reduced. Further, in order to improve the breakdown voltage, the surface can be covered with a silicon oxide film as necessary.

  FIG. 2 shows the operating characteristics of the transistor of Example 1. This is the gate voltage dependence of the drain current when the drain voltage is kept at 2V. The gate length of the element is 2 μm, the source-drain distance is 14 μm, the source-gate distance is 2 μm, and the gate width is 50 μm. This shows that the threshold voltage is about +0.8 V, and normally-off is achieved. Since the p-type InGaN layer has a small band gap, it is considered that the effect of depleting electrons in the channel is large.

In addition, the sheet resistances of the case where an InGaN layer having the same thickness as that of a GaN layer having a thickness of 5 nm was grown on an AlGaN / GaN heterostructure having an AlGaN barrier layer having a thickness of about 20 nm were compared. As a result, it was 550Ω for the GaN layer and 800Ω for the InGaN layer.
As a result, the growth of the InGaN layer on the AlGaN barrier layer as in the present invention is larger than the case where the GaN layer is grown on the AlGaN barrier layer. It is considered that charges are generated by the piezo effect and electrons in the channel are more depleted.
From the above, it was found that the threshold voltage can be increased and a completely normally-off operation can be obtained as compared with the case where the p-type GaN layer is used.

  The element of Example 1 was an element manufactured for investigating that the threshold voltage was positive, and used an MES structure for the gate portion. Further, no passivation film is applied to the element surface. For this reason, when the gate voltage is increased, the gate leakage current increases, so the amount of drain current is small. However, if the MIS structure is used, gate leakage can be prevented and a large gate voltage can be applied, so that the drain current can be increased.

(Example 2)
FIG. 3 shows an embodiment in which the gate region has a recess structure. In this element, since the AlGaN barrier layer 4 between the gate and the drain is thick, the influence of the collapse due to the surface level on the AlGaN barrier layer 4 is small.

As a method for manufacturing this element, the p-type InGaN layer 5 was selectively grown after making the AlGaN barrier layer 4 in the gate portion into a recess structure by etching. Since the p-type InGaN layer 5 is grown only in the gate region, there is an advantage that diffusion of p-type doping is difficult to occur outside the gate region. Thereafter, formation of a mesa structure, formation of an insulating film, formation of a surface protective layer using a source electrode 10, a drain electrode 12, and a silicon nitride film, and formation of a gate electrode 11 were performed in substantially the same manner as in Example 1. It was. It is also effective to use a MIS structure for the gate region.
There is also a method of selectively growing a thick AlGaN barrier layer 4 between the drain and the gate. In this case, the InGaN layer in the gate portion is covered with a silicon nitride film, a silicon oxide film, or the like and selectively grown.

  Since the lateral element can increase the breakdown voltage, for example, it can be integrated with other electronic components, and the AC-DC conversion unit of the household DC power source can be downsized. Further, since it can operate at high speed and is effective in energy saving, it is useful for inverters, converters, etc. for household power supplies.

It is sectional drawing of the field effect transistor which has the layer structure where the p-type InGaN layer was laminated | stacked on the barrier layer of the gate area | region. 3 is an operation characteristic of the field effect transistor according to the first embodiment. It is sectional drawing of the field effect transistor which has the layer structure where the p-type InGaN layer which has a recess structure was laminated | stacked on the barrier layer of the gate area | region.

Explanation of symbols

1: substrate 2: buffer layer 3: carrier layer 4: barrier layer 5: p-type InGaN layer 10: source electrode 11: gate electrode 12: drain electrode

Claims (7)

In a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, the p-type InGaN layer has a structure in which the p-type InGaN layer is stacked on the barrier layer of the gate region, and has a heterojunction structure Field effect transistor. In a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, the gate region of the barrier layer has a recess structure, and a p-type InGaN layer is stacked on the barrier layer of the recess structure portion. Field effect transistor having a heterojunction structure characterized by having 3. The heterojunction structure according to claim 1, wherein the heterojunction structure of the barrier layer / channel layer includes any one of AlGaN / GaN, AlN / GaN, InAlN / GaN, and AlGaN / InGaN. A field effect transistor. The field effect transistor having a heterojunction structure according to any one of claims 1 to 3, wherein an insulating layer is laminated directly under the gate electrode. 5. The field effect transistor having a heterojunction structure according to claim 1, further comprising a termination film on the barrier layer excluding the p-type InGaN layer in the source electrode, the drain electrode, and the gate region. In a method of manufacturing a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, a non- doped barrier layer is stacked on the channel layer, a p-type InGaN layer is stacked on the barrier layer, and a gate A method of manufacturing a field effect transistor having a telojunction structure, wherein a p-type InGaN layer other than a region is removed to form a structure in which a p-type InGaN layer is stacked on a barrier layer in a gate region. In a method of manufacturing a field effect transistor having a heterojunction structure of a non-doped barrier layer and a channel layer made of a nitride semiconductor, a non- doped barrier layer is stacked on the channel layer, and then a recess structure is formed by etching the barrier layer in the gate region. A method of manufacturing a field effect transistor having a heterojunction structure, characterized in that a p-type InGaN layer is stacked on a barrier layer in a recess structure portion, and a structure in which the p-type InGaN layer is stacked on a barrier layer in a gate region is formed .

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