JPH11261053A - High electron mobility transistor - Google Patents

High electron mobility transistor

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Publication number
JPH11261053A
JPH11261053A JP5707098A JP5707098A JPH11261053A JP H11261053 A JPH11261053 A JP H11261053A JP 5707098 A JP5707098 A JP 5707098A JP 5707098 A JP5707098 A JP 5707098A JP H11261053 A JPH11261053 A JP H11261053A
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layer
type
gan
semiconductor layer
type semiconductor
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Kiyoteru Yoshida
清輝 吉田
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Furukawa Electric Co Ltd:The
古河電気工業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Abstract

PROBLEM TO BE SOLVED: To provide a high electron mobility transistor(HEMT) of GaN compound semiconductor where a high voltage can be applied.
SOLUTION: A laminated structure A is composed of an I-type semiconductor layer 3 and an N-type semiconductor layer 4 laminated in this sequence on a semi-insulating substrate 1, wherein the semiconductor layers are all formed of GaN compound semiconductor. A gate electrode G is provided in the N-type semiconductor layer 4 through the intermediary of a P-type semiconductor layer 5 of GaN compound semiconductor, a source electrode S and a drain electrode D are provided direct onto the N-type semiconductor layer 4, and the P-type semiconductor layer 5 is a single-layer structure of P-type GaN layer or P-type InGaN layer or a two-layered structure composed of a P-type GaN layer and a P-type InGaN layer.
COPYRIGHT: (C)1999,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明のGaN系化合物半導体から成る高移動度トランジスタ(HEMT)に関し、 Composed of a GaN-based compound semiconductor of the present invention relates to relates to a high mobility transistor (HEMT),
更に詳しくは、高電圧印加の下で作動できる新規な構造のHEMTに関する。 More particularly, to HEMT having a novel structure that can operate under high voltage.

【0002】 [0002]

【従来の技術】HEMTは、例えば高出力マイクロ波素子の素材として期待されていて、現在ではGaAs系化合物半導体を用いて製造されているのが通例である。 BACKGROUND ART HEMT, for example, is expected as a material for high power microwave devices, it is customary and is manufactured using a GaAs-based compound semiconductor is now. 例えば、半絶縁性基板の上にi型GaAs層とn型GaA For example, i-type GaAs layer on a semi-insulating substrate and the n-type GaA
x As 1-x層を順次成膜し、そしてそのn型GaAl x l x As 1-x layer was deposited, and the n-type GaAl x
As 1-x層の上に、ソース電極とドレイン電極が装荷され、更に例えばp型GaAs層を介してゲート電極が装荷された構造のものが知られている。 Over the as 1-x layer, the source electrode and the drain electrode is loaded, it is known further example a structure in which a gate electrode is loaded through the p-type GaAs layer.

【0003】この構造のHEMTの場合、x=0.25 [0003] In the case of the HEMT of this structure, x = 0.25
のときのエネルギーバンド図をみると、n型GaAl Looking at the energy band diagram in the case of, n-type GaAl
0.25 As 0.75層とi型GaAs層のヘテロ接合界面におけるヘテロ障壁(ΔEc)は約0.26eVになっていて、熱平衡状態においては、当該接合界面に2次元電子ガス層が形成される状態になっている。 Hetero barrier at the heterojunction interface 0.25 As 0.75 layer and i-type GaAs layer (.DELTA.Ec) it becomes about 0.26 eV, in the thermal equilibrium state, a state where two-dimensional electron gas layer in the junction interface is formed ing. そして、ソース電極とドレイン電極の間に所定値の逆バイアス電圧を印加し、またソース電極とゲート電極の間に順バイアス電圧を印加することにより、前記n型GaAl x As 1 -x層からはその下に位置するi型GaAs層へ電子が供給され、供給された電子は前記接合界面で2次元電子ガス層を形成し、そのガス層内に閉じ込められた状態で電子はドレイン電極へと高速で流れてHEMT動作を実現する。 Then, by applying a reverse bias voltage of a predetermined value between the source electrode and the drain electrode, and by applying a forward bias voltage between the source electrode and the gate electrode, from the n-type GaAl x As 1 -x layer fast electrons are supplied to the i-type GaAs layer located thereunder, supplied electrons form a 2-dimensional electron gas layer at the bonding interface, electrons in a state of being confined to the gas layer to the drain electrode to achieve a HEMT operation flow in. その場合、ゲート電圧の直下における電界強度が強いほど、2次元電子がガス層への電子の閉じ込め効果は高まるので、高速動作は実現しやすくなる。 In that case, as the electric field intensity immediately below the gate voltage is high, since the two-dimensional electron increases the electron confinement effect to the gas layer, high-speed operation is easily achieved.

【0004】しかしながら、GaAs系HEMTの場合、ヘテロ接合界面における不連続バンドは0.26eV However, in the case of GaAs system HEMT, the discontinuous band at the heterojunction interface 0.26eV
程度(x=0.25のとき)であり、その絶縁破壊電界値は3×10 5 V/cm程度であるため、ゲート電極に高電圧を印加してその直下に高電界を形成することにより高速動作を実現するという点で難がある。 On the order (when x = 0.25), therefore the dielectric breakdown electric field value is about 3 × 10 5 V / cm, by forming a high electric field immediately below by applying a high voltage to the gate electrode a difficulty in terms of realizing a high-speed operation. このような問題に対処することを目的として、最近、GaN系化合物半導体を用いたHEMTの試作研究が行われている。 For the purpose of dealing with this problem, recently, trial studies HEMT using a GaN-based compound semiconductor has been performed.

【0005】これは、GaAl x1-xとGaNとのヘテロ接合界面におけるヘテロ障壁(ΔEc)は約0.67e [0005] This hetero barrier at the heterojunction interface between GaAl x N 1-x and GaN (.DELTA.Ec) about 0.67e
Vであり、GaAs系の場合に比べて約2.6倍と高い不連続バンドを有し、またその絶縁破壊電界値も2×10 A V, has about 2.6 times as high discontinuous band as compared with the case of GaAs system, also 2 × 10 also their breakdown field value
6 V/cmであり、GaAs系の場合に比べて1桁大きいので2次元電子ガス層内への電子の閉じ込め効果を高めることができ、理論的には、GaAs系に比べて電子濃度を10倍程度大きくすることができるからである。 A 6 V / cm, since an order of magnitude larger than that of GaAs systems could be enhanced electron confinement effect to a two-dimensional electron gas layer, in theory, the electron concentration in comparison with GaAs system 10 This is because it is possible to order multiple large.

【0006】このGaN系HEMTとしては、例えば次のようなものがMOCVD法を用いて製造されている。 [0006] As the GaN-based HEMT, for example, as follows is manufactured by MOCVD.
すなわちまず、半絶縁性のサファイア基板の上に、Al That is, first, on a semi-insulating sapphire substrate, Al
Nバッファ層が成膜される。 N buffer layer is deposited. ついで、Ga源としてトリメチルガリウム,N源としてアンモニアを用いて前記A Then, trimethyl gallium as a Ga source, the use of ammonia as an N source A
lNバッファ層の上にi型GaN層が成膜され、更にトリメチルアルミニウムをAl源として前記i型GaN層の上にn型AlGaN層が成膜される。 i-type GaN layer is deposited on top of lN buffer layer is n-type AlGaN layer is deposited over the further the i-type GaN layer trimethyl aluminum as an Al source. そして、このn Then, the n
型AlGaN層に対して常法のホトリソグラフィーとエッチングを行ったのち、所定の箇所にゲート電極,ソース電極,およびドレイン電極が装荷される。 After performing photolithography and etching of a conventional method for a type AlGaN layer, the gate electrode at a predetermined position, a source electrode and a drain electrode are loaded.

【0007】このGaN系HEMTの場合、i型GaN [0007] In the case of the GaN-based HEMT, i-type GaN
層とn型AlGaN層のヘテロ接合界面、具体的にはi Heterojunction interface layers and n-type AlGaN layer, in particular i
型GaN層の最上層に2次元電子ガス層が形成され、ここを電子が高速移動してHEMT動作を実現する。 -Type GaN layer two-dimensional electron gas layer in the uppermost layer is formed of, here electrons to achieve a HEMT operation moving at high speed. このとき、電子の高移動度を実現するためには、このi型G At this time, in order to realize a high mobility of the electrons, the i-type G
aN層には不純物や結晶欠陥が極力存在していないことが必要である。 The aN layer it is necessary to impurities and crystal defects are not as much as possible there.

【0008】 [0008]

【発明が解決しようとする課題】しかしながら、上記したGaN系HEMTの場合、GaAs系HEMTに比べれば高い電圧の印加は可能であるが、更なる高速動作が要求されている昨今の状況に対しては必ずしも充分な電子移動度を発揮するものとはいいがたい。 [SUMMARY OF THE INVENTION However, in the case of GaN-based HEMT as described above, but the application of higher voltage compared to GaAs based HEMT is possible, with respect to recent situation higher speed operation is required it can not be said that to exert necessarily sufficient electron mobility. 本発明は従来のGaN系HEMTにおける上記した問題を解決し、高耐圧性を備えている新規構造のGaN系HEMTの提供を目的とする。 The present invention solves the problems mentioned above in a conventional GaN-based HEMT, and an object thereof is to provide a GaN-based HEMT of the new structure and a high pressure resistance.

【0009】 [0009]

【課題を解決するための手段】上記した目的を達成するために、本発明においては、半絶縁性基板の上に、i型半導体層,n型半導体層をこの順序で積層して成る積層構造が形成され、前記各半導体層はいずれもGaN系化合物半導体から成り、前記n型半導体層の上にはGaN To achieve the above object SUMMARY OF THE INVENTION In the present invention, on a semi-insulating substrate, i-type semiconductor layer, formed by laminating the n-type semiconductor layer in this order laminated structure There is formed, the made from the semiconductor layer GaN-based compound are both semiconductor, GaN is formed on the n-type semiconductor layer
系化合物半導体から成るp型半導体層を介してゲート電極が装荷され、また前記n型半導体層の上には直接ソース電極とドレイン電極がそれぞれ装荷されていることを特徴とする高移動度トランジスタ、とくに、前記p型半導体層が、p型GaN層もしくはp型InGaN層の1 A gate electrode is loaded through the p-type semiconductor layer comprising a system compound semiconductor and high mobility transistor, wherein a direct source electrode and the drain electrode on the n-type semiconductor layer are loaded respectively, in particular, the p-type semiconductor layer, the first p-type GaN layer or p-type InGaN layer
層構造、またはp型GaN層にp型InGaN層を積層して成る2層構造である高移動度トランジスタが提供される。 Layer structure or high mobility transistors a p-type InGaN layer in the p-type GaN layer is a two-layer structure formed by laminating, are provided.

【0010】 [0010]

【発明の実施の形態】以下、本発明のHEMTにつき、 DETAILED DESCRIPTION OF THE INVENTION below, per HEMT of the present invention,
その基本構造を示す図1に基づいて詳細に説明する。 It will be described in detail with reference to FIG. 1 showing the basic structure. 本発明のHEMTは、半絶縁性基板1の上に、バッファ層2,i型半導体層3,n型半導体層4から成る積層構造Aが形成され、n型半導体層4の上には、p型半導体層6を介してゲート電極Gが装荷され、また、ソース電極S,ドレイン電極Dがそれぞれ装荷された構造になっている。 HEMT of the present invention, on a semi-insulating substrate 1, a laminated structure A consisting of buffer layer 2, i-type semiconductor layer 3, n-type semiconductor layer 4 is formed, on the n-type semiconductor layer 4, p type semiconductor layer 6 is the gate electrode G via the loading, also has a source electrode S, drain electrode D are loaded respectively structure.

【0011】このHEMTは、GaN系化合物半導体に対してMOCVD法やMOMBE法など公知のエピタキシャル成長法を適用することにより、半絶縁性基板1の上に所定組成の半導体層を成膜していくことによって製造される。 [0011] It this HEMT is that by applying the MOCVD method or MOMBE method such as a known epitaxial growth method with respect to GaN-based compound semiconductor, continue to deposit a semiconductor layer having a predetermined composition on a semi-insulating substrate 1 It is produced by. ここで、半絶縁性基板1としては、この上に成膜していく各半導体層との間で格子整合している材料から成ることが本来は好ましいが、GaN系に関してはそのような材料は存在しないので、従来から使用されている材料、例えばサファイア,Si単結晶などの半絶縁性材料の基板であればよい。 Here, the semi-insulating substrate 1, it is originally preferably made of a material which is lattice matched with the respective semiconductor layers will deposited thereon, such materials with respect to GaN-based because there, the material that is conventionally used, for example sapphire, may be a substrate of semi-insulating material such as Si single crystal. また、バッファ層2としては、GaN層が選択される。 As the buffer layer 2, GaN layer is selected.

【0012】i型半導体層3を構成するGaN系化合物半導体としては、例えば、i型GaN,i型InGaN [0012] As the GaN-based compound semiconductor constituting the i-type semiconductor layer 3, for example, i-type GaN, i-type InGaN
などをあげることができる。 And the like. とくに、i型GaNは好適である。 In particular, i-type GaN is suitable. また、バンドギャップエネルギーが上記した高純度なi型GaNのそれよりも小さいかまたは同等であれば、i型In x Ga 1-xy Al y N(ただし、0<x< Further, if the band gap energy highly pure i-type smaller or equal than that of GaN as described above, i-type In x Ga 1-xy Al y N ( However, 0 <x <
1,0<y<0.2)をi型半導体層3として用いることもできる。 1,0 <y <0.2) can also be used as the i-type semiconductor layer 3.

【0013】n型半導体層4を構成するGaN系化合物半導体としては、例えば、n型AlGaN,n型GaN [0013] As the GaN-based compound semiconductor constituting the n-type semiconductor layer 4, for example, n-type AlGaN, n-type GaN
などをあげることができる。 And the like. これらのうち、n型AlG Of these, n-type AlG
aNは好適である。 aN is preferred. また、バンドギャップエネルギーが上記n型AlGaNのそれよりも小さいかまたは同等であれば、n型In u Ga 1-uv Al v N(ただし、0<u Further, if the band gap energy less than or equal to than that of the n-type AlGaN, n-type In u Ga 1-uv Al v N ( However, 0 <u
<1,0<v<0.5)をn型半導体層として用いることもできる。 <Can also be used 1, 0 <v a <0.5) as the n-type semiconductor layer.

【0014】このn型半導体層4の成膜に用いるn型ドーパントとしては、例えば金属Si(MBE法で成膜する場合)やジシラン(MOCVD法で成膜する場合)をあげることができる。 [0014] As the n-type dopant used for forming the n-type semiconductor layer 4, it can be cited for example (case of forming by MBE) metallic Si and disilane (if deposited by MOCVD method). このn型半導体層4の上には直接ソース電極Sとドレイン電極Dを装荷することを考えると、両者間でオーミック接触を実現させるため、できるだけ低抵抗となるようにドーパント濃度を設定することが好ましい。 Considering that loading the source electrode S and the drain electrode D directly on top of the n-type semiconductor layer 4, in order to achieve the ohmic contact therebetween, to set the dopant concentration such that the lowest possible resistance preferable. 例えばn型ドーパントがSiである場合には、5×10 17 〜5×10 18 cm -3程度の濃度にする。 For example, when n-type dopant is Si is a concentration of about 5 × 10 17 ~5 × 10 18 cm -3.

【0015】次に、p型半導体層5を構成するGaN系化合物半導体としては、p型GaN,p型InGaNをあげることができる。 Next, as the GaN-based compound semiconductor constituting the p-type semiconductor layer 5, it may be mentioned p-type GaN, a p-type InGaN. このp型半導体層5は、p型Ga The p-type semiconductor layer 5, p-type Ga
N層,p型InGaN層のそれぞれ1層から成っていてもよいが、p型GaN層の上に更にp型InGaN層を積層して成る2層構造にすることが好適である。 N layer may consist single layer of p-type InGaN layer, but it is preferable to a two-layer structure formed by further laminating a p-type InGaN layer on the p-type GaN layer. このp This p
型半導体層5を成膜するときのp型ドーパントとしては、例えば金属Mg(MBE法で成膜する場合)やシクロペンタジエニルマグネシウム(MOCVD法で成膜する場合)などをあげることができる。 The p-type dopant when forming the type semiconductor layer 5, for example (if a film is formed by MBE method) metallic Mg and (if a film is formed by MOCVD method) cyclopentadienyl magnesium, and the like. このときのp型ドーパントの濃度は5×10 17 〜5×10 18 cm -3程度にする。 The concentration of p-type dopant in this case is set to about 5 × 10 17 ~5 × 10 18 cm -3.

【0016】最後に、ゲート電極Gを構成する材料としては例えばAu/Pt,Alなどをあげることができ、 [0016] Finally, may be mentioned for example Au / Pt, Al or the like as the material constituting the gate electrode G,
またゲート電極Gを構成する材料としては例えばAu, As the material constituting the gate electrode G such as Au,
Ti/Alなどをあげることができる。 Such as it is possible to increase the Ti / Al. この構造のHE HE of this structure
MTは、ゲート電極Gの下がpn接合構造になっている。 MT, under the gate electrode G is in pn junction structure. そして、ゲート電極Gから電圧印加を行うと、n型半導体層4とi型半導体層3のヘテロ接合界面、具体的には、i型半導体層3の最上層部に2次元電子ガス層3 When a voltage is applied from the gate electrode G, the heterojunction interface between the n-type semiconductor layer 4 and the i-type semiconductor layer 3, specifically, i-type two-dimensional electron gas layer 3 on the uppermost layer portion of the semiconductor layer 3
aが形成され、そこにn型半導体層4から供給された電子が閉じ込められ、高速でドレイン電極Dへ流れてHE a is formed, which in the n-type semiconductor layer 4 electrons confined supplied from, and fast flow to the drain electrode D HE
MT動作を実現する。 To realize the MT operations.

【0017】その場合、ゲート電極G直下のpn接合の働きにより少量のキャリア注入で電圧が制御され、かつ制御された電圧によってチャネル間を流れる電流を制御することが可能になるので、前記2次元電子ガス層3a [0017] In that case the voltage is controlled with a small amount of carrier injection by the action of the pn junction directly under the gate electrode G, and since the control voltage it is possible to control the current flowing between channels, the two-dimensional electron gas layer 3a
を高電圧で制御することが可能になり、2次元電子ガス層3aへの電子の閉じ込め効果も高くなって電子の高速移動が可能になる。 The it is possible to control a high voltage, even higher allowing faster transfer of electrons electron effect of confining two-dimensional electron gas layer 3a.

【0018】とくに、p型半導体層5が前記したp型G [0018] In particular, the p-type p-type semiconductor layer 5 is the G
aNとp型InGaNの2層構造になっている場合には、この積層構造が1種の量子井戸構造として機能し、 If you have a two-layer structure of aN and p-type InGaN, the laminated structure functions as a kind of quantum well structure,
その結果、量子効果によるトンネル電流が流れるようになり、ゲート電流は流れやすくなるので好適である。 As a result, to flow a tunnel current due to the quantum effect, the gate current is preferred since easily flow.

【0019】 [0019]

【実施例】図1で示した積層構造のHEMTをMOMB The HEMT of laminated structure shown in Embodiment] FIG 1 MOMB
E法により次のようにして製造した。 It was prepared as follows by the E method. まず、半絶縁性のSi単結晶基板1の上に、Ga源として金属Ga(5× First, on a semi-insulating single crystal Si substrate 1, a metal Ga (5 × as Ga source
10 10 -7 Torr),N源としてジメチルヒドラジン(5×1 -7 Torr), dimethylhydrazine as N source (5 × 1
-5 Torr)を用い、成長温度640℃でエピタキシャル成長を行い、厚み50ÅのGaNバッファ層2を成膜した。 0 -5 Torr) using, epitaxial growth was performed at a growth temperature of 640 ° C., thereby forming a GaN buffer layer 2 having a thickness of 50 Å.

【0020】ついで、N源をアンモニア(5×10 -5 To [0020] Then, N sources of ammonia (5 × 10 -5 To
rr)に切り換え、成長温度を850℃に上昇してエピタキシャル成長を行い、厚み5000Åのi型GaN層3 Switched rr), carried out rises and epitaxially growing the growth temperature to 850 ° C., the thickness 5000 Å i-type GaN layer 3
を成膜した。 The film was formed. なお、このときのキャリア濃度は5×10 The carrier concentration in this case is 5 × 10
16 cm -3以下となるように成膜条件を設定した。 16 cm -3 was set deposition conditions as to become less.

【0021】ついで、金属Al(2×10 -7 Torr)を供給し、またn型ドーパントとして金属Si(2×10 -9 [0021] Then, by supplying the metal Al (2 × 10 -7 Torr) , also metallic Si (2 × 10 -9 as n-type dopant
Torr)を供給し、成長温度850℃でエピタキシャル成長を継続して、厚みが500Åのn型AlGaN層4を成膜した。 Torr) to supply, to continue the epitaxial growth at a growth temperature of 850 ° C., the thickness was deposited an n-type AlGaN layer 4 of 500 Å. このとき、キャリア濃度は1×10 18 cm -3となるように成膜条件を設定した。 In this case, the carrier concentration was set deposition conditions such that the 1 × 10 18 cm -3. ついで、金属Siの供給を絶ち、p型ドーパントとして金属Mg(5×10 -9 Then, it cuts off the supply of metal Si, metal as a p-type dopant Mg (5 × 10 -9
Torr)を供給して成膜操作を続け、前記n型AlGaN Continue film formation operation by supplying Torr), the n-type AlGaN
層4の上に厚み500Åのp型GaN層6を成膜した。 It was formed a p-type GaN layer 6 having a thickness of 500Å on the layer 4.
このとき、キャリア濃度は1×10 18 cm -3となるように成膜条件を設定した。 In this case, the carrier concentration was set deposition conditions such that the 1 × 10 18 cm -3.

【0022】ついで、水素とアルゴンとメタンの混合ガスをプラズマ化したものをエッチャントにしてドライエッチングを行い、ゲート電極を装荷すべき箇所以外のp [0022] Then, dry etching is performed by an etchant of those plasma mixed gas of hydrogen and argon and methane, other than portions to be loaded gate electrode p
型GaN層をエッチング除去してn型InGaN層4を表出させた。 -Type GaN layer were removed by etching to expose the n-type InGaN layer 4. その後、全体の表面を被覆してSiO 2膜をプラズマCVD法で成膜し、ホトレジストでパターニングしたのちゲート電極を装荷すべき箇所を含む部分をマスキングし、ソース電極とドレイン電極を装荷すべき箇所は開口し、そこに表出したn型InGaN層4の上に、金属Alを蒸着することにより、ソース電極Sとドレイン電極Dを装荷した。 Locations Thereafter, the SiO 2 film deposited by plasma CVD to cover the entire surface, masking the portion including the portion to be loaded gate electrode After patterning with a photoresist, to be loaded with the source electrode and the drain electrode It is open, on the n-type InGaN layer 4 which is exposed to the outside there, by depositing metallic Al, loaded with the source electrode S and the drain electrode D.

【0023】最後、前記マスキングをエッチング除去し、その下のSiO 2膜を開口し、ソース電極Sとドレイン電極Gの箇所をSiO 2膜でマスキングしたのち、 [0023] Finally, after the masking is removed by etching, an opening of the SiO 2 film beneath it was masked portions of the source electrode S and the drain electrode G of SiO 2 film,
上記開口部にAuを蒸着してp型GaN層5の上にはゲート電極Gを装荷して図1で示したHEMTを製造した。 Were prepared HEMT shown in FIG. 1 by loading a gate electrode G is formed on the p-type GaN layer 5 by depositing Au on the opening. このHEMTは、ゲート電圧からの印加電圧を3V The HEMT is, the applied voltage from the gate voltage of 3V
でドレイン電流(Ids)が60mA,ドレイン電圧2V以上で飽和するHEMT特性が得られた。 In drain current (Ids) is 60 mA, HEMT characteristics saturated at the drain voltage of 2V or more was obtained. すなわち、この飽和特性はVdsを100Vまであげても一定値を保ち、 That is, the saturation characteristics keeps a constant value even by increasing the Vds to 100 V,
HEMTとしての機能を喪失することはなかった。 It did not lose the function of the HEMT.

【0024】室温下でのこのHEMT構造の移動度は、 The mobility of this HEMT structure under room temperature,
600cm 2 /V・secであり、77Kでの移動度は7500c 600cm is a 2 / V · sec, mobility in the 77K is 7500c
m 2 /V・secと良好な値を示した。 It showed good values and m 2 / V · sec.

【0025】 [0025]

【発明の効果】以上の説明で明らかなように、本発明のGaN系HEMTは、ゲート電極をVまで高めても故障を起こすことがなく、従来のGaN系HEMTに比べて高速動作をすることができる。 As apparent from the above description, according to the present invention, the GaN-based HEMT of the present invention, without causing failure even increase the gate electrode to V, to a high-speed operation as compared with the conventional GaN-based HEMT can. これは、ゲート電極とチャネル層との間をpn接合構造とし、i型半導体層とn This between the gate electrode and the channel layer and pn junction structure, i-type semiconductor layer and the n
型半導体層との接合界面に電子の閉じ込め効果が優れている2次元電子ガス層が形成されるようにしたことがもたらす効果である。 It is effective to bring the type semiconductor layer and the two-dimensional electron gas layer is an electron confinement effect is excellent in the bonding interface was to be formed.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明のHEMTの層構造を示す断面図である。 1 is a cross-sectional view showing a layer structure of the HEMT of the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 半絶縁性基板 2 バップ層(GaN層) 3 i型半導体層(i型GaN層) 3a 2次元電子ガス層 4 n型半導体層(n型InGaN層) 5 p型半導体層(p型GaN層) S ソース電極 G ゲート電極 D ドレイン電極 1 semi-insulating substrate 2 Bop layer (GaN layer) 3 i-type semiconductor layer (i-type GaN layer) 3a 2-dimensional electron gas layer 4 n-type semiconductor layer (n-type InGaN layer) 5 p-type semiconductor layer (p-type GaN layer ) S source electrode G gate electrode D drain electrode

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 半絶縁性基板の上に、i型半導体層,n 1. A on a semi-insulating substrate, i-type semiconductor layer, n
    型半導体層をこの順序で積層して成る積層構造が形成され、前記各半導体層はいずれもGaN系化合物半導体から成り、前記n型半導体層の上にはGaN系化合物半導体から成るp型半導体層を介してゲート電極が装荷され、また前記n型半導体層の上には直接ソース電極とドレイン電極がそれぞれ装荷されていることを特徴とする高移動度トランジスタ。 -Type semiconductor layer laminated structure formed by laminating in this order is formed, the respective semiconductor layers are both made of a GaN-based compound semiconductor, p-type semiconductor layer made of GaN-based compound semiconductor on the n-type semiconductor layer high mobility transistor having a gate electrode is loaded, also characterized in that the direct source electrode and the drain electrode on the n-type semiconductor layer is loaded through respective.
  2. 【請求項2】 前記p型半導体層が、p型GaN層もしくはp型InGaN層の1層構造、またはp型GaN層にp型InGaN層を積層して成る2層構造である請求項1の高移動度トランジスタ。 Wherein said p-type semiconductor layer, p-type single-layer structure of GaN layer or p-type InGaN layer or p-type GaN layer according to claim 1 which is a two-layer structure formed by laminating a p-type InGaN layer, high mobility transistor.
JP5707098A 1998-03-09 1998-03-09 High electron mobility transistor Pending JPH11261053A (en)

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