JPH11261053A - High electron mobility transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high electron mobility transistor(HEMT) of GaN compound semiconductor where a high voltage can be applied. SOLUTION: A laminated structure A is composed of an I-type semiconductor layer 3 and an N-type semiconductor layer 4 laminated in this sequence on a semi-insulating substrate 1, wherein the semiconductor layers are all formed of GaN compound semiconductor. A gate electrode G is provided in the N-type semiconductor layer 4 through the intermediary of a P-type semiconductor layer 5 of GaN compound semiconductor, a source electrode S and a drain electrode D are provided direct onto the N-type semiconductor layer 4, and the P-type semiconductor layer 5 is a single-layer structure of P-type GaN layer or P-type InGaN layer or a two-layered structure composed of a P-type GaN layer and a P-type InGaN layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high mobility transistor (HEMT) comprising a GaN-based compound semiconductor according to the present invention.
More specifically, the present invention relates to a HEMT having a novel structure capable of operating under high voltage application.

[0002]

2. Description of the Related Art HEMTs are expected to be used, for example, as materials for high-power microwave devices. At present, HEMTs are usually manufactured using GaAs-based compound semiconductors. For example, an i-type GaAs layer and an n-type GaAs are formed on a semi-insulating substrate.
l _x As _1-x layers are sequentially formed, and the n-type GaAl _x
There is known a structure in which a source electrode and a drain electrode are loaded on an As1 _-x layer, and a gate electrode is further loaded via, for example, a p-type GaAs layer.

In the case of a HEMT having this structure, x = 0.25
Looking at the energy band diagram at the time of, n-type GaAl
The hetero barrier (ΔEc) at the heterojunction interface between the _0.25 As _0.75 layer and the i-type GaAs layer is about _0.26 eV. In a thermal equilibrium state, a two-dimensional electron gas layer is formed at the junction interface. ing. Then, by applying a predetermined reverse bias voltage between the source electrode and the drain electrode and applying a forward bias voltage between the source electrode and the gate electrode, the n-type GaAl _x As _{1 -x} layer Electrons are supplied to an i-type GaAs layer located thereunder, and the supplied electrons form a two-dimensional electron gas layer at the junction interface. The electrons are conveyed at a high speed to the drain electrode while being confined in the gas layer. To realize the HEMT operation. In that case, as the electric field intensity immediately below the gate voltage is higher, the effect of confining the two-dimensional electrons in the gas layer is increased, so that high-speed operation is easily realized.

However, in the case of a GaAs HEMT, the discontinuous band at the heterojunction interface is 0.26 eV.
(When x = 0.25) and the dielectric breakdown electric field value is about 3 × 10 ⁵ V / cm. Therefore, by applying a high voltage to the gate electrode and forming a high electric field immediately below the gate electrode, There is a difficulty in realizing high-speed operation. For the purpose of addressing such a problem, recently, trial manufacture and research of HEMTs using GaN-based compound semiconductors have been conducted.

[0005] This is because the hetero barrier (ΔEc) at the heterojunction interface between GaAl _x N _1-x and GaN is about 0.67 e.
V, which has a discontinuous band that is about 2.6 times higher than that of the GaAs-based one.
⁶ V / cm, which is an order of magnitude larger than that of the GaAs system, so that the effect of confining electrons in the two-dimensional electron gas layer can be enhanced. This is because it can be approximately twice as large.

For example, the following GaN-based HEMTs are manufactured by using the MOCVD method.
That is, first, on a semi-insulating sapphire substrate, Al
An N buffer layer is formed. Next, the above-mentioned A was prepared using trimethylgallium as a Ga source and ammonia as an N source.
An i-type GaN layer is formed on the 1N buffer layer, and an n-type AlGaN layer is formed on the i-type GaN layer using trimethyl aluminum as an Al source. And this n
After performing conventional photolithography and etching on the type AlGaN layer, a gate electrode, a source electrode, and a drain electrode are loaded at predetermined locations.

In the case of this GaN-based HEMT, i-type GaN
Interface between the layer and the n-type AlGaN layer, specifically, i
A two-dimensional electron gas layer is formed on the uppermost layer of the type GaN layer, and electrons move at a high speed to realize a HEMT operation. At this time, in order to realize high electron mobility, the i-type G
It is necessary that impurities and crystal defects do not exist as much as possible in the aN layer.

[0008]

However, in the case of the GaN-based HEMT described above, a higher voltage can be applied than in the case of the GaAs-based HEMT. Does not necessarily exhibit sufficient electron mobility. An object of the present invention is to solve the above-described problems in the conventional GaN-based HEMT and to provide a GaN-based HEMT having a novel structure and high withstand voltage.

[0009]

In order to achieve the above object, according to the present invention, there is provided a laminated structure in which an i-type semiconductor layer and an n-type semiconductor layer are laminated in this order on a semi-insulating substrate. Is formed, each of the semiconductor layers is made of a GaN-based compound semiconductor, and GaN is formed on the n-type semiconductor layer.
A high mobility transistor, wherein a gate electrode is loaded via a p-type semiconductor layer made of a compound semiconductor, and a source electrode and a drain electrode are directly loaded on the n-type semiconductor layer, respectively. In particular, the p-type semiconductor layer is one of a p-type GaN layer and a p-type InGaN layer.
A high mobility transistor having a layer structure or a two-layer structure in which a p-type InGaN layer is stacked on a p-type GaN layer is provided.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a HEMT of the present invention will be described.
This will be described in detail with reference to FIG. In the HEMT of the present invention, a laminated structure A including a buffer layer 2, an i-type semiconductor layer 3, and an n-type semiconductor layer 4 is formed on a semi-insulating substrate 1, and a p-type The gate electrode G is loaded via the mold semiconductor layer 6, and the source electrode S and the drain electrode D are loaded respectively.

In this HEMT, a semiconductor layer having a predetermined composition is formed on a semi-insulating substrate 1 by applying a known epitaxial growth method such as a MOCVD method or a MOMBE method to a GaN-based compound semiconductor. Manufactured by Here, it is originally preferable that the semi-insulating substrate 1 be made of a material which is lattice-matched with each semiconductor layer to be formed thereon. Since it does not exist, a substrate of a conventionally used material, for example, a semi-insulating material such as sapphire or Si single crystal may be used. Further, a GaN layer is selected as the buffer layer 2.

As the GaN compound semiconductor constituting the i-type semiconductor layer 3, for example, i-type GaN, i-type InGaN
And so on. In particular, i-type GaN is suitable. If the band gap energy is smaller than or equal to that of the above-mentioned high-purity i-type GaN, i-type In _x Ga _{1 -xy} Al _y N (where 0 <x <
1,0 <y <0.2) can be used as the i-type semiconductor layer 3.

As the GaN-based compound semiconductor constituting the n-type semiconductor layer 4, for example, n-type AlGaN, n-type GaN
And so on. Of these, n-type AlG
aN is preferred. If the band gap energy is smaller than or equal to that of the n-type AlGaN, n-type In _u Ga _1-uv Al _v N (where 0 <u)
<1,0 <v <0.5) can also be used as the n-type semiconductor layer.

The n-type dopant used for forming the n-type semiconductor layer 4 includes, for example, metal Si (in the case of forming by MBE) and disilane (in the case of forming by MOCVD). Considering that the source electrode S and the drain electrode D are directly loaded on the n-type semiconductor layer 4, it is necessary to set the dopant concentration so that the resistance is as low as possible in order to realize ohmic contact between the two. preferable. For example, when the n-type dopant is Si, the concentration is set to about 5 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ .

Next, as the GaN-based compound semiconductor constituting the p-type semiconductor layer 5, p-type GaN and p-type InGaN can be mentioned. This p-type semiconductor layer 5 is made of p-type Ga
It may be composed of one layer each of an N layer and a p-type InGaN layer, but it is preferable to form a two-layer structure in which a p-type InGaN layer is further laminated on the p-type GaN layer. This p
Examples of the p-type dopant when forming the type semiconductor layer 5 include metal Mg (when forming by the MBE method) and cyclopentadienyl magnesium (when forming by the MOCVD method). At this time, the concentration of the p-type dopant is set to about 5 × 10 ^{17 to} 5 × 10 ¹⁸ cm ⁻³ .

Finally, examples of the material constituting the gate electrode G include Au / Pt, Al and the like.
Examples of the material forming the gate electrode G include Au,
Ti / Al and the like can be mentioned. HE of this structure
The MT has a pn junction structure below the gate electrode G. When a voltage is applied from the gate electrode G, the two-dimensional electron gas layer 3 is formed at the heterojunction interface between the n-type semiconductor layer 4 and the i-type semiconductor layer 3, specifically, at the uppermost layer of the i-type semiconductor layer 3.
a is formed, and the electrons supplied from the n-type semiconductor layer 4 are confined therein, flow to the drain electrode D at high speed, and HE
Implement MT operation.

In this case, the voltage is controlled by a small amount of carrier injection by the function of the pn junction immediately below the gate electrode G, and the current flowing between the channels can be controlled by the controlled voltage. Electron gas layer 3a
Can be controlled at a high voltage, the effect of confining the electrons in the two-dimensional electron gas layer 3a is enhanced, and the electrons can move at high speed.

In particular, the p-type semiconductor layer 5 is
In the case of a two-layer structure of aN and p-type InGaN, this stacked structure functions as one kind of quantum well structure,
As a result, a tunnel current due to the quantum effect flows and a gate current easily flows, which is preferable.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The HEMT having the laminated structure shown in FIG.
It was produced as follows by Method E. First, semi-insulating
On a Si single crystal substrate 1, metal Ga (5 ×
10 ^-7Torr), dimethylhydrazine (5 × 1) as N source
0^-FiveTorr) and epitaxial growth at 640 ° C
After growing, a GaN buffer layer 2 having a thickness of 50 ° is formed.
Was.

Then, the N source was changed to ammonia (5 × 10 ⁻⁵ To
rr), the growth temperature is raised to 850 ° C. and epitaxial growth is performed, and the 5000-mm thick i-type GaN layer 3 is formed.
Was formed. The carrier concentration at this time is 5 × 10
^The film forming conditions were set so as to be ¹⁶ cm ⁻³ or less.

Next, metal Al (2 × 10 ⁻⁷ Torr) is supplied, and metal Si (2 × 10 ⁻⁹ Torr) is used as an n-type dopant.
(Torr), epitaxial growth was continued at a growth temperature of 850 ° C., and an n-type AlGaN layer 4 having a thickness of 500 ° was formed. At this time, the film forming conditions were set so that the carrier concentration was 1 × 10 ¹⁸ cm ⁻³ . Then, the supply of metal Si was stopped, and metal Mg (5 × 10 ⁻⁹⁾ was used as a p-type dopant.
Torr) to continue the film forming operation, and the n-type AlGaN
A p-type GaN layer 6 having a thickness of 500 ° was formed on the layer 4.
At this time, the film forming conditions were set so that the carrier concentration was 1 × 10 ¹⁸ cm ⁻³ .

Then, dry etching is performed by using a mixture of hydrogen, argon, and methane, which has been turned into plasma, as an etchant to perform p etching on portions other than those where the gate electrode is to be loaded.
The n-type InGaN layer 4 was exposed by removing the n-type GaN layer by etching. After that, the entire surface is covered, a SiO ₂ film is formed by a plasma CVD method, and after patterning with a photoresist, a portion including a portion where a gate electrode is to be loaded is masked, and a portion where a source electrode and a drain electrode are to be loaded. Was opened, and the source electrode S and the drain electrode D were loaded on the exposed n-type InGaN layer 4 by depositing metal Al.

Finally, the masking is removed by etching, the underlying SiO ₂ film is opened, and the portions of the source electrode S and the drain electrode G are masked with the SiO ₂ film.
Au was vapor-deposited on the opening and a gate electrode G was loaded on the p-type GaN layer 5 to manufacture the HEMT shown in FIG. In this HEMT, the applied voltage from the gate voltage is 3 V
As a result, HEMT characteristics were obtained in which the drain current (Ids) was saturated at 60 mA and the drain voltage was 2 V or more. That is, this saturation characteristic maintains a constant value even when Vds is increased up to 100 V,
The function as HEMT was not lost.

The mobility of this HEMT structure at room temperature is:
600 cm ² / V · sec, mobility at 77K is 7500 c
It showed a good value of m ² / V · sec.

[0025]

As is apparent from the above description, the GaN-based HEMT of the present invention does not fail even if the gate electrode is raised to V, and operates at a higher speed than the conventional GaN-based HEMT. Can be. This is because a pn junction structure is formed between the gate electrode and the channel layer, and the i-type semiconductor layer
This is an effect brought about by forming a two-dimensional electron gas layer having an excellent electron confinement effect at the junction interface with the mold semiconductor layer.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a layer structure of a HEMT of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semi-insulating substrate 2 Vap layer (GaN layer) 3 i-type semiconductor layer (i-type GaN layer) 3a Two-dimensional electron gas layer 4 n-type semiconductor layer (n-type InGaN layer) 5 p-type semiconductor layer (p-type GaN layer) ) S source electrode G gate electrode D drain electrode

Claims (2)

[Claims] An i-type semiconductor layer is formed on a semi-insulating substrate.
A stacked structure is formed by stacking type semiconductor layers in this order. Each of the semiconductor layers is made of a GaN-based compound semiconductor, and a p-type semiconductor layer made of a GaN-based compound semiconductor is formed on the n-type semiconductor layer. A high-mobility transistor, wherein a gate electrode is loaded via the gate electrode, and a source electrode and a drain electrode are respectively loaded directly on the n-type semiconductor layer. 2. The p-type semiconductor layer according to claim 1, wherein the p-type semiconductor layer has a one-layer structure of a p-type GaN layer or a p-type InGaN layer, or a two-layer structure in which a p-type GaN layer is laminated on a p-type GaN layer. High mobility transistor.