JP4940557B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a field effect transistor using a nitride material and a manufacturing method thereof.

  Nitride semiconductors such as GaN, AlGaN, InGaN, and InAlGaN have high breakdown field strength, high thermal conductivity, and high electron saturation speed, and are promising as high-frequency power device materials.

  In particular, in a semiconductor device having an AlGaN / GaN heterojunction structure, a region in which electrons are accumulated at a high concentration, called a two-dimensional electron gas, is formed near the heterojunction interface between AlGaN and GaN.

In the AlGaN / GaN heterojunction structure, since there is a difference in spontaneous polarization between AlGaN and GaN and piezoelectric polarization due to tensile stress applied to AlGaN, it exceeds 1 × 10 ¹³ cm ⁻² near the AlGaN / GaN heterojunction interface. It is known that very high two-dimensional electron gas concentration regions can be created. The value of the two-dimensional electron gas concentration described above corresponds to an electron concentration of 3 to 5 times that of the AlGaAs / InGaAs system that is currently popular as a high-frequency transistor.

Further, the two-dimensional electron gas in the AlGaN / GaN heterojunction structure has a high electric field region of about 1 × 10 ⁵ V / cm and has an electron velocity more than twice that of the AlGaAs / InGaAs system.

  Because of these features, field effect transistors (FETs) using an AlGaN / GaN heterojunction structure are very promising as power devices because they can realize a large drain current. In this type of semiconductor device, it is essential to reduce parasitic resistance.

  For example, as a conventional FET technique for the purpose of reducing parasitic resistance, a low-resistance contact layer with a high n-type impurity concentration or a low Al concentration is provided between an electron supply layer and a source electrode and a drain electrode. There is an FET in which is inserted (for example, Patent Document 1).

FIG. 8 shows a conventional semiconductor device 90. The semiconductor device 90 has a low-temperature GaN buffer layer 92, an undoped GaN layer 93, an n-Al _x Ga _1-x N (0 ≦ x ≦ 1) electron supply layer 94 on the sapphire substrate 91, and an Al concentration from the electron supply layer 94. lower ^{_{n + -Al y Ga 1-y}} n (0 ≦ y ≦ 1, y ≦ x) are laminated contact layer 95 created sequentially, the two-dimensional electron gas layer 99 is formed in the electron supply layer 94 Has been.

The ^{_{n + -Al y Ga 1-y}} N contact layer 95 source electrode 96 and drain electrode 97 is formed on is formed, directly below the gate region ^{_{n + -Al y Ga 1-y}} N contact layer 95 is removed n -Al _x Ga _1-x N electron supply layer 94 is exposed, the gate electrode 98 is formed on the gate region.

In the semiconductor device ^{_{90, n + -Al y Ga 1}} -y N to the n-type impurity concentration of the contact layer 95 higher than the n-type impurity concentration of the _{n-Al x Ga 1-x} N electron supply layer 94, and n ⁺ is characterized by a -Al _y Ga _1-y n Al composition y of the contact layer 95 is smaller than the _{n-Al x Ga 1-x} n of the electron supply layer 94 Al composition x.

As a result, in the semiconductor device ^90, as compared with the case _{n + -Al y Ga 1-y} N contact layer 95 is not, because it can reduce the contact resistance between the source electrode 96 and drain electrode 97 and the semiconductor layer, a parasitic transistor The resistance can be reduced, and it can contribute to improvement of characteristics and reliability.
JP 2000-277724 A

  However, the above-described semiconductor device 90 has a problem that the parasitic resistance of the transistor is not sufficiently reduced. FIG. 9 shows a potential distribution with respect to electrons in the BB cross section in the semiconductor device 90.

In the semiconductor device 90, positive polarization occurs at the interface between the undoped GaN layer 93 and the n-Al _x Ga _1-x N electron supply layer 94 due to the difference in spontaneous polarization between AlGaN and GaN and the effect of piezoelectric polarization generated in the AlGaN layer. _charge, negative polarization charge is generated in the interface of the _{n-Al x Ga 1-x} n electron supply layer 94 and the ^{_{n + -Al y Ga 1-y}} n contact layer 95.

This is because, in the potential distribution shown in FIG. 9, the potential decreases at the interface between the undoped GaN layer 93 and the n-Al _x Ga _1-x N electron supply layer 94, and n-Al _x Ga _1-x N electron supply. at the interface layer 94 and ^{_{n + -Al y Ga 1-y}} n contact layer 95 corresponding to the potential is high.

In the nitride-based _{semiconductor, n-Al x Ga 1-} x N electron supply layer 94 and the ^{_{n + -Al y Ga 1-y}} N polarized charge generated at the interface of the contact layer 95 is 1 × ¹⁰ 13 ^{cm -2} or more And very large. _Therefore, so that _{the n-Al x Ga 1-x} N large potential barrier at the interface of the electron supply layer 94 and the ^{_{n + -Al y Ga 1-y}} N contact layer 95 is present.

Further, the n ⁺ -Al _y Ga _1-y N contact layer 95 has an n-Al _x Ga _1-x N electron supply layer 94 in the vicinity of the interface, depending on the impurity concentration and Al composition due to the potential barrier described above. A depletion layer region that is not generated occurs.

From the ^above, n ₊ -Al by providing _{y Ga 1-y} N contact layer 95, the source electrode 96 and drain electrode 97, positions the potential barrier on the way leading to the two-dimensional electron gas layer 99 to form a channel At the same time, a high resistance region called a depletion layer region is interposed. The above-described potential barrier and depletion layer increase the parasitic resistance of the transistor.

For ^these, n ₊ -Al when _{y Ga 1-y} N contact layer is not present, potential barrier _{^{n + -Al y Ga 1-y}} N contact layer between the source electrode 96 and the two-dimensional electron gas 99 Not as high as 95.

This is because the potential barrier at the contact interface between the n-Al _x Ga _1-x N electron supply layer 94 and the source electrode 96 and the drain electrode 97 made of a metal material does not depend on the generated polarization charge, and the material This is because it is a Schottky barrier determined by specific physical properties. Therefore, there is no depletion layer between the source electrode 96 and the two-dimensional electron gas 99.

  As described above, in the conventional semiconductor device 90, the contact resistance with the source electrode 96 and the drain electrode 97 is reduced by inserting it into the contact layer 95. A large potential barrier and a depletion layer generated at the interface increase the resistance, and the parasitic resistance of the transistor cannot be reduced sufficiently.

  The present invention has been made in view of the problems of conventional heterojunction FETs in nitride-based semiconductors, and provides a field effect transistor with reduced parasitic resistance, with the object of improving the performance and reliability of the device. And

  A field effect transistor according to one aspect of the present invention has a stacked body including a channel layer made of a nitride semiconductor and an electron supply layer made of a nitride semiconductor and located on the channel layer on a substrate, A field effect transistor having a source electrode, a drain electrode, and a gate electrode on a surface of the stacked body, wherein an n-type impurity concentration below each of the source electrode and / or the drain electrode in the channel layer is the gate electrode. N-type impurity concentration under the gate electrode is higher than the n-type impurity concentration under the source electrode and / or the drain electrode in the electron supply layer. It is.

  A method of manufacturing a field effect transistor according to another aspect of the present invention includes a step of forming a channel layer with a nitride semiconductor on a substrate, and an electron supply layer that generates polarization charges on the channel layer with a nitride semiconductor. A step of adding an n-type impurity to a position corresponding to a position below the source electrode and the drain electrode in the channel layer and / or the electron supply layer, and a step of activating the n-type impurity. This is a method for manufacturing a transistor.

  According to the present invention, it is possible to provide a field effect transistor with reduced parasitic resistance and to improve the performance and reliability of the element.

First embodiment.
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view of a field effect transistor (FET) 1 according to the present embodiment.

The FET 1 has a GaN buffer layer 12, a channel layer 13 made of InGaN or GaN, an AlGaN electron supply layer 14, and an n ⁺ -GaN contact layer 15 on a substrate 11 made of sapphire, SiC, GaN, Si, or AlN. Are stacked in order.

The GaN buffer layer 12 may have a thickness of 2 to 3 μm, for example. The GaN buffer layer 12 is a layer provided to alleviate lattice mismatch between the substrate 11 and a layer stacked on the substrate 11. The n ⁺ -GaN contact layer 15 is a layer provided for reducing the contact resistance between the electrode and the nitride semiconductor layer. In the n ⁺ -GaN contact layer 15, the layer thickness is preferably 5 to ²⁰ nm and the n-type impurity concentration is preferably 1 to 2 × 10 ²⁰ cm ⁻³ .

  In the channel layer 13, a two-dimensional electron gas region resulting from a piezoelectric polarization resulting from a difference in lattice constant between the channel layer 13 and the AlGaN electron supply layer 14 and from a difference in spontaneous polarization between the channel layer 13 and the AlGaN electron supply layer 14. 20 has occurred.

The n ⁺ -GaN contact layer 15 is selectively etched away at the central gate region, and a gate electrode 18 is formed through the AlGaN electron supply layer 14 whose surface is exposed. A source electrode 16 and a drain electrode 17 are formed via the n ⁺ -GaN contact layer 15.

Under the n ⁺ -GaN contact layer ^15, over the n + -GaN contact layer 15 AlGaN electron supply layer 14, the channel layer 13 is formed high concentration n-type impurity region 19. The high-concentration n-type impurity region 19 is a region created by diffusing the n-type impurity added to the n ⁺ -GaN contact layer 15 to the channel layer 13 by heat treatment.

  That is, in the FET 1 according to the present embodiment, the n-type impurity concentration under the source electrode 16 and the drain electrode 17 in the channel layer 13 is higher than the n-type impurity concentration under the gate electrode 18, and the electrons In the supply layer 14, the n-type impurity concentration below each of the source electrode 16 and the drain electrode 17 is higher than the n-type impurity concentration below the gate electrode 18.

  In the FET 1 of the present embodiment, the current flowing between the source electrode 16 and the drain electrode 17 is controlled by the voltage applied to the gate electrode 18. Since the two-dimensional electron gas region 20 exists near the interface with the AlGaN electron supply layer 14 in the channel layer 13, a large drain current can flow.

  In the FET 1 of the present embodiment, in the channel layer 13, the n-type impurity concentration under each of the source electrode 16 and the drain electrode 17 is higher than the n-type impurity concentration under the gate electrode 18, and the electron supply In the layer 14, the n-type impurity concentration below each of the source electrode 16 and the drain electrode 17 is higher than the n-type impurity concentration below the gate electrode 18. The resistance to the gas region 20 is significantly reduced.

  Further, since the n-type impurity added at a high concentration is activated and positively charged, the negative polarization charge existing at the interface between the electron supply layer 14 and the contact layer 15 can be canceled out. As a result, the potential barrier existing at the interface between the electron supply layer 14 and the contact layer 15 is lowered, and the parasitic resistance of the FET 1 can be reduced.

  The AlGaN electron supply layer 14 may use an undoped layer for a part or all of it. Using an undoped layer for the electron supply layer 14 has an effect of reducing the gate current.

  Further, the gate current is reduced by thinning the AlGaN electron supply layer 14 or by forming a groove in the AlGaN electron supply layer 14 located under the gate electrode 18 by dry etching to form a recessed gate structure in which the gate electrode is embedded. It is possible.

  Both of these have the effect of lowering the threshold of the reverse voltage applied to the gate electrode at the same time as the gate current is reduced. If the thickness of the AlGaN electron supply layer 14 under the gate electrode 18 is 5 nm or less, the threshold is increased. Is a normally-off type FET.

  There are two types of FETs: normally-on type and normally-off type. Normally-on type has a current between the source electrode and the drain electrode when the reverse voltage applied to the gate electrode is zero. The normally-off type is a FET in which the current flowing between the source electrode and the drain electrode is zero when the reverse voltage applied to the gate electrode is zero.

FIG. 2 schematically shows a potential distribution in a cross section at AA in the high concentration n-type impurity region 19 of FIG. Since the AlGaN electron supply layer 14 is doped with high-concentration n-type impurities, the potential distribution is greatly curved. Further, it is possible to offset the negative charge at the interface between the AlGaN electron supply layer 14 and the ⁿ + -GaN contact layer 15, present at the interface between the AlGaN electron supply layer 14 and the ⁿ + -GaN contact layer 15 The height of the potential barrier can be lowered.

Lowering the potential barrier allows electrons to tunnel through the potential barrier. Further, since the potential distribution is curved, the thickness of the potential barrier at the interface between the AlGaN electron supply layer 14 and the n ⁺ -GaN contact layer 15 is reduced, and the probability that electrons tunnel is increased. For this reason, the resistance between the source electrode 16 and the drain electrode 17 and the two-dimensional electron gas 20 is reduced.

Next, a method for manufacturing the FET 1 according to the first embodiment will be described with reference to FIG. On the sapphire substrate 11, for example, using a metal organic vapor phase epitaxy (MOVPE), the buffer layer 12, the channel layer 13, the electron supply layer 14, and the n ⁺ -contact layer 15 are sequentially arranged from the bottom. Laminate (see FIG. 3A).

The substrate 11 may use not only sapphire but also SiC, GaN, Si, and AlN. The buffer layer 12 is made of GaN. The channel layer 13 is made of undoped GaN or undoped InGaN, and preferably has a layer thickness of 2 to 3 μm. The electron supply layer 14 is made of AlGaN, and as an example of the composition, the electron supply layer 14 is preferably made of Al _0.25 Ga _0.75 N with a layer thickness of 20 nm and Si added at 1 × 10 ¹⁸ cm ⁻³ .

The contact layer 15 is made of GaN and needs to have a higher n-type impurity concentration than the electron supply layer 14. This is because in the FET 1 according to the present embodiment, it is necessary to diffuse the n-type impurity of the contact layer 15 in order to create the high-concentration n-type impurity region 19. As an example of the composition, the layer thickness is preferably 5 nm and the Si doping amount is preferably 2 × 10 ²⁰ cm ⁻³ .

After the contact layer 15 is laminated, a patterned photoresist 21 is formed using photolithography. Using the photoresist 21 as an etching mask, the n ⁺ -GaN contact layer 15 is selectively removed by dry etching using, for example, an ICP method (see FIG. 3B). After removing the photoresist 21, a heat treatment (for example, 1150 ° C., 30 minutes) is performed in a nitrogen atmosphere to form a high-concentration n-type impurity region 19 by diffusion and activation of Si (see FIG. 3C). .

  The function of supplying electrons is not sufficiently exhibited when the n-type impurity is added to the nitride semiconductor, and the function of supplying electrons is performed by being activated. Therefore, in the present embodiment, the n-type impurities are diffused up to the channel layer 13 and activated at the same time by processing at a high temperature of 900 ° C. or higher and 1400 ° C. or lower.

After the heat treatment, a source electrode 16 and a drain electrode 17 (for example, a Ti layer having a thickness of 10 nm and an Al layer having a thickness of 200 nm) made of Ti / Al are formed using, for example, electron gun evaporation and a lift-off method. , N ⁺ -GaN layer 15. The source electrode 16 and the drain electrode 17 form an ohmic junction, for example, by performing lamp annealing at 650 ° C. for 30 seconds.

  A gate electrode 18 made of Pt / Au (for example, a Pt layer having a thickness of 10 nm and an Au layer having a thickness of 200 nm) is formed via the electron supply layer 14 using electron gun vapor deposition and a lift-off method.

Si added to the FET 1 according to the present embodiment can be activated almost entirely by heat treatment at 900 ° C. or higher and 1400 ° C. or lower (for example, 1150 ° C.). Thereby, the density of activated Si in the n ⁺ -GaN contact layer 15 can be made higher than the Si concentration in the contact layer in the FET formed by MOVPE, and the source electrode 16 and the drain electrode 17 and the n ⁺ − The effect that the contact resistance with the GaN contact layer 15 can be reduced is obtained.

Further, in the step of dry etching the n ⁺ -GaN contact layer 15, the surface of the electron supply layer 14 is damaged, but this damage can be recovered by heat treatment. Thereby, it is possible to obtain an FET having excellent reliability. As described above, a semiconductor device used in a microwave amplifier constituting a wireless communication system such as a mobile phone, satellite communication, or WLAN can be used as an example of utilizing an FET having excellent reliability.

  The conditions in the substrate material, nitride semiconductor material, electrode material, and manufacturing method described in this embodiment are not limited to these, and the materials and structures used in the manufacture of GaN-based heterojunction field effect transistors are not limited thereto. The present invention can be widely applied.

  For example, in addition to sapphire, SiC, GaN, Si, AlN, or the like can be used as the substrate material, and the buffer layer 12 has a multilayer structure including an AlN layer, an AlGaN layer, an InAlGaN layer, etc. as a part thereof. It can also be used.

Second embodiment.
FIG. 4 shows a configuration diagram of the FET 2 according to the second embodiment. In the second embodiment, the present invention is applied to an FET without a contact layer. The operation principle and components similar to those in the first embodiment are omitted.

The difference from the FET 1 according to the first embodiment is that the n ⁺ -GaN contact layer 15 is not provided, and the source electrode 16 and the drain electrode 17 are formed via the electron supply layer 14.

  Conventionally, it has been difficult to form an ohmic electrode with a low contact resistance on the AlGaN layer. However, by applying the present invention, the potential distribution of the electron supply layer 14 under the source electrode 16 and the drain electrode 17 is greatly curved, resulting in a potential barrier. And the probability of electron tunneling at the electrode / semiconductor interface increases, so that a low contact resistance can be easily obtained.

  Next, the manufacturing method of 2nd Embodiment is demonstrated with reference to FIG. On the SiC substrate 11, for example, by using metal organic vapor phase epitaxy (MOVPE), a GaN buffer layer 12 (for example, a layer thickness of 2 to 3 μm), a channel layer 13 made of undoped GaN or undoped InGaN, AlGaN electrons A supply layer 14 (for example, a layer thickness of 30 nm) is sequentially stacked (see FIG. 5A).

Next, a patterned photoresist 21 is formed using photolithography, and Si ions are implanted using this as a mask. (For example, it is performed under the conditions of a surface density of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 25 keV) (see FIG. 5B).

  After the ion implantation, the photoresist 21 is removed, and an AlN film 23 (not shown) is formed by sputtering for surface protection. After the surface protective AlN film 23 is formed, high-temperature heat treatment (for example, 1300 ° C., 30 minutes) is performed in a nitrogen atmosphere to diffuse and activate Si, thereby forming a high-concentration n-type impurity region 19 (FIG. 5). (C)). Further, by performing the above-described heat treatment, it is possible to remove defects in the electron supply layer 14 due to ion implantation.

  Thereafter, the AlN film 23 is removed by etching, and the source electrode 16 and the drain electrode 17 made of Ti / Au (for example, a Ti layer having a thickness of 10 nm and an Au layer having a thickness of 300 nm) are subjected to electron gun evaporation and a lift-off method. And installed through the high-concentration n-type impurity region 19. After the source electrode 16 and the drain electrode 17 are installed, an ohmic junction is formed by lamp annealing (for example, 800 ° C., 30 seconds).

  Next, a gate electrode 18 composed of Ni / Au (for example, a Ni layer having a thickness of 15 nm and an Au layer having a thickness of 400 nm) is formed via the AlGaN electron supply layer 14 by using an electron gun deposition and a lift-off method. Form FET2 by forming.

  In the FET 2 according to the present embodiment, the high concentration n-type impurity region 19 is formed by ion implantation. By ion implantation, it becomes easy to specify the location where Si is diffused, and the diffusion of Si can be controlled up to the two-dimensional electron gas region 20.

Third embodiment.
FIG. 6 shows a configuration diagram of the FET 3 according to the third embodiment. In the third embodiment, the present invention is applied to an FET having a MIS gate structure in which an insulating film is inserted between the gate electrode 18 and the AlGaN electron supply layer 14. The operation principle and components similar to those in the first embodiment are omitted.

The difference from the FET 1 according to the first embodiment is that the n ⁺ -GaN contact layer 15 is not provided, the source electrode 16 and the drain electrode 17 are formed via the electron supply layer 14, and the gate electrode 18 and the AlGaN electrons are formed. That is, the insulating film 22 is inserted between the supply layer 14.

Next, the manufacturing method of 3rd Embodiment is demonstrated with reference to FIG. On the Si substrate 11, for example, using molecular beam epitaxy (MBE), a GaN buffer layer 12 (for example, a layer thickness of 2 to 3 μm), a channel layer 13 made of undoped GaN or undoped InGaN, and an AlGaN electron supply layer 14. (For example, the layer thickness is 5 nm) are sequentially stacked. After the electron supply layer 14 is stacked, the SiO ₂ insulating film 22 is formed by using a low pressure vapor phase epitaxy (LPCVD) (see FIG. 7A).

Next, a gate electrode 18 made of Mo having a thickness of 500 nm is formed using electron gun vapor deposition and a lift-off method. Si ion implantation is performed using the gate electrode 18 as a mask. (For example, it is performed under the conditions of a surface density of 8 × 10 ¹⁵ cm ⁻² and an acceleration energy of 25 keV) (see FIG. 7B).

  After Si ion implantation, heat treatment using lamp annealing (for example, 200 ° C. for 2 minutes) is performed to diffuse and activate Si, thereby forming a high-concentration n-type impurity region 19 (see FIG. 7C). .

  Finally, the source electrode 16 and the drain electrode 17 composed of Nb / Al (for example, the thickness of the Nb layer is 15 nm and the thickness of the Al layer is 300 nm) are applied to the high-concentration n-type by electron gun evaporation and lift-off method. An FET 3 is obtained by installing through the impurity region 19 and performing lamp annealing (for example, 650 ° C., 30 seconds) to form an ohmic junction.

  In the present embodiment, by performing ion implantation using the gate electrode as a mask, a self-alignment process that does not require alignment between the gate electrode 18 and the high-concentration n-type impurity region 19 is realized. For this reason, it is possible to manufacture an FET that is excellent in mass productivity and can provide a high yield.

  Further, since the lateral distance between the gate electrode 18 and the high-concentration n-type impurity region 19 can be reduced to zero, the parasitic resistance between the source electrode and the gate electrode and between the gate electrode and the drain electrode can be significantly reduced.

  Further, the electron supply layer 14 is thinned or dry etching is performed to form a groove in the electron supply layer 14 located below the gate electrode 18, an insulating film is formed in the groove, and the gate electrode is embedded via the insulating film. A gate current can be reduced by using a recessed gate structure.

In the second and third embodiments described above, as in the first embodiment, the substrate material, the nitride semiconductor material, the electrode material, and the conditions in the manufacturing method are not limited to this, and GaN Needless to say, the present invention can be widely applied to materials and structures used in the manufacture of heterojunction field-effect transistors. For example, the insulating film 22 is not limited to SiO ₂ , and AlN, SiN, Al ₂ O ₃ , MgO, or the like can be used.

Further, the combination of the structure and the manufacturing method is not limited to these. For example, the high-concentration n-type impurity region in the first embodiment may be formed using ion implantation. It is also clear that a MIS gate structure can be realized even with a structure using an n ⁺ -GaN contact layer.

Further, a GaN cap layer to which Si is added at a relatively low concentration (1 × 10 ¹⁸ cm ⁻³ or less) or an impurity is not added is epitaxially grown on the electron supply layer, and the GaN cap layer is not etched away, An FET can be manufactured according to the manufacturing method of the second or third embodiment. By adopting such a layer structure, an effect of reducing the gate leakage current can be obtained by the potential barrier generated at the interface between the GaN cap layer and the AlGaN electron supply layer.

  In any of the first, second, and third embodiments described above, the region having a high n-type impurity concentration in the channel layer or the electron supply layer need not be both under the source electrode and the drain electrode. , Either one of the source electrode and the drain electrode may be provided. Such a structure is, for example, that in the first embodiment, the contact layer 15 is left only in either the source electrode side or the drain electrode side in the step of removing the contact layer 15 by etching. In the second embodiment, n In the step of ion-implanting the type impurity, it can be obtained by ion-implanting only one of the source electrode side and the drain electrode side. As described above, when the high n-type impurity concentration region is set to only one of the source electrode side and the drain electrode side, the parasitic resistance reduction effect is slightly smaller than when both are set to the high n-type impurity concentration. On the other hand, there is an effect that a high breakdown voltage can be obtained.

Sectional drawing of the field effect transistor which concerns on the 1st Embodiment of this invention. The potential conceptual diagram in the AA cross section of the field effect transistor which concerns on the 1st Embodiment of this invention. The manufacturing method of the field effect transistor which concerns on the 1st Embodiment of this invention. Sectional drawing of the field effect transistor which concerns on the 2nd Embodiment of this invention. The manufacturing method of the field effect transistor which concerns on the 2nd Embodiment of this invention. Sectional drawing of the field effect transistor which concerns on the 3rd Embodiment of this invention. The manufacturing method of the field effect transistor which concerns on the 3rd Embodiment of this invention. The block diagram of the conventional field effect transistor. The potential conceptual diagram in the BB cross section of the conventional field effect transistor.

Explanation of symbols

1 Field Effect Transistor According to First Embodiment
11 Substrate 12 GaN buffer layer 13 Channel layer 14 AlGaN electron supply layer 15 n ⁺ -GaN contact layer 16 Source electrode 17 Drain electrode 18 Gate electrode 19 High-concentration n-type impurity region 20 Two-dimensional electron gas region 21 Photoresist 22 Insulating film 23 Surface protective film 90 Conventional semiconductor device 91 Sapphire substrate 92 Low temperature GaN buffer layer 93 Undoped GaN layer 94 Electron supply layer 95 Contact layer 96 Source electrode 96 97 Drain electrode 98 Gate electrode 99 Two-dimensional electron gas layer

Claims (10)

On the substrate, a laminate including a channel layer made of a nitride semiconductor and an electron supply layer made of a nitride semiconductor and located on the channel layer,
A field effect transistor comprising a source electrode, a drain electrode and a gate electrode on the surface of the laminate,
In the channel layer, an n-type impurity concentration under each of the source electrode and / or the drain electrode is higher than an n-type impurity concentration under the gate electrode,
Wherein the electron supply layer, the source electrode and / or the n-type impurity concentration under the drain electrode each, rather higher than the n-type impurity concentration beneath the gate electrode,
On the electron supply layer, a contact layer is provided between the source electrode and / or the drain electrode and the electron supply layer.
Field effect transistor. The field effect transistor according to claim 1 ,
A field effect transistor, wherein the gate electrode is formed in a groove formed in a part of the electron supply layer. The field effect transistor according to claim 1 ,
A field effect transistor comprising the electron supply layer and an insulating film, wherein the insulating film is between the gate electrode and the electron supply layer. The field effect transistor according to claim 3 ,
A field effect transistor, wherein the insulating film and the gate electrode are formed in a groove formed in a part of the electron supply layer. The field effect transistor according to any one of claims 1 to 4 ,
A field effect transistor having a cap layer on the electron supply layer. A method of manufacturing a field effect transistor, comprising:
Forming a channel layer of a nitride semiconductor on a substrate;
Forming an electron supply layer that generates polarization charges on the channel layer with a nitride semiconductor;
Adding an n-type impurity at a position corresponding to a position below the source electrode and / or drain electrode in the channel layer and the electron supply layer;
Activating the n-type impurity ;
Forming a contact layer between the source and drain electrodes and the electron supply layer with a nitride semiconductor having the n-type impurity;
A method of manufacturing a field effect transistor comprising: It is a manufacturing method of the field effect transistor according to claim 6 ,
A method of manufacturing a field effect transistor, wherein the step of activating the n-type impurity is high-temperature heat treatment at 900 ° C. to 1400 ° C. A method of manufacturing a field effect transistor according to claim 6 or 7 ,
Adding the n-type impurity;
A method of manufacturing a field effect transistor, wherein the step of activating the n-type impurity is performed simultaneously. A method of manufacturing a field effect transistor according to any one of claims 6 to 8,
A method of manufacturing a field effect transistor including a step of diffusing an n-type impurity of the contact layer by performing a high-temperature heat treatment at 900 ° C. to 1400 ° C. A method of manufacturing a field effect transistor according to any one of claims 6 to 9 ,
A method of manufacturing a field effect transistor including a step of performing ion implantation using a gate electrode as a mask.

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