JP5117031B2 - HEMT operating normally off - Google Patents

Description

  The present invention relates to a HEMT (High Electron Mobility Transistor) that operates normally off.

  HEMTs having a heterostructure in which semiconductor layers having different band gap widths are stacked are known. A normal HEMT includes a gate structure for controlling on / off of current between a pair of main electrodes (for example, a drain electrode and a source electrode). The gate structure is formed on the first semiconductor layer, the second semiconductor layer formed on the first semiconductor layer and having a wider band gap than the first semiconductor layer, and on the second semiconductor layer. And a gate electrode formed on the gate insulating film. The first semiconductor layer and the second semiconductor layer constitute a hetero interface, and the hetero interface extends between the pair of main electrodes.

  For example, HEMTs using nitride semiconductors as materials for the first semiconductor layer and the second semiconductor layer have been developed. Since nitride semiconductors have a large dielectric breakdown electric field and saturated electron density, HEMTs using nitride semiconductors are expected to be capable of controlling a large current with a high breakdown voltage. Patent Document 1 discloses a HEMT using a nitride semiconductor.

JP-A-10-294442

  Usually, in a HEMT using a nitride semiconductor, a two-dimensional electron gas layer is generated at the heterointerface between the first semiconductor layer and the second semiconductor layer when no voltage is applied to the gate electrode. When a negative voltage is applied to the gate electrode, the depletion layer extends to the heterointerface and the two-dimensional electron gas layer disappears. Therefore, HEMTs using nitride semiconductors operate normally.

  Development of a safe and easy-to-use normally-off HEMT is also underway. For example, a technique for realizing normally-off by reducing the piezo effect generated between the first semiconductor layer and the second semiconductor layer, or a depletion at the heterointerface between the first semiconductor layer and the second semiconductor layer by a built-in voltage of the pn junction A technique for realizing normally-off by forming a layer and a technique for realizing normally-off by introducing a positive charge into a second semiconductor layer are known. In HEMTs operating normally off, when no voltage is applied to the gate electrode, a two-dimensional electron gas layer is not generated at the heterointerface between the first semiconductor layer and the second semiconductor layer, and a positive voltage is applied to the gate electrode. In this case, a two-dimensional electron gas layer is generated at the heterointerface between the first semiconductor layer and the second semiconductor layer.

  However, a detailed study of HEMTs operating with normally-off obtained by these techniques has revealed that the following phenomenon has occurred. In a conventional HEMT that operates normally off, when the voltage applied to the gate electrode is increased from 0 V, a two-dimensional electron gas layer is generated at the heterointerface between the first semiconductor layer and the second semiconductor layer. It has been found that an inversion layer is generated at the interface between the second semiconductor layer and the gate insulating film. If an inversion layer is first generated at the interface between the second semiconductor layer and the gate insulating film, it becomes difficult to exert a gate voltage action on the heterointerface between the first semiconductor layer and the second semiconductor layer. For this reason, after the inversion layer is generated at the interface between the second semiconductor layer and the gate insulating film, the carrier density of the two-dimensional electron gas layer cannot be increased even if the gate voltage is increased, which is an advantage of HEMT. The characteristic that the on-resistance is small could not be actually obtained.

  The present invention was created from the first discovery of the above phenomenon. The HEMT configured to avoid the above phenomenon can obtain a low on-resistance, which is an original characteristic of the HEMT, and can provide a very useful result.

That is, the HEMT disclosed in the present specification includes a first semiconductor layer and a second semiconductor layer that is formed on at least a part of the first semiconductor layer and has a wider band gap than the first semiconductor layer. And a gate insulating film formed on at least a part of the second semiconductor layer, and a gate electrode formed on at least a part of the gate insulating film. In the HEMT disclosed in this specification, when a voltage is not applied to the gate electrode, a two-dimensional electron gas layer is not generated at the interface between the first semiconductor layer and the second semiconductor layer. In the HEMT disclosed in this specification, when the positive voltage applied to the gate electrode is increased, the first semiconductor layer is formed before the inversion layer is generated at the interface between the second semiconductor layer and the gate insulating film. A two-dimensional electron gas layer is generated at the interface between the first semiconductor layer and the second semiconductor layer.
In order to generate the two-dimensional electron gas layer prior to the generation of the inversion layer, it can be realized, for example, by adjusting the thickness of the second semiconductor layer to be thin. The present invention is characterized by utilizing a phenomenon first discovered by the present inventors. If knowledge relating to this phenomenon is obtained, the HEMT that embodies the present invention can take various forms.
According to the above HEMT, when a positive voltage is applied to the gate electrode, the gate voltage can sufficiently affect the heterointerface between the first semiconductor layer and the second semiconductor layer. For this reason, the carrier density at the heterointerface between the first semiconductor layer and the second semiconductor layer can be increased. The above-mentioned HEMT can obtain the characteristic that the on-resistance is small.

In one HEMT disclosed in this specification, when a positive voltage is applied to the gate electrode, the carrier density generated at the interface between the second semiconductor layer and the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or less. , that exists a state in which the carrier density of the first semiconductor layer and the 2-dimensional electron gas layer generated at the interface of the second semiconductor layer is 1 × 10 ¹⁹ cm ^-3 or more.
If the density of carriers generated at the interface between the second semiconductor layer and the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or less, it can be evaluated that the inversion layer is not formed. When the carrier density is 1 × 10 ¹⁸ cm ⁻³ or less, the gate voltage action is not hindered at the interface between the second semiconductor layer and the gate insulating film, but at the hetero interface between the first semiconductor layer and the second semiconductor layer. Can range up to.
Furthermore, when the carrier density of the two-dimensional electron gas layer is 1 × 10 ¹⁹ cm ⁻³ or more, it can be evaluated that a carrier density comparable to that of a HEMT operating with a conventional normally-on is achieved. Therefore, according to the above-described HEMT, it is possible to operate with normally-off while achieving on-resistance comparable to that of a conventional HEMT that operates with normally-on, which is extremely useful in practice.

In another HEMT disclosed in this specification, when a voltage of 10 V is applied to the gate electrode, the carrier density generated at the interface between the second semiconductor layer and the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or less. der Ru.
Usually, the control voltage applied to the gate electrode is often varied between 0 V and 10 V, and on / off of the semiconductor device is often controlled based on the control voltage. Therefore, when a carrier density generated at the interface between the second semiconductor layer and the gate insulating film when a voltage of 10 V is applied to the gate electrode is 1 × 10 ¹⁸ cm ⁻³ or less, the gate voltage acts as the second semiconductor. Without being hindered at the interface between the layer and the gate insulating film, it can sufficiently reach the heterointerface between the first semiconductor layer and the second semiconductor layer, and low on-resistance can be obtained.

In HEMT disclosed herein, the material of the first semiconductor layer and the second semiconductor layer, Ru nitride semiconductor der.
By using a nitride semiconductor, a HEMT capable of controlling a large current with a high breakdown voltage can be obtained.

The HEMT disclosed in this specification preferably further includes a third semiconductor layer in contact with at least the back surface of the first semiconductor layer in a range facing the gate electrode and containing a p-type impurity. Furthermore, the first semiconductor layer is gallium nitride, the second semiconductor layer is gallium nitride / aluminum, the third semiconductor layer is gallium nitride, the gate insulating film is silicon oxide or silicon nitride, and the gate electrode has a large number of gate electrodes. It is preferably a laminated film of one or more layers made of crystalline silicon, aluminum, nickel, titanium, tungsten, molybdenum, gold, platinum, or silicite thereof. In the HEMT disclosed in the present specification, the thickness of the second semiconductor layer is preferably 20 nm or less. In this form of HEMT, it has been confirmed that the carrier density of the two-dimensional electron gas layer generated at the heterointerface between the first semiconductor layer and the second semiconductor layer is 1 × 10 ¹⁹ cm ⁻³ or more. .
Furthermore, the thickness of the second semiconductor layer is preferably 10 nm or less. In this case, the carrier density generated at the interface between the second semiconductor layer and the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or less, and the two-dimensional electron gas layer generated at the heterointerface between the first semiconductor layer and the second semiconductor layer. It has been confirmed that a carrier density of 1 × 10 ¹⁹ cm ⁻³ or more exists.

  According to the HEMT disclosed in this specification, it is possible to obtain a low on-resistance characteristic while operating normally off.

Preferred features of the invention are listed.
(First Feature) A nitride semiconductor is represented by a general formula of Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ 1-XY ≦ 1).
(Second Feature) The HEMT preferably includes a p-type third semiconductor layer facing the interface between the first semiconductor layer and the second semiconductor layer. The third semiconductor layer is preferably opposed to the interface between the first semiconductor layer and the second semiconductor layer via the first semiconductor layer.

Embodiments will be described in detail below with reference to the drawings.
FIG. 1 schematically shows a cross-sectional view of a main part of a HEMT 10 using a nitride semiconductor. The HEMT 10 shown in FIG. 1 embodies basic components necessary for explaining the technique of the present invention in a basic form. The technology of the present invention can also be applied to various other forms of HEMTs, for example, it can be applied to HEMTs such as Japanese Patent Application Laid-Open No. 2004-260140 already filed by the present applicant. is there.
The HEMT 10 is formed on a first semiconductor layer 24 of gallium nitride, a second semiconductor layer 26 of gallium nitride / aluminum formed on the first semiconductor layer 24, and a part of the second semiconductor layer 26. A gate insulating film 34 and a gate electrode 36 formed on the gate insulating film 34. A drain electrode 32 and a source electrode 38 are also formed on the second semiconductor layer 36, and the drain electrode 32 and the source electrode 38 are separated by the gate insulating film 34 and the gate electrode 36. The HEMT 10 further includes a third semiconductor layer 22 of gallium nitride in contact with the back surface of the first semiconductor layer 24.

The first semiconductor layer 24 is an intrinsic i-type that does not substantially contain impurities, and its impurity concentration is 1 × 10 ¹³ cm ⁻³ . The thickness of the first semiconductor layer 24 is about 2 μm. The first semiconductor layer 24 can be obtained from the surface of a semiconductor substrate such as sapphire (not shown) using a crystal growth technique.
The second semiconductor layer 26 may not substantially contain impurities, and may contain n-type impurities. The band gap of the second semiconductor layer 26 is wider than the band gap of the first semiconductor layer 24. As will be described later, the thickness 26T of the second semiconductor layer 26 is adjusted to be extremely thin. The second semiconductor layer 26 can be obtained from the surface of the first semiconductor layer 24 using a crystal growth technique.
Silicon oxide is used as the material of the gate insulating film 34. Alternatively, silicon nitride may be used. The thickness of the gate insulating film is about 0.1 μm.
Polycrystalline silicon is used as the material of the gate electrode 36. Instead of this, a single layer film made of aluminum, nickel, titanium, tungsten, molybdenum, gold, platinum, or silicite thereof may be used. Alternatively, a laminated film including two or more layers made of polycrystalline silicon, aluminum, nickel, titanium, tungsten, molybdenum, gold, platinum, or silicite thereof may be used.
The material of the drain electrode 32 and the source electrode 38 is a laminated film of titanium and aluminum, and is in ohmic contact with the second semiconductor layer 26.
The third semiconductor layer 22 contains magnesium as an impurity and has p-type conductivity. The impurity concentration of the third semiconductor layer 22 is about 1 × 10 ¹⁹ cm ⁻³ . The thickness of the third semiconductor layer 22 is about 3 μm. The third semiconductor layer 22 can be obtained using a crystal growth technique from the surface of a semiconductor substrate such as sapphire (not shown). Alternatively, the third semiconductor layer 22 may be formed by introducing magnesium into the back surface of the first semiconductor layer 24.

  Next, the operation of the HEMT 10 will be described. In the HEMT 10, since the third semiconductor layer 22 is in contact with the back surface of the first semiconductor layer 24, the first semiconductor layer 24 is depleted based on the built-in voltage at the junction surface between the first semiconductor layer 24 and the third semiconductor layer 22. A layer is formed. The depletion layer extends to the surface of the first semiconductor layer 24. Therefore, in the HEMT 10, when no voltage is applied to the gate electrode 36, the second semiconductor layer 26 side of the heterointerface 25 between the first semiconductor layer 24 and the second semiconductor layer 26 is depleted, and the two-dimensional The electron gas layer (2DEG) is not generated. Therefore, in the HEMT 10, when a voltage is not applied to the gate electrode 36, a part of the two-dimensional electron gas layer (2DEG) between the drain electrode 32 and the source electrode 38 is cut off. No current can flow between the electrodes 38. The HEMT 10 can operate normally off.

  Next, when a positive gate voltage is applied to the gate electrode 36, a two-dimensional electron gas layer (2DEG) is generated on the second semiconductor layer 26 side of the heterointerface 25 between the first semiconductor layer 24 and the second semiconductor layer 26. To do. Thereby, since the two-dimensional electron gas layer (2DEG) between the drain electrode 32 and the source electrode 38 is continuous, a current can flow between the drain electrode 32 and the source electrode 38.

  Here, the features of the HEMT 10 will be described. In the HEMT 10, when the voltage applied to the gate electrode 36 is increased from 0 V, the first semiconductor layer 24 and the first semiconductor layer 24 are formed before the inversion layer is generated at the interface 27 between the second semiconductor layer 26 and the gate insulating film 34. A two-dimensional electron gas layer (2DEG) is generated at the heterointerface 25 of the two semiconductor layers 26. This phenomenon is realized by forming the second semiconductor layer 26 with a small thickness 26T.

FIG. 2 shows the relationship between the gate voltage and the peak carrier density of the two-dimensional electron gas layer (2DEG) when the thickness 26T of the second semiconductor layer 26 is changed in the range of 5 nm to 50 nm. FIG. 3 shows the relationship between the thickness 26T of the second semiconductor layer 26 and the peak carrier density of the two-dimensional electron gas layer (2DEG) when the gate voltage is 30V. These results are obtained by using TCAD (Synopsys MEDICI) simulation software.
As shown in FIGS. 2 and 3, it can be seen that the peak carrier density of the two-dimensional electron gas layer (2DEG) increases as the thickness 26T of the second semiconductor layer 26 decreases. In particular, as shown in FIG. 2, when the thickness 26T of the second semiconductor layer 26 is 20 nm or less, there is a state where the peak carrier density of the two-dimensional electron gas layer (2DEG) is 1 × 10 ¹⁹ cm ⁻³ or more. It was confirmed that Here, the peak carrier density of the two-dimensional electron gas layer (2DEG) is 1 × 10 ¹⁹ cm ^-3 or higher, which means that the carrier density is comparable to that of HEMTs operating with conventional normally-on. To do. There is a report that a sheet carrier density of 1 × 10 ¹³ cm ^-2 has been achieved in a conventional HEMT that operates with normally-on (see IEICE ED2003-149). Since the thickness of the two-dimensional electron gas layer (2DEG) is generally about 10 nm, it can be evaluated that the carrier density of a conventional HEMT operating with normally-on is about 1 × 10 ¹⁹ cm ⁻³ . That is, the HEMT 10 of this embodiment can operate normally off while achieving a carrier density comparable to that of a conventional HEMT that operates normally.

As shown in FIGS. 2 and 3, the phenomenon that the peak carrier density of the two-dimensional electron gas layer (2DEG) increases as the thickness 26T of the second semiconductor layer 26 decreases, the second semiconductor layer 26 and the gate insulating film 34 This is because the carrier density induced at the interface 27 is reduced. This can be explained from the results of FIG. FIG. 4 shows the relationship between the gate voltage and the carrier density induced at the interface 27 when the thickness 26T of the second semiconductor layer 26 is changed in the range of 5 nm to 50 nm.
As shown in FIG. 4, it can be seen that the carrier density induced at the interface 27 decreases as the thickness 26T of the second semiconductor layer 26 decreases. When the thickness 26T of the second semiconductor layer 26 is 5 nm, the carrier density induced at the interface 27 is 1 × 10 ¹⁶ cm ⁻³ or less and does not appear on the drawing. Here, the inflection points a to e shown in FIG. 4 correspond to the inflection points a to e shown in FIG. The inflection points a to e shown in FIG. 4 exist in the range of carrier density of 1 × 10 ^{18 to} 0.5 × 10 ¹⁹ cm ⁻³ . That is, when the carrier density induced at the interface 27 reaches the range of 1 × 10 ^{18 to} 0.5 × 10 ¹⁹ cm ⁻³ , the peak carrier density of the two-dimensional electron gas layer (2DEG) increases as shown in FIG. It turns out that it is suppressed.

This is because when the carrier density induced at the interface 27 between the second semiconductor layer 26 and the gate insulating film 34 reaches the range of 1 × 10 ^{18 to} 0.5 × 10 ¹⁹ cm ⁻³ , the action of the gate voltage is induced at the interface 27. This is because it is hindered by the generated carriers and does not reach the heterointerface 25 between the first semiconductor layer 24 and the second semiconductor layer 26. In other words, if the carrier density induced at the interface 27 between the second semiconductor layer 26 and the gate insulating film 34 is 1 × 10 ¹⁸ or less, the gate voltage acts as the interface 27 between the second semiconductor layer 26 and the gate insulating film 34. Without being hindered by this, it can sufficiently reach the heterointerface 25 between the first semiconductor layer 24 and the second semiconductor layer 26, and the peak carrier density of the two-dimensional electron gas layer (2DEG) can be increased.

Usually, the gate voltage applied to the gate electrode 36 is often changed between 0V and 10V, and on / off of the HEMT is often controlled based on the gate voltage. Accordingly, when the carrier density generated at the interface 27 between the second semiconductor layer 26 and the gate insulating film 34 when a voltage of 10 V is applied to the gate electrode 36 is 1 × 10 ¹⁸ cm ⁻³ or less, the hetero interface 25 The action of the gate voltage can be sufficiently exerted, and a low on-resistance can be obtained. As shown in FIG. 4, when the thickness 26T of the second semiconductor layer 26 is 20 nm or less, the carrier density generated at the interface 27 when the voltage of 10 V is applied to the gate electrode 36 is 1 × 10 ¹⁸ cm ^−3. It was confirmed that the following can be made.

Further, as shown in FIGS. 2 and 4, when the thickness 26T of the second semiconductor layer 26 is 10 nm or less, the carrier density generated at the interface 27 between the second semiconductor layer 26 and the gate insulating film 34 is 1 × 10 ^18. cm ^-3 or less, there is a state in which the carrier density of the two-dimensional electron gas layer and the first semiconductor layer 24 occurs at the hetero-interface 25 of the second semiconductor layer 26 (2DEG) is 1 × 10 ¹⁹ cm ^-3 or more It was confirmed that When operated in this state, the HEMT 10 can exhibit an extremely low on-resistance.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of HEMT of an Example is typically shown. The relationship between the gate voltage when the thickness 26T of the second semiconductor layer 26 is changed and the peak carrier density of the two-dimensional electron gas layer (2DEG) is shown. The relationship between the thickness 26T of the second semiconductor layer 26 and the peak carrier density of the two-dimensional electron gas layer (2DEG) at the heterointerface 25 when the gate voltage is 30V is shown. The relationship between the gate voltage and the carrier density of the interface 27 when the thickness 26T of the second semiconductor layer 26 is changed is shown.

Explanation of symbols

22: third semiconductor layer 24: first semiconductor layer 26: second semiconductor layer 32: drain electrode 34: gate insulating film 36: gate electrode 38: source electrode

Claims (4)

A first semiconductor layer of nitride semiconductor ;
A nitride semiconductor second semiconductor layer formed on at least a portion of the first semiconductor layer and having a wider band gap than the first semiconductor layer;
A gate insulating film formed on at least part of the second semiconductor layer;
A gate electrode formed on at least a part of the gate insulating film;
When no voltage is applied to the gate electrode, a two-dimensional electron gas layer is not generated at the interface between the first semiconductor layer and the second semiconductor layer,
When a positive voltage is applied to the gate electrode, the carrier density generated at the interface between the second semiconductor layer and the gate insulating film is 1 × 10 ¹⁸ cm ⁻³ or less, and the interface between the first semiconductor layer and the second semiconductor layer HEMT is characterized in that there is a state in which the carrier density of the two-dimensional electron gas layer generated at 1 is 10 × 10 ¹⁹ cm ⁻³ or more . A first semiconductor layer of nitride semiconductor ;
A nitride semiconductor second semiconductor layer formed on at least a portion of the first semiconductor layer and having a wider band gap than the first semiconductor layer;
A gate insulating film formed on at least part of the second semiconductor layer;
A gate electrode formed on at least a part of the gate insulating film;
When no voltage is applied to the gate electrode, a two-dimensional electron gas layer is not generated at the interface between the first semiconductor layer and the second semiconductor layer,
A HEMT, wherein a carrier density generated at the interface between the second semiconductor layer and the gate insulating film when a voltage of 10 V is applied to the gate electrode is 1 × 10 ¹⁸ cm ⁻³ or less . A third semiconductor layer that is in contact with at least the back surface of the first semiconductor layer in a range facing the gate electrode and includes a p-type impurity;
The first semiconductor layer is gallium nitride,
The second semiconductor layer is gallium nitride / aluminum,
The third semiconductor layer is gallium nitride,
The gate insulating film is silicon oxide or silicon nitride,
The gate electrode is a laminated film of one or more layers made of polycrystalline silicon, aluminum, nickel, titanium, tungsten, molybdenum, gold, platinum, or silicite thereof.
The HEMT according to claim 1 or 2 , wherein the thickness of the second semiconductor layer is 20 nm or less. The HEMT according to claim 3 , wherein the thickness of the second semiconductor layer is 10 nm or less.

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