JP2008192701A - GaN-BASED SEMICONDUCTOR ELEMENT - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN-based semiconductor element having a GaN-based semiconductor laminated structure having high breakdown voltage and low leakage. <P>SOLUTION: The semiconductor element is represented by a structure in which a third n-type GaN-type semiconductor layer 3, a first n-type GaN-based semiconductor layer 4, an i-type GaN-based semiconductor layer 5, a p-type GaN-based semiconductor layer 6, and a second n-type GaN-based semiconductor layer 7 are laminated on a substrate 1. The p-type GaN-based semiconductor layer 6 has an impurity concentration of ≤1×10<SP>20</SP>cm<SP>-3</SP>, and the first n-type GaN-based semiconductor layer 4 has an impurity concentration of ≤1×10<SP>18</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a GaN-based semiconductor device using a group III-V nitride semiconductor.

  For example, many devices using a nitride thin film have been proposed and realized, such as a high-intensity blue light-emitting device using a GaN-based thin film, a MISFET using an AlN / GaN thin film, and a HEMT using an AlGaN / GaN thin film.

  Conventionally, power devices using silicon semiconductors are used for power amplifier circuits, power supply circuits, motor drive circuits, and the like. However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands. Therefore, development of a GaN-based electronic device having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and small on-resistance has been proposed (see Non-Patent Document 1 below).

It is said that particularly important characteristics for a GaN-based electronic device for power devices are withstand voltage (withstand voltage) and on-resistance. As for the on-resistance, there is a method of reducing the on-resistance by shortening the channel length of the channel region. For example, a structure having an oblique gate electrode is considered. On the other hand, regarding the breakdown voltage, it is difficult to secure a high breakdown voltage in the lateral structure GaN-based electronic device in which the source electrode and the drain electrode are arranged in the horizontal direction. And a vertical GaN-based electronic device in which drain electrodes are arranged in a vertical direction have been proposed.
JP 2004-260140 A Okubo Satoshi, “GaN is behind the evolution of equipment, not just shining” June 5, 2006, Nikkei Electronics, p. 51-60

  In a lateral structure GaN-based electronic device, the distance between the source electrode and the drain electrode can be increased, so that the breakdown voltage is improved, but it is difficult to integrate, the on-resistance is increased, etc. There's a problem.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a GaN-based semiconductor device having a high breakdown voltage and a low on-resistance by a vertical structure.

In order to achieve the above object, the invention described in claim 1 is characterized in that at least a first n-type or i-type GaN-based semiconductor layer, a GaN-based semiconductor layer containing a p-type impurity, and a second n-type on a substrate. Alternatively, a GaN-based semiconductor element including an i-type GaN-based semiconductor layer in order, wherein the impurity concentration of the GaN-based semiconductor layer containing the p-type impurity is 1 × 10 ²⁰ cm ⁻³ or less, and the first n The impurity concentration of the i-type or i-type GaN-based semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or less.

According to a second aspect of the present invention, an impurity Mg concentration is 1 × 10 ¹⁸ cm ⁻ between the first n-type or i-type GaN-based semiconductor layer and a GaN-based semiconductor layer containing a p-type impurity. ^2. The GaN-based semiconductor element according to claim 1, wherein ^three or less i-type GaN-based semiconductor layers are formed.

  According to a third aspect of the present invention, the impurity concentration between the substrate and the first n-type or i-type GaN-based semiconductor layer is higher than that of the first n-type or i-type GaN-based semiconductor layer. 3. The GaN-based semiconductor device according to claim 1, wherein three n-type GaN-based semiconductor layers are formed.

  According to a fourth aspect of the present invention, in the GaN-based semiconductor according to any one of the first to third aspects, the thickness of the GaN-based semiconductor layer containing the p-type impurity is 2 μm or less. It is an element.

The invention according to claim 5 5. The GaN-based semiconductor element according to claim 1, wherein an impurity of the GaN-based semiconductor layer containing the p-type impurity is Mg.

  According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the impurity of the first n-type or i-type GaN-based semiconductor layer is Si or O. The GaN-based semiconductor device described.

  The invention according to claim 7 is characterized in that an impurity concentration of the first n-type or i-type GaN-based semiconductor layer is smaller than that of the second n-type or i-type GaN-based semiconductor layer. A GaN-based semiconductor device according to any one of claims 1 to 6.

  The invention according to claim 8 is characterized in that the thickness of the second n-type or i-type GaN-based semiconductor layer is 1 μm or less. This is a GaN-based semiconductor element.

The invention described in claim 9 is characterized in that the impurity concentration of the third n-type GaN-based semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or more. 2. A GaN-based semiconductor device according to item 1.

  The invention according to claim 10 is characterized in that a gate insulating film is formed in contact with a wall surface exposed by processing of the GaN-based semiconductor layer containing the p-type impurity. 2. A GaN-based semiconductor device according to item 1.

  The invention according to claim 11 is characterized in that the region in the vicinity of the wall surface is made of a semiconductor having a different conduction characteristic from the GaN-based semiconductor layer containing the p-type impurity. A semiconductor-based semiconductor device.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional structure of a GaN-based semiconductor device of the present invention. The GaN-based semiconductor device of the present invention includes three n-type GaN-based semiconductor layers, one i-type GaN-based semiconductor layer, and one p-type GaN-based semiconductor layer. Semiconductor layer 3 (corresponding to a third n-type GaN-based semiconductor layer), first n-type GaN-based semiconductor layer 4 (corresponding to a first n-type or i-type GaN-based semiconductor layer), i-type GaN-based semiconductor layer 5 , A p-type GaN-based semiconductor layer 6 (corresponding to a GaN-based semiconductor layer containing p-type impurities) and a second n-type GaN-based semiconductor layer 7 (corresponding to a second n-type or i-type GaN-based semiconductor layer) are stacked. It is expressed by a laminated structure. As will be described later, the i-type GaN-based semiconductor layer 5 expands a region to be a depletion layer and improves the breakdown voltage. However, the i-type GaN-based semiconductor layer 5 may have a structure excluding the i-type GaN-based semiconductor layer 5.

Here, a III-V group GaN-based semiconductor which is a hexagonal compound semiconductor is used as the GaN-based semiconductor, and the III-V group GaN-based semiconductor is a quaternary mixed crystal Al _x Ga _y In _z. N (x + y + z = 1, 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1), and includes GaN or a GaN compound. An i-type semiconductor means a semiconductor that does not contain intentional impurities, that is, includes a low-concentration n-type semiconductor, and is a semiconductor close to an intrinsic semiconductor.

  When a GaN-based semiconductor element having an npn type layer structure as shown in FIG. 1 is used for an electronic device such as an FET (field effect transistor), the p-type GaN-based semiconductor layer 6 is used as a channel layer. The second n-type GaN-based semiconductor layer 7 is used as a source layer and the third n-type GaN-based semiconductor layer 3 is used as a drain layer to operate as an electronic device. Therefore, the GaN-based semiconductor element of FIG. 1 is applied to an electronic device called a so-called vertical structure.

  In the pnp type, the npn type layer structure can realize only an element with low carrier mobility and low carrier concentration. In the pnp type, even when ions are implanted into the uppermost p-type layer to form a p + type layer, it is generally difficult to use a GaN-based p-type layer, and the uppermost layer is an n-type layer. This is relatively easy. Therefore, it was decided to use an npn type structure.

  Next, in order to use the GaN-based semiconductor element having the layer structure of FIG. 1 for a power device, it is essential to improve the breakdown voltage. First, in order to improve the breakdown voltage of the element, the impurity concentration and thickness of the n-type layer where the depletion layer expands during transistor operation becomes important. That is, although the first n-type GaN-based semiconductor layer 4 corresponds to the n-type layer, attention is focused on the impurity concentration of the first n-type GaN-based semiconductor layer 4. Note that Si (silicon), O (oxygen), or the like is used as the dopant of the n-type layer.

Here, the breakdown voltage V _max of the element is known to be inversely proportional to the impurity concentration N1 of the 1n-type GaN-based semiconductor layer 4, the smaller the impurity concentration N1, breakdown voltage of the device increases. The impurity concentration of the p-type GaN-based semiconductor layer 6 is greater than the 1n-type GaN-based semiconductor layer 4 is generally the breakdown voltage _{V max} and the impurity concentration N1 in the following relationship.
V _max = ε1 × (E _max ) ² / (2 × q × N1)
Here, E _max represents the breakdown electric field of the element, ε 1 represents the dielectric constant of the first n-type GaN-based semiconductor layer 4, and q represents the elementary electric quantity. For example, when the impurity concentration N1 of the first n-type GaN-based semiconductor layer 4 is 1 × 10 ¹⁸ cm ⁻³ and the dielectric breakdown electric field E _max is 3.5 M (V / cm), the breakdown voltage is 321 V. In order to maintain such a breakdown voltage, the impurity concentration of the first n-type GaN-based semiconductor layer 4 must be 1 × 10 ¹⁸ cm ⁻³ or less. Here, M represents mega. As described above, the first n-type GaN-based semiconductor layer 4 is composed of an n ⁻ -type GaN-based semiconductor layer with a low impurity concentration.

  Next, the factor related to the breakdown voltage is the thickness (width) of the depletion region. As the thickness of the depletion region increases, the breakdown voltage also improves. In general, in the case of a PN junction, the PN junction interface forms a depletion layer, but this extent of depletion region expansion is insufficient. Therefore, by adopting a PIN structure in which the i-type GaN-based semiconductor layer 5 is sandwiched between the p-type GaN-based semiconductor layer 6 and the first n-type GaN-based semiconductor layer 4, the i-type GaN-based semiconductor layer 5 is depleted, The depletion region is expanded to improve the breakdown voltage.

Assuming that the film thickness of the i-type GaN-based semiconductor layer 5 is t1 and the dielectric breakdown electric field _Emax , the breakdown voltage Vi of the i-type GaN-based semiconductor layer 5 is Vi = t1 × _Emax , and the breakdown voltage Vi is proportional to the film thickness t1. To do. For example, when the film thickness t1 is 0.2 μm and E _max = 3.5 M (V / cm), Vi = 0.2 × 3.5 = 70 (V), and the entire element is 70 volts, withstand voltage Will increase. The i-type GaN-based semiconductor layer 5 means a semiconductor close to an intrinsic semiconductor as described above, but may be doped with p-type impurity Mg intentionally. This is because the i-type GaN-based semiconductor layer 5 becomes slightly n-type when grown as it is, so that this can be corrected. In that case, it is desirable that the Mg doping concentration be 1 × 10 ¹⁷ cm ⁻³ or less. This is because the depletion region does not expand when the impurity concentration increases.

Next, the impurity concentration of the p-type GaN-based semiconductor layer 6 is considered as follows. First, the lower limit of the impurity concentration N2 is considered as follows. The depletion region width (width in the stacking direction) W at the time of the dielectric breakdown electric field is determined in inverse proportion to the impurity concentration. If the depletion region extends too much vertically, reach-through occurs in which electrons flow from the second n-type GaN-based semiconductor layer 7. To avoid this, the thickness Wp of the p-type GaN-based semiconductor layer 6 is dielectric breakdown. It must be greater than or equal to the depletion region width W in the electric field (Wp ≧ W). W is W = εp × E where the dielectric breakdown electric field E _{max of} the element, q is the elementary charge, εp is the dielectric constant of the p-type GaN-based semiconductor layer 6, and N2 is the impurity concentration of the p-type GaN-based semiconductor layer 6. It is expressed by _max / (q × N2) and is inversely proportional to the impurity concentration. For example, if the impurity concentration N2 is 1 × 10 ¹⁷ cm ⁻³ , the thickness Wp of the p-type GaN-based semiconductor layer 6 needs to be 1.8 μm or more. When the impurity concentration N2 is 1 × 10 ¹⁸ cm ⁻³ , the thickness Wp of the p-type GaN-based semiconductor layer 6 is 0.18 μm or more, and when the impurity concentration N2 is 1 × 10 ¹⁹ cm ⁻³ , the thickness is increased. The thickness Wp is required to be 0.018 μm or more.

By the way, in order to reduce the channel resistance (ON resistance) at the time of driving the element, it is necessary to shorten the length (channel length) in the stacking direction of the inversion distribution region generated in the p-type GaN-based semiconductor layer 6. For this, it is necessary to reduce the thickness Wp of the p-type GaN-based semiconductor layer 6 itself. From the viewpoint of reducing the channel resistance, for example, if the thickness Wp of the p-type GaN-based semiconductor layer 6 is 0.5 μm or less, the impurity concentration N2 is 3 × 10 ¹⁷ from the calculation formula of the depletion region width W. It is desirable to be cm ⁻³ or more. If the impurity concentration of the p-type GaN-based semiconductor layer 6 is about 1 × 10 ¹⁷ cm ⁻³ , as described above, the film thickness Wp of the p-type GaN-based semiconductor layer 6 needs to be about 2 μm. It becomes.

Next, the upper limit of the impurity concentration N2 of the p-type GaN-based semiconductor layer 6 is considered as follows. When the element is driven, an inversion distribution region must be generated along the stacking direction of the p-type GaN-based semiconductor layer 6, but it is difficult to invert at a high impurity concentration as shown in the following equation. Here, when the interface potential in the inversion distribution is φ _S (inv), the Boltzmann constant is k, the absolute temperature of the semiconductor is T, the intrinsic carrier density of the semiconductor is n _i , and the elementary charge is q,
φ _S (inv) ≈2k × T × ln (N2 / n _i ) / q
The threshold voltage _Vth for generating an inversion distribution in an ideal state without an interface state is expressed as follows. When the capacitance of the insulating film having the MIS structure is C1, the dielectric constant is ε1, the capacitance of the p-type GaN-based semiconductor layer 6 is C2, and the dielectric constant is ε2,
V _th = q × φ _S (inv) × (C1 + C2) / C1
= (1+ (ε2 × Wp) / (ε1 × W _max ) × q × φs (inv)
Here, W _max is the maximum depletion layer width during inversion,
W _max = {(2εp × φs (inv)) / (q × N2)} ^1/2 .
When SiO ₂ having a thickness of 0.1 μm is used for the insulating film having the MIS structure and the thickness Wp of the p-type GaN-based semiconductor layer 6 is 0.5 μm as described above, an ideal state having no interface state. In order to suppress the threshold voltage _Vth for generating the inversion distribution to 100 volts or less, the impurity concentration N2 of the p-type GaN-based semiconductor layer 6 is set to 5 × 10 ¹⁹ cm ⁻³ or less from the above formula. Is desirable.

On the other hand, doping with Mg as an impurity is not preferable because precipitation occurs at 1 × 10 ²⁰ cm ⁻³ or more. In summary, the upper limit of the impurity concentration N2 of the p-type GaN-based semiconductor layer 6 is desirably 1 × 10 ²⁰ cm ⁻³ or less.

Finally, considering the second n-type GaN-based semiconductor layer 7 and the third n-type GaN-based semiconductor layer 3, from the point of ohmic contact with an electrode such as a source electrode or a drain electrode, and from the point of injecting a large current, It is desirable that the resistance of the semiconductor layer in contact with the electrode is low. Here, the resistance R of the second n-type GaN-based semiconductor layer 7 is as follows. The film thickness of the second n-type GaN-based semiconductor layer 7 is t2, the cross-sectional area is S, the impurity concentration is N3, and the mobility is μ.
R = t2 / (q × N3 × μ × S). In order to reduce the resistance, the impurity concentration N3 was 1 × 10 ¹⁸ cm ⁻³ and the film thickness t2 was 0.5 μm. As a result, the resistance (rate) becomes about 2.2 × 10 ⁻⁶ (Ω · cm ² ). Therefore, it is desirable that the impurity concentration of the second n-type GaN-based semiconductor layer 7 is 1 × 10 ¹⁸ cm ⁻³ or more. Furthermore, from the equation of resistance R, the smaller the film thickness t2, the smaller the resistance. Therefore, the film thickness t2 is preferably about 1 μm or less.

Further, since the third n-type GaN-based semiconductor layer 3 is also considered to be the same as the second n-type GaN-based semiconductor layer 7, it is desirable that the film thickness is 1 μm or less and the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more. . As described above, the second n-type GaN-based semiconductor layer 7 and the third n-type GaN-based semiconductor layer 3 are composed of n ⁺ -type GaN-based semiconductor layers having a high impurity concentration.

From the matters described above, when an example of the GaN-based semiconductor device configuration of FIG. 1 is shown, the substrate 1 uses any one of a sapphire substrate, a ZnO substrate, a Si substrate, a GaAs substrate, a GaN substrate, a SiC substrate, and the like. The thickness of the third n-type GaN-based semiconductor layer 3 is 1 μm and the doping concentration of impurity Si is 3 × 10 ¹⁸ cm ⁻³ . The thickness of the first n-type GaN-based semiconductor layer 4 is 5 μm and the doping concentration of impurity Si is 1 ×. 10 ¹⁷ cm ⁻³ , the thickness of the i-type GaN-based semiconductor layer 5 is 0.2 μm, the thickness of the p-type GaN-based semiconductor layer 6 is 0.5 μm, and the doping concentration of impurity Mg is 3 × 10 ¹⁹ cm ⁻³ . The film thickness of the second n-type GaN-based semiconductor layer 7 was 0.5 μm, and the doping concentration of impurity Si was 3 × 10 ¹⁸ cm ⁻³ . The case shown here is for GaN, but the same discussion can be made for AlGaN, for example. In that case, it is replaced by dielectric breakdown field E _max in its physical properties. The present invention includes such a design.

  FIG. 2 is a schematic cross-sectional view showing the structure of a first MIS type field effect transistor using the GaN-based semiconductor element structure of FIG. Therefore, the conditions such as the impurity concentration and the film thickness in the description of the GaN-based semiconductor element of FIG. 1 described above are applied, and the same applies to the second MIS type field effect transistor described later. The first MIS type field effect transistor includes a sapphire substrate 11 which is an insulating substrate, and a GaN-based semiconductor stacked portion having a PIN structure on an undoped GaN 12 grown on the sapphire substrate 11. Compared with the GaN-based semiconductor device structure in FIG. 1, the portion of the substrate 1 corresponds to the sapphire substrate 11 and the undoped GaN 12. As described above, in this embodiment, the GaN-based semiconductor stacked portion is formed on the undoped GaN 12 which is the same kind of substrate as the GaN-based semiconductor layer.

From the undoped GaN 12 side, the GaN-based semiconductor stacked portion includes an n ⁺ -type AlGaN layer 13 (drain layer), an n ⁻ -type GaN layer 14, an undoped GaN layer 15, a p-type GaN layer 16 (channel layer), and an n ⁺ -type GaN layer. 17 (source layer). When this GaN-based semiconductor laminate is compared with the GaN-based semiconductor structure of FIG. 1, the third n-type GaN-based semiconductor layer is the n ⁺ -type AlGaN layer 13 and the first n-type GaN-based semiconductor layer is the n ⁻ -type GaN layer 14. The i-type GaN-based semiconductor layer 5 corresponds to the undoped GaN layer 15, the p-type GaN-based semiconductor layer 6 corresponds to the p-type GaN layer 16, and the second n-type GaN-based semiconductor layer corresponds to the n ⁺ -type GaN layer 17.

GaN-based semiconductor lamination portion is etched from the ^{n +} -type GaN layer 17 so that the cross section is substantially rectangular ^to a depth ^{n +} -type AlGaN layer 13 is exposed. The n ⁺ -type AlGaN layer 13 has lead portions 13a that are drawn in the lateral direction along the surface of the sapphire substrate 11 from both sides of the GaN-based semiconductor stacked portion. The lead portion 13a is composed of an extension of the n ⁺ -type AlGaN layer 13, and the drain electrode 19 is formed in contact with the surface of the lead portion 13a.

On the other hand, the depth from the n ⁺ -type GaN layer 17 through the p-type GaN layer 16 and the undoped GaN layer 15 to the middle of the n ⁻ -type GaN layer 14 is near the middle in the width direction of the GaN-based semiconductor stack. V-shaped groove A is formed. The inclined side surface in the V-shaped groove A forms a wall surface extending over the n ⁻ -type GaN layer 14, the undoped GaN layer 15, the p-type GaN layer 16 and the n ⁺ -type GaN layer 17. A gate insulating film 20 is formed in a V shape in a region that covers the entire wall surface and further reaches the edge of the V-shaped groove A on the upper surface of the n ⁺ -type GaN layer 17. Further, a gate electrode 21 is formed in a V shape on the gate insulating film 20. The gate electrode 20 is provided via the gate insulating film 19, and is configured so that the gate electrode 20 and the GaN-based semiconductor layer are not in direct contact. Such a configuration is called a vertical MIS (Metal Insulator Semiconductor) structure.

A region near the wall surface of the V-shaped groove A in the p-type GaN layer 16 is a channel region (inversion distribution region) 16 a facing the gate electrode 21. In the channel region 16a, when an appropriate bias voltage is applied to the gate electrode 21, an inversion distribution that electrically connects the undoped GaN layer 15 and the n ⁺ -type GaN layer 17 is formed.

Near the interface between the undoped GaN layer 12 and the n ⁺ -type AlGaN layer 13, a two-dimensional electron gas 23 is generated in the undoped GaN layer 12 due to the piezoelectric effect. The undoped GaN layer 12 is formed on the sapphire substrate 11 by so-called selective lateral epitaxial growth (ELO), and includes a region having a high dislocation density and a region having a low dislocation density (non-dislocation region) in the horizontal direction along the substrate surface. have. The formation positions of the portions other than the lead portion 13a in FIG. 2 are selected so that a region with a low dislocation density is located immediately below. The undoped GaN layer 12 is grown on the sapphire substrate 11 so that its main surface (surface parallel to the sapphire substrate 11) is, for example, a C plane (0001).

In this case, the n ⁺ -type AlGaN layer 13, the n ⁻ -type GaN layer 14, the undoped GaN layer 15, the p-type GaN layer 16, and the n ⁺ -type GaN layer 17 stacked on the undoped GaN layer 12 by epitaxial growth are also C-planes. (0001) is laminated as the main surface. The wall surface of the V-shaped groove A is, for example, a nonpolar surface (m-plane (10-10) or a-plane (11-20)), or semipolar surface ((10-1-1), (10-1-). 3), (11-22), etc.) other than the C-plane having the maximum polarity.

The main surface of the undoped GaN layer 12 is a nonpolar surface (m-plane (10-10) or a-plane (11-20)), or semipolar surface ((10-1-1), (10-1-3)). , (11-22), etc.) may be grown on the sapphire substrate 11. In this case, accordingly, the semiconductor layer to ^{the n +} -type AlGaN layer 13～N ⁺ -type GaN layer 17 will be laminated corresponding crystal plane as the main surface.

The gate insulating film 20 can be made of, for example, nitride or oxide. More specifically, if the gate insulating film 20 is made of silicon nitride (Si _x N _y ) or silicon oxide, the charge at the interface with the p-type GaN layer 16 can be reduced, and the carrier movement in the channel region 16a. The degree can be improved. That is, channel resistance can be reduced. The gate electrode 21 is made of a conductive material such as a Ni—Au alloy, a Ni—Ti—Au alloy, a Pd—Au alloy, a Pd—Ti—Au alloy, a Pd—Pt—Au alloy, Pt, Al, or polysilicon. The

  The drain electrode 19 is preferably made of a metal containing at least Al. For example, the drain electrode 19 can be made of a Ti—Al alloy. Similarly, the source electrode 18 is preferably made of a metal containing Al, for example, a Ti—Al alloy. By configuring the drain electrode 19 and the source electrode 18 with a metal containing Al, good contact with a wiring layer (not shown) can be obtained. In addition, the drain electrode 19 and the source electrode 18 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide). .

Next, the operation of the MIS field effect transistor will be briefly described. A reverse bias voltage is applied between the source electrode 18 and the drain electrode 19 so that the drain electrode 19 side becomes positive. As a result, a reverse voltage is applied to the PIN junction composed of the n ⁻ -type GaN layer 14, the undoped GaN layer 15, and the p-type GaN layer 16. The depletion region in the undoped GaN layer 15 that is an i-type semiconductor is expanded. As a result, the source and drain are cut off, but in this state, if a predetermined voltage is applied between the source electrode 18 and the gate electrode 21 so that the gate electrode 21 side becomes positive, the p-type GaN layer 16 is not affected. A bias is applied to the gate electrode 21.

Thereby, electrons are induced in the channel region 16a of the p-type GaN layer 16 to form an inversion channel. Via this inversion channel, the undoped GaN layer 15 and the n ⁺ -type GaN layer 17 are electrically connected, and the source and drain are electrically connected. That is, when a predetermined bias is applied to the gate electrode 21, the source and the drain are conducted, and when no bias is applied to the gate electrode 21, the source and the drain are cut off. In this way, a normally-off operation is possible.

When an inversion channel is formed in the channel region 16a, electrons supplied from the source electrode 18 pass from the n ⁺ -type GaN layer 17 through the channel region 16a, the undoped GaN layer 15, the n ⁻ -type GaN layer 14, It flows into the n ⁺ -type AlGaN layer 13 and travels to the drain electrode 19 via the two-dimensional electron gas 23. By using the two-dimensional electron gas 23, the resistance due to the movement of electrons in the lateral direction can be reduced.

4A to 4E are schematic cross-sectional views showing a method of manufacturing the MIS field effect transistor of FIG. 2 in the order of steps. First, an undoped GaN layer 12 is formed on a sapphire substrate 11 by a lateral selective epitaxial growth method (see Patent Document 2). On the undoped GaN layer 12, an n ⁺ -type AlGaN layer 13, an n ⁻ -type GaN layer 14, an undoped GaN layer 15, a p-type GaN layer 16, and an n ⁺ -type GaN layer 17 are sequentially stacked by epitaxial growth. The Thus, a GaN-based semiconductor element structure is formed as shown in FIG.

  Further, a sapphire substrate 11 in which a GaN layer is previously formed by a lateral selective epitaxial growth method is used as the sapphire substrate 11, and the undoped GaN layer 12 is formed on the sapphire substrate 11 by normal epitaxial growth. It may be. Even in this case, since the undoped GaN layer 12 inherits dislocations from the underlying layer, it has a region having a high dislocation density and a region having a low dislocation density (non-dislocation region).

  When the undoped GaN layer 12 is formed, the impurity may not be intentionally doped, or epitaxial growth may be performed while doping Mg, C or Fe as a p-type dopant. This is for correcting this because when the GaN layer is epitaxially grown without adding a p-type dopant, it becomes slightly n-type. Mg, C, or Fe may be used as a p-type dopant added when epitaxially growing the p-type GaN layer 16.

For example, Si is used as an n-type dopant when epitaxially growing the n ⁺ -type AlGaN layer 13, the n ⁻ -type GaN layer 14, and the n ⁺ -type GaN layer 17. Next, as shown in FIG. 4B, mesa etching is performed from the n ⁺ -type GaN layer 17 to the middle of the n ⁺ -type AlGaN layer 13 to form the remaining GaN-based semiconductor stacked portion in a stripe shape. Thereby, on the sapphire substrate 11, a plurality of GaN-based semiconductor stacked portions are formed in a stripe shape, and a lead portion 13 a that is an extension of the n ⁺ -type AlGaN layer 13 is simultaneously formed.

  Thereafter, the drain electrode 19 and the source electrode 18 are formed, and the state shown in FIG. As shown in the figure, the drain electrode 19 is formed so as to be in contact with the surface of the lead portion 13a.

Next, as shown in FIG. 4C, a V-shaped groove A is formed in the vicinity of the intermediate portion in the width direction of each GaN-based semiconductor stacked portion formed in a stripe shape. The formation position of the V-shaped groove A is determined so that the non-dislocation region of the p-type GaN layer 16 is exposed from the side wall to form a wall surface. The V-shaped groove A is formed by dry etching (anisotropic etching) using plasma to form the V-shaped groove A from the n ⁺ -type GaN layer 17 to the n ⁻ -type GaN layer 14. Here, the damaged surface layer may be removed by performing an etching process on the wall surface of the V-shaped groove A damaged by dry etching.

For the etching process, for example, a low-damage dry etching process using a low-speed etching gas such as SiCl ₄ or B ₂ Cl ₃ can be used. In the case of wet etching treatment, it is preferable to use a basic solution such as KOH (potassium hydroxide) or NH ₄ OH (ammonia water). By reducing the damage to the wall surface of the V-shaped groove A, the crystal state of the channel region 16a can be kept good, and the interface with the gate insulating film 20 can be made a good interface. The interface state can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed.

Next, as shown in FIG. 4D, the gate insulating film 20 is formed so as to cover the wall surface of the V-shaped groove A and to cover a part of the upper surface of the n ⁺ -type GaN layer 17. For the formation of the gate insulating film 20, a PECVD (plasma enhanced chemical vapor deposition) method or the like is used. Thereafter, as shown in FIG. 4E, the gate electrode 21 is formed, and the insulating film 22 is filled between the source electrode 18 and the gate electrode 21 and between the source electrode 18 and the drain electrode 19. 2 is formed on the side surface or the surface of the GaN-based semiconductor multilayer portion so as to fill the MIS type field effect transistor. The insulating film 22 may be the same type of insulating film as the gate insulating film 20 or may be another type of insulating film. Further, the insulating film 22 may be substituted by forming the gate insulating film 20 on all surfaces other than the source electrode 18 and the drain electrode 19.

  Each of the plurality of GaN-based semiconductor stacked portions formed in a stripe shape on the sapphire substrate 11 forms a unit cell. The drain electrode 19, the gate electrode 21, and the source electrode 18 of each GaN-based semiconductor stacked portion are commonly connected at positions not shown. The drain electrode 19 can be shared by adjacent GaN-based semiconductor stacked portions.

FIG. 3 shows an MIS field effect transistor having the same structure as the first MIS field effect transistor of FIG. 2, but having a different configuration of the p-type GaN layer 16 serving as a channel layer. The same reference numerals as those in FIG. 2 indicate the same configurations. In FIG. 3, unlike FIG. 2, the region under the wall surface on the V-shaped groove A side of the p-type GaN layer 16 constitutes the altered layer 161. The altered layer 161 is a semiconductor layer having a different conduction characteristic from the p-type GaN layer 16 and is composed of any one of p ^- type, i-type, and n-type. The altered layer 161 also corresponds to a channel region that generates an inversion distribution of the p-type GaN layer 16.

  As described above, the p-type GaN layer 16 has the altered layer 161. By making the altered layer 161 a part of the channel region, inversion distribution of the channel region is likely to occur, and the on-voltage of the transistor is reduced. can do.

  As a method for forming the altered layer 161, an ECR (Electron Cyclotron Resonance) sputtering method may be used instead of the PECVD method when forming the insulating film 20 in the manufacturing process of FIG. . The altered layer 161 is formed by Ar plasma irradiation or the like in the ECR sputtering method. As described above, the method of forming the altered layer in the p-type GaN channel layer can also be applied to the second MIS field effect transistor described later.

FIG. 5 is a schematic cross-sectional view for explaining the configuration of a second MIS type field effect transistor using the GaN-based semiconductor element structure of the present invention. In this embodiment, a conductive substrate 31 is used. A GaN-based semiconductor laminate is formed on one surface of the conductive substrate 31. The GaN-based semiconductor stack includes an n ⁻ -type GaN layer 34, an undoped GaN layer 35, a p-type GaN layer 36, and an n ⁺ -type GaN layer 37.

A drain electrode 41 is formed in contact with the other surface of the conductive substrate 31. Therefore, the drain electrode 41 is electrically connected to the n ⁻ -type GaN layer 34 via the conductive substrate 31. Other configurations are the same as those of the first MIS field effect transistor described above, and the operation is also the same.

the n ^- -type GaN layer 34, since the conductive substrate 31 over its entire surface is in contact, through the channel region 36a of an undoped GaN layer 35 n ^- electrons supplied to the -type GaN layer 34, The n ⁻ -type GaN layer 34 passes through a wide area toward the conductive substrate 31 and flows into the drain electrode 41 through the conductive substrate 31. Thus, current concentration can be suppressed.

As the conductive substrate 31, a ZnO substrate, Si substrate, GaAs substrate, GaN substrate, or SiC substrate can be applied. In contrast to the GaN-based semiconductor device structure of FIG. 1, when a ZnO substrate, Si substrate, GaAs substrate, SiC substrate, or the like is used as the conductive substrate 31, it becomes a different type of substrate, and when a GaN substrate is used, the same kind is used. It becomes a substrate. Of these, it is most preferable to use a GaN substrate. When a GaN substrate is used as the conductive substrate 31, the lattice constant with the n ⁻ -type GaN layer 34 formed on the surface thereof can be matched.

In addition, for the GaN-based semiconductor stacked portion, the first n-type GaN-based semiconductor layer 4 is the n ⁻ -type GaN layer 34, the i-type GaN-based semiconductor layer 5 is the undoped GaN layer 35, and the p-type GaN-based semiconductor layer 6 is p The second n-type GaN-based semiconductor layer 7 corresponds to the n ⁺ -type GaN layer 37 in the type GaN layer 36. Here, since the conductive substrate is used, the third n-type GaN-based semiconductor layer 3 for making ohmic contact with the drain electrode is not used.

When a conductive substrate 31 having a C-plane (0001) as the main surface is used, an n ⁻ -type GaN layer 34, an undoped GaN layer 35, a p-type GaN layer 36 and an n ⁺ -type layered on the conductive substrate 31 by epitaxial growth. The GaN layer 37 is also laminated with the C surface (0001) as the main surface. The wall surface of the V-shaped groove B is, for example, a nonpolar surface (m-plane (10-10) or a-plane (11-20)) or semipolar surface ((10-1-1), (10-1). -3) and (11-22).

The main surface of the conductive substrate 31 is a nonpolar surface (m-plane (10-10) or a-plane (11-20)), or semipolar surface ((10-1-1), (10-1-3)). , (11-22), etc.) may be used. In this case, accordingly, the n ⁻ -type GaN layer 34 to the p-type GaN layer 36 are stacked with the corresponding crystal plane as the main surface.

6A to 6E are schematic cross-sectional views showing a method of manufacturing the second field effect transistor of FIG. 5 in the order of steps. An n ⁻ -type GaN layer 34, an undoped GaN layer 35, a p-type GaN layer 36, and an n ⁺ -type GaN layer 37 are epitaxially grown in this order on the conductive substrate 31, thereby producing a GaN-based semiconductor as shown in FIG. A stacked portion is formed.

  Next, as shown in FIG. 6B, after a plurality of source electrodes 34 are formed at predetermined positions, in the same way as the first field effect transistor, the source electrode 34 is formed near the middle portion of the adjacent source electrodes 34. As shown in FIG. 4, a V-shaped groove B is formed by dry etching. Note that, as described in FIG. 6C in the first method of manufacturing a field effect transistor, an etching process for removing a damaged layer on the wall surface of the V-shaped groove B may be performed. Wet etching or low damage dry etching is used. Then, as shown in FIG. 6D, after the gate insulating film 39 covering the wall surface of the V-shaped groove B is formed, the gate electrode 40 and the drain electrode 41 are formed as shown in FIG. The The drain electrode 41 is formed in contact with the lower surface of the conductive substrate 31.

  In this way, a field effect transistor having a plurality of cells can be manufactured using each V-shaped groove B as a unit cell. Adjacent cells share a source electrode 40 disposed therebetween. As in the case of the first field effect transistor described above, the gate electrode 40 and the source electrode 38 of the plurality of cells are commonly connected at positions not shown. The drain electrode 41 is formed in contact with the conductive substrate 31 and is a common electrode for all cells.

  Next, FIG. 7 shows an example of a field effect transistor having the same layer structure and the like as FIG. 5, but having a different groove shape for providing a gate insulating film and a gate electrode. The same reference numerals as those in FIG. 5 denote the same configurations. In FIG. 5, the shape of the groove B is V-shaped, but in FIG. 7, the shape of the groove C is U-shaped. In the V-shaped groove of FIG. 5, the bottom of the V-shape is sharp and sharp, and the electric field tends to concentrate and dielectric breakdown tends to occur. Therefore, the U-shape is rounded as shown in FIG. Thus, electric field concentration is prevented. In addition, although it is good also as another shape of U shape, it is desirable to set it as the shape which gave roundness. The U-shaped groove can also be applied to the first field effect transistor shown in FIGS.

It is a figure which shows an example of the cross-sectional structure of the GaN-type semiconductor element of this invention. It is a figure which shows the cross-sectional structure which applied the GaN-type semiconductor element of this invention to 1st MIS type FET. It is a figure which shows that the area | region where a conduction characteristic differs is formed in a part of p-type GaN layer of 1st MIS type FET. It is a figure which shows the manufacturing method of 1st MIS type FET. It is a figure which shows the cross-sectional structure which applied the GaN-type semiconductor element of this invention to 2nd MIS type FET. It is a figure which shows the manufacturing method of 2nd MIS type FET. It is a figure which shows an example of the cross-section of MIS type | mold FET by which the groove | channel shape for forming a gate electrode was U shape.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 3 Third n-type GaN-based semiconductor layer 4 First n-type GaN-based semiconductor layer 5 i-type GaN-based semiconductor layer 6 p-type GaN-based semiconductor layer 7 Second n-type GaN-based semiconductor layer 7

Claims (11)

A GaN-based semiconductor device comprising, on a substrate, at least a first n-type or i-type GaN-based semiconductor layer, a GaN-based semiconductor layer containing p-type impurities, and a second n-type or i-type GaN-based semiconductor layer in that order. There,
The impurity concentration of the p-type GaN-based semiconductor layer containing the p-type impurity is 1 × 10 ²⁰ cm ⁻³ or less, and the impurity concentration of the first n-type or i-type GaN-based semiconductor layer is 1 × 10 ¹⁸ cm. A GaN-based semiconductor element characterized by being ^-3 or less. Between the first n-type or i-type GaN-based semiconductor layer and the GaN-based semiconductor layer containing a p-type impurity, an i-type GaN-based semiconductor layer having an impurity Mg concentration of 1 × 10 ¹⁸ cm ⁻³ or less is provided. The GaN-based semiconductor device according to claim 1, wherein the GaN-based semiconductor device is formed.   A third n-type GaN-based semiconductor layer having an impurity concentration higher than that of the first n-type or i-type GaN-based semiconductor layer is formed between the substrate and the first n-type or i-type GaN-based semiconductor layer. The GaN-based semiconductor element according to claim 1, wherein the GaN-based semiconductor element is formed.   4. The GaN-based semiconductor device according to claim 1, wherein a thickness of the GaN-based semiconductor layer containing the p-type impurity is 2 μm or less. 5.  5. The GaN-based semiconductor element according to claim 1, wherein the impurity of the GaN-based semiconductor layer containing the p-type impurity is Mg.   6. The GaN-based semiconductor device according to claim 1, wherein the impurity of the first n-type or i-type GaN-based semiconductor layer is Si or O. 6.   7. The impurity concentration of the first n-type or i-type GaN-based semiconductor layer is lower than the second n-type or i-type GaN-based semiconductor layer. 2. A GaN-based semiconductor device according to item 1.   8. The GaN-based semiconductor element according to claim 1, wherein a thickness of the second n-type or i-type GaN-based semiconductor layer is 1 μm or less. 9. The GaN-based semiconductor device according to claim 3, wherein an impurity concentration of the third n-type GaN-based semiconductor layer is 1 × 10 ¹⁸ cm ⁻³ or more.   10. The GaN-based semiconductor element according to claim 1, wherein a gate insulating film is formed in contact with a wall surface exposed by processing of the GaN-based semiconductor layer containing the p-type impurity.   11. The GaN-based semiconductor device according to claim 10, wherein the region in the vicinity of the wall surface is made of a semiconductor having a different conduction characteristic from the GaN-based semiconductor layer containing the p-type impurity.

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