JP4993673B2 - MIS field effect transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III-V nitride semiconductor MIS-type field effect transistor suitable for application to a power device. <P>SOLUTION: In the field effect transistor, a nitride semiconductor lamination structure section 2 is arranged on a sapphire substrate 41. The nitride semiconductor lamination structure section 2 comprises: a superlattice n-type layer 5; a p-type GaN layer 6 laminated on the superlattice n-type layer 5; and a superlattice n-type layer 7 laminated on the p-type GaN layer 6. A trench 16 having a V-shaped section is formed at the nitride compound semiconductor lamination structure section 2, and the sidewall of the trench 16 forms a wall surface 17 spread over the superlattice n-type layer 5, the p-type GaN layer 6, and the superlattice n-type layer 7. A gate insulation film is formed on the wall surface 17, and further a gate electrode 20 is formed so that it opposes the wall surface 17 while sandwiching the gate insulation film 19. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a MIS field effect transistor using a group III-V nitride semiconductor and a method for manufacturing the same.

Conventionally, power devices using silicon semiconductors are used for power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of a GaN device having features such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and small on-resistance has been studied (Non-Patent Document 1 below).
JP 2004-260140 A JP 2000-912523 A Satoshi Okubo, “GaN is behind the evolution of equipment, not just shining”, June 5, 2006, Nikkei Electronics, p. 51-60

However, all the GaN devices proposed so far have a lateral structure in which the source, gate and drain are arranged along the substrate surface, and are not necessarily suitable for power devices that require a large current. , Pressure resistance is insufficient. Furthermore, there is a problem that it is not always easy to realize a normally-off operation that can be said to be essential in a power device.
Accordingly, an object of the present invention is to provide a group III-V nitride semiconductor MIS field effect transistor suitable for application to a power device and a method for manufacturing the same.

  In order to achieve the above object, the invention according to claim 1 is the first conductivity type first group III-V nitride semiconductor layer (5), the second layer laminated on the first group III-V nitride semiconductor layer. Conductive type second III-V nitride semiconductor layer (6) and first conductive type third group III-V nitride semiconductor layer (7) laminated on the second group III-V nitride semiconductor layer A nitride semiconductor multilayer structure (2), wherein at least one of the first and third group III-V nitride semiconductor layers is a superlattice semiconductor layer made of nitrides having different compositions; A gate formed so as to straddle these first, second and third group III-V nitride semiconductor layers on a wall surface (17) formed straddling the first, second and third group III-V nitride semiconductor layers An insulating film (19, 50) and the second group III-V nitride semiconductor layer (more Preferably, a gate electrode (20) made of a conductive material so as to face the first to third III-V group nitride semiconductor layers), and the first III-V group nitride semiconductor layer And a source electrode (25) electrically connected to the third III-V nitride semiconductor layer. The MIS field effect transistor includes a drain electrode (15) electrically connected to the third III-V nitride semiconductor layer. The alphanumeric characters in parentheses indicate corresponding components in the embodiments described later. The same applies hereinafter.

  According to this configuration, the first III-V nitride semiconductor layer, the second III-V nitride semiconductor layer, and the third III-V nitride semiconductor layer are stacked to form an NPN structure or PNP structure nitride semiconductor. A laminated structure is formed, and a gate insulating film is disposed on a wall surface formed across the first to third group III-V nitride semiconductor layers. A portion of the second group III-V nitride semiconductor layer that forms the wall surface forms a channel region with the gate insulating film interposed therebetween, and a gate electrode faces the channel region. Furthermore, a drain electrode is provided so as to be electrically connected to the first III-V nitride semiconductor layer, and a source electrode is provided so as to be electrically connected to the third III-V nitride semiconductor layer. Yes. Thus, a vertical MIS (Metal Insulator Semiconductor) type field effect transistor is formed.

  Thus, by having the basic structure as a vertical MIS field effect transistor, a normally-off operation, that is, an operation in which the source and drain are turned off when no bias is applied to the gate electrode is easily realized. can do. Furthermore, since it has a vertical structure, a large current can be flowed easily and a high breakdown voltage can be secured, so that an effective power device can be provided. Of course, the field effect transistor is composed of a III-V nitride semiconductor layer, so that it has a higher breakdown voltage, higher temperature operation, higher current density, higher speed switching and lower on-resistance than a device using a silicon semiconductor. You can enjoy the features. In particular, since a high voltage and low loss operation is possible, a good power device can be realized.

  Moreover, in this embodiment, since at least one of the first and third group III-V nitride semiconductor layers is composed of a superlattice semiconductor layer made of nitrides having different compositions, the superlattice semiconductor layer The on-resistance in the lateral direction can be reduced in the group III-V nitride semiconductor layer configured as follows. Furthermore, since current can be diffused in the lateral direction by the superlattice semiconductor layer, current concentration can be suppressed. This can further contribute to the reduction of on-resistance.

The III-V group nitride semiconductor is a group III-V semiconductor in which nitrogen is used as a group V element. Typical examples include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). It is an example. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).
For example, a first III-V nitride semiconductor layer and a third III-V nitride semiconductor layer are N-type, and a second III-V nitride semiconductor layer is P-type. The operation when configured will be described. In this case, a bias with a positive drain side is applied between the source and the drain. At this time, a reverse voltage is applied to the PN junction at the interface between the first and second group III-V nitride semiconductor layers, so that the source and drain are cut off. In this state, when a bias voltage that is positive with respect to the second group III-V nitride semiconductor layer is applied to the gate electrode, a region near the wall surface facing the gate electrode in the second group III-V nitride semiconductor layer Electrons are induced in the (channel region), and an inversion channel is formed. The first and third group III-V nitride semiconductor layers conduct through the inversion channel, and therefore, the source and the drain conduct. In this way, the source-drain conducts when an appropriate bias is applied to the gate electrode, while the source-drain is cut off when no bias is applied to the gate electrode. That is, a normally-off operation is realized. When the first and third group III-V nitride semiconductor layers are P-type and the second group III-V nitride semiconductor layer is N-type to form a P-channel field effect transistor, the polarity of the bias voltage is reversed. However, the operation is similar to that described above.

  The invention according to claim 2 is the MIS field effect transistor according to claim 1, wherein the superlattice semiconductor layer is made of a superlattice layer of AlGaN having different Al composition (Al composition is 0% to 100%). For example, a superlattice semiconductor layer can be composed of an AlGaN superlattice layer and a GaN superlattice layer. The film thickness of the superlattice layer is preferably 10 to 100 mm as described in claim 3.

  According to a fourth aspect of the present invention, there is provided a trench (16) which penetrates the second group III-V nitride semiconductor layer from the third group III-V nitride semiconductor layer and reaches the first group III-V nitride semiconductor layer. The MIS field effect transistor according to any one of claims 1 to 3, wherein a sidewall of the trench forms the wall surface. With this configuration, by forming a trench in the nitride semiconductor multilayer structure, the wall surface of the second III-V group nitride semiconductor layer that provides the channel region can be exposed.

The trench may be a V-shaped trench, a U-shaped trench, or a rectangular trench. Further, it may be a V-shaped trench (inverted trapezoidal groove) having a flat surface at the bottom, or a trench having a trapezoidal cross-sectional shape.
According to a fifth aspect of the present invention, the source electrode is provided so as to be in contact with both the second III-V group nitride semiconductor layer and the third III-V group nitride semiconductor layer. 5. An MIS field effect transistor according to any one of 4 above.

  According to this configuration, since the source electrode is in contact with both the second and third group III-V nitride semiconductor layers, the connection of the source electrode to the third group III-V nitride semiconductor layer is ensured at the same time. The second group III-V nitride semiconductor layer can be fixed at the same potential as the source. Therefore, by applying a bias to the gate electrode with reference to the source potential, an inversion channel can be formed in a portion (channel region) of the second III-V nitride semiconductor layer facing the wall surface.

For example, a trench (24) for burying a source electrode may be formed at a position different from the wall surface of the nitride semiconductor multilayer structure portion, and the source electrode may be buried in this trench. In this case, the source electrode trench may be formed to a depth reaching the second III-V nitride semiconductor layer from the third III-V nitride semiconductor layer.
According to a sixth aspect of the present invention, the nitride semiconductor multilayer structure is disposed on the opposite side of the second III-V nitride semiconductor layer with respect to the first III-V nitride semiconductor layer (contact arrangement). The third conductivity type 4III-V nitride semiconductor layer (9) of the first conductivity type may be further included, and the drain electrode is connected to the fourth III-V nitride semiconductor layer. It is a MIS field effect transistor as described in any one of 1-5.

  According to this configuration, since the drain electrode is connected to the fourth group III-V nitride semiconductor layer formed in contact with the first group III-V nitride semiconductor layer, the fourth group III-V nitride semiconductor is provided. The drain electrode can be electrically connected to the first III-V nitride semiconductor layer through the layer. Even when the nitride semiconductor multilayer structure is provided on the insulating substrate, the electrical connection between the drain electrode and the first group III-V nitride semiconductor layer is made with the group III-V nitride. This can be achieved via the semiconductor layer.

According to the seventh aspect of the present invention, the nitride semiconductor multilayer structure is disposed on a side opposite to the second III-V nitride semiconductor layer with respect to the first III-V nitride semiconductor layer (contact arrangement). The MIS type field effect transistor according to any one of claims 1 to 5, further comprising a first group III-V nitride semiconductor layer (9) of the first conductivity type containing Al. is there.
According to this configuration, the fourth group III-V nitride semiconductor layer having the same conductivity type as the first group III-V nitride semiconductor is provided so as to form a stacked relationship with the first group III-V nitride semiconductor layer. Yes. The fourth group III-V nitride semiconductor layer contributes to an improvement in breakdown voltage and a reduction in resistance.

The invention according to claim 8 is the MIS field effect transistor according to claim 7, wherein the drain electrode is connected (contacted) to the fourth group III-V nitride semiconductor layer.
With this configuration, the drain electrode can be electrically connected to the first group III-V nitride semiconductor layer through the fourth group III-V nitride semiconductor layer. When the nitride semiconductor multilayer structure is disposed on the substrate, the drain electrode can be connected using the group III-V nitride semiconductor layer even when the substrate is an insulating substrate. .

The intrinsic structure of the nitride semiconductor multilayer structure is disposed on the opposite side of the fourth III-V nitride semiconductor layer from the first III-V nitride semiconductor layer (contact arrangement is preferred). It is preferable to further include a fifth III-V nitride semiconductor layer (8) which is (undoped).
In this configuration, the fourth group III-V nitride semiconductor layer and the fifth group III-V nitride semiconductor layer made of an intrinsic semiconductor layer are arranged in a stacked relationship. In the vicinity of the boundary between the fourth and fifth III-V nitride semiconductor layers, a high concentration two-dimensional electron gas (28) is formed in the fifth III-V nitride semiconductor layer. By utilizing this two-dimensional electron gas, the resistance value from the first III-V nitride semiconductor layer to the drain electrode can be reduced, and the resistance can be further reduced. In particular, for example, even in the case where the drain is led out in the lateral direction of the nitride semiconductor multilayer structure using the fourth III-V nitride semiconductor layer, the wide range of the first III-V nitride semiconductor layer is used. The current flowing between the two-dimensional electron gas can be dispersed. As a result, current concentration can be suppressed, and the resistance of the device can be reduced.

  The fifth III-V nitride semiconductor layer is preferably a layer doped with Mg, C, or Fe. Nitride semiconductors tend to be slightly N-type during the formation (epitaxial growth), and in order to counteract this, doping with Mg, C, or Fe as a P-type dopant allows group III-V nitrides to be formed. The semiconductor layer can be an intrinsic semiconductor layer.

The invention according to claim 9 is the MIS field effect transistor according to claim 1, wherein the nitride semiconductor multilayer structure is formed (grown) on the substrate (1, 41). is there.
The invention according to claim 10 is the MIS field effect transistor according to claim 9, wherein the substrate is an insulating substrate (1). A typical insulating substrate is a sapphire (Al ₂ O ₃ ) substrate. Even in the case of using such an insulating substrate, the first III-V can be configured by adopting the configuration as in claim 6 or 8 or by directly contacting the drain electrode with the first III-V nitride semiconductor layer. The drain electrode can be electrically connected to the group V nitride semiconductor layer.

The invention according to claim 11 is the MIS field effect transistor according to claim 9, wherein the substrate is an Al ₂ O ₃ substrate, a ZnO substrate, a Si substrate, a GaAs substrate, a GaN substrate, or a SiC substrate. From the standpoint of lattice constant matching with the nitride semiconductor multilayer structure, a GaN substrate is the best, and a nitride semiconductor layer with few dislocations can be formed by using the GaN substrate. Also, from the viewpoint of cost reduction, it is preferable to use an Al ₂ O ₃ substrate (sapphire substrate), and when importance is placed on heat dissipation (thermal conductivity), an SiC substrate may be used.

The invention according to claim 12 is a substrate in which the substrate has a region having a high dislocation density and a region having a low dislocation density in a direction along the substrate surface, and the gate electrode is grown from a region having a low dislocation density. The MIS field effect transistor according to any one of claims 9 to 11, wherein the MIS field effect transistor is disposed so as to face the region.
For example, a substrate having an epitaxially grown layer formed by lateral selective epitaxial growth (ELO: epitaxial lateral overgrowth) as described in Patent Document 2 includes a region having a low dislocation density (no dislocation). Region) and a region having a high dislocation density. In this case, if the channel region (region facing the wall surface) of the second III-V nitride semiconductor layer is located in a region grown from a region having a low dislocation density, the dislocation density in the channel region is low. Therefore, leakage current can be suppressed.

According to a thirteenth aspect of the present invention, the nitride semiconductor multilayer structure is disposed on one surface of the conductive substrate (41), and the drain electrode is connected (contacted) to the other surface of the conductive substrate. The MIS field effect transistor according to any one of claims 1 to 5.
In this configuration, the nitride semiconductor multilayer structure is disposed on one surface of the conductive substrate, and the drain electrode is connected to the other surface of the conductive substrate. It is electrically connected to the physical semiconductor layer. Thereby, since current flows through a wide range of the nitride semiconductor multilayer structure portion, current confinement can be suppressed and high breakdown voltage can be achieved.

As the conductive substrate, a ZnO substrate, Si substrate, GaAs substrate, GaN substrate, or SiC substrate can be applied. Especially, since the lattice constant of the GaN substrate matches that of the nitride semiconductor multilayer structure, the crystallinity of the nitride semiconductor multilayer structure can be improved by using the GaN substrate.
The MIS field effect transistor according to any one of claims 1 to 5, wherein the drain electrode is connected (contacted) to the first III-V nitride semiconductor layer. It is. With this configuration, the drain electrode can be electrically connected to the first III-V nitride semiconductor layer.

The invention according to claim 15 is any one of claims 1 to 5, wherein the drain electrode is formed in contact with the surface opposite to the gate electrode with respect to the nitride semiconductor multilayer structure portion. The MIS field effect transistor according to one item.
According to this configuration, the drain electrode is formed in contact with the surface opposite to the gate electrode with respect to the nitride semiconductor multilayer structure portion, and thus the substrate can be omitted. More specifically, the drain electrode may be formed in contact with the surface of the first III-V nitride semiconductor layer opposite to the second III-V nitride semiconductor layer. Good. With such a configuration, for example, a MIS field effect transistor having a thickness of 30 μm or less can be realized.

According to a sixteenth aspect of the present invention, the first, second and third group III-V nitride semiconductor layers may be stacked with a C plane (0001) as a main surface.
In addition, as described in claim 17, the first, second, and third group III-V nitride semiconductor layers have a nonpolar plane (m-plane (10-10) or a-plane (11-20)). ) Or a semipolar surface (such as (10-1-1), (10-1-3), (11-22)) may be laminated.

Furthermore, as described in claim 18, the wall surfaces of the first, second, and third group III-V nitride semiconductor layers on which the gate insulating film is formed are nonpolar surfaces (m-plane (10 -10) or a-plane (11-20)) or a semipolar plane ((10-1-1), (10-1-3), (11-22), etc.).
In addition, the gate insulating film may be a nitride or an oxide. In particular, it is preferable that the gate insulating film is made of silicon nitride or silicon oxide.

  The gate insulating film may include a group III-V nitride intrinsic semiconductor gate layer (51: regrowth layer) containing Al (preferably not containing In). According to this configuration, the III-V nitride intrinsic semiconductor gate layer containing Al forms a good interface with the wall surfaces of the first to third III-V nitride semiconductor layers. Therefore, unlike the case where an insulating film such as an oxide film is formed in contact with the wall surfaces of the first to third III-V nitride semiconductor layers, the carrier mobility in the channel region is reduced due to the unstable interface. Or problems such as a decrease in device reliability can be suppressed or avoided.

  The gate insulating film may include another insulating film (52) stacked on the III-V nitride intrinsic semiconductor gate layer containing Al. In this case, the another insulating film is preferably laminated on the opposite side of the wall surface with respect to the III-V nitride intrinsic semiconductor gate layer. With this configuration, the gate leakage current can be reduced. The III-V nitride intrinsic semiconductor gate layer containing Al may have insufficient insulation when the Al composition is small. In such a case, it is preferable to compensate for the lack of insulation of the III-V nitride intrinsic semiconductor gate layer containing Al by another insulating film.

The Al composition in the III-V nitride intrinsic semiconductor gate layer containing Al is preferably 50 to 100 wt% (50 wt% or more and less than 100 wt%). Thereby, necessary insulation can be ensured.
In addition, as described in claim 21, the conductive material constituting the gate electrode is preferably made of a single metal or an alloy containing at least one of Al, Au, and Pt. . According to a twenty-second aspect of the present invention, the conductive material constituting the gate electrode may contain polysilicon.

  On the other hand, as described in claim 23, the source electrode or the drain electrode is preferably made of a material containing at least Al. More specifically, as described in claim 24, the source electrode or the drain electrode is preferably made of an alloy material containing at least Ti and Al. Thereby, the contact for wiring can be satisfactorily taken with respect to the source electrode or the drain electrode. In addition, as described in claim 25, the material constituting the source electrode or drain electrode may contain Mo or Mo compound, Ti or Ti compound, or W or W compound.

  According to a twenty-sixth aspect of the present invention, there is provided a step of forming a first group III-V nitride semiconductor layer (5) of the first conductivity type on a substrate (1, 41, 45), and the first group III-V nitride semiconductor. A step of forming a second conductivity type second III-V nitride semiconductor layer (6) on the layer, and a step of forming the first conductivity type second III-V nitride semiconductor layer on the second III-V nitride semiconductor layer. A step of laminating and forming a 3III-V nitride semiconductor layer (7), and a wall surface forming step of forming a wall surface (17) straddling the first, second and third III-V nitride semiconductor layers, A gate insulating film forming step of forming a gate insulating film on the wall surface so as to straddle the first, second and third group III-V nitride semiconductor layers; and the second III with the gate insulating film interposed therebetween Forming a gate electrode (20) made of a conductive material so as to face the -V group nitride semiconductor layer, and the first II Forming a drain electrode (15) so as to be electrically connected to the group I-V nitride semiconductor layer; and a source electrode (10) so as to be electrically connected to the third group III-V nitride semiconductor layer. 25), and at least one of the step of forming the first group III-V nitride semiconductor layer and the step of forming the third group III-V nitride semiconductor layer has a different composition. A method for manufacturing a MIS field effect transistor, which includes a step of forming a superlattice semiconductor layer made of nitride. By this method, the MIS field effect transistor having the structure described in claim 1 can be manufactured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a MIS field effect transistor according to a first embodiment of the present invention. The field effect transistor includes a sapphire substrate 1 that is an insulating substrate, and a nitride semiconductor multilayer structure portion 2 made of a GaN compound semiconductor layer grown on the sapphire substrate 1. The nitride semiconductor multilayer structure unit 2 includes a superlattice N-type layer 5 (drain layer), a P-type GaN layer 6 laminated on the superlattice N-type layer 5, and a P-type GaN layer 6 on the P-type GaN layer 6. The superlattice N-type layer 7 (source layer) is provided. Further, the nitride semiconductor multilayer structure portion 2 includes an intrinsic (undoped) GaN layer 8 formed in contact with the sapphire substrate 1 and an N-type AlGaN layer 9 laminated on the intrinsic GaN layer 8. The superlattice N-type layer 5 is laminated on the N-type AlGaN layer 9.

  The superlattice N-type layers 5 and 7 are N-type III-V nitride semiconductor layers and are superlattice semiconductor layers composed of superlattice layers made of nitrides having different compositions. Specifically, it is composed of AlGaN superlattice layers having different Al compositions. More specifically, it is composed of an AlGaN superlattice layer and a GaN superlattice layer. The film thickness of each superlattice layer is preferably in the range of 10 to 100 mm.

  The nitride semiconductor multilayer structure portion 2 is etched from the superlattice N-type layer 7 to a depth at which the N-type AlGaN layer 9 is exposed so that the cross section is substantially rectangular. The N-type AlGaN layer 9 has lead portions 10 that are drawn from both sides of the nitride semiconductor multilayer structure portion 2 in the lateral direction along the surface of the sapphire substrate 1. A drain electrode 15 is formed in contact with the surface of the lead portion 10. That is, the lead-out portion 10 drawn out from the nitride semiconductor multilayer structure portion 2 in the lateral direction is formed by an extension of the N-type AlGaN layer 9 in this embodiment.

  On the other hand, a trench 16 having a depth extending from the superlattice N-type layer 7 through the P-type GaN layer 6 to the middle part of the superlattice N-type layer 5 near the middle in the width direction of the nitride semiconductor multilayer structure portion 2. Is formed. In this embodiment, the trench 16 is formed in a V-shaped cross section, and the inclined side surface thereof extends over the wall surface 17 straddling the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7. Forming. A gate insulating film 19 is formed in a region covering the entire surface of the wall surface 17 and reaching the edge of the trench 16 on the upper surface of the superlattice N-type layer 7. Further, a gate electrode 20 is formed on the gate insulating film 19. That is, the gate electrode 20 faces the wall surface 17, that is, the superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 with the gate insulating film 19 interposed therebetween. The upper surface of the layer 7 is formed to extend to the vicinity of the edge of the trench 16.

A region near the wall surface 17 in the P-type GaN layer 6 is a channel region 21 that faces the gate electrode 20. In this channel region 21, an inversion channel that electrically connects the superlattice N-type layers 5 and 7 is formed by applying an appropriate bias voltage to the gate electrode 20.
In the nitride semiconductor multilayer structure portion 2, a source electrode trench 24 is formed at a location different from the trench 16. In this embodiment, a pair of source electrode trenches 24 are formed on both sides of the trench 16. The source electrode trench 24 is formed to a depth from the surface of the superlattice N-type layer 7 to the P-type GaN layer 6. A source electrode 25 is embedded in the source electrode trench 24. Therefore, the source electrode 25 is electrically connected to both the superlattice N-type layer 7 and the P-type GaN layer 6.

Near the interface between the intrinsic GaN layer 8 and the N-type AlGaN layer 9, a two-dimensional electron gas 28 is generated in the intrinsic GaN layer 8 due to the piezoelectric effect.
The intrinsic GaN layer 8 is formed on the sapphire substrate 1 by so-called selective lateral epitaxial growth (ELO), and includes a region having a high dislocation density and a region having a low dislocation density (non-dislocation region) in the horizontal direction along the substrate surface. have. The trench 16 is formed at a position where a region having a low dislocation density (non-dislocation region) is located immediately below the channel region 21. Intrinsic GaN layer 8 is grown on sapphire substrate 1 such that its main surface (surface parallel to sapphire substrate 1) is, for example, a C-plane (0001). In this case, the N-type AlGaN layer 9, the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7 that are stacked on the intrinsic GaN layer 8 by epitaxial growth still have the C plane (0001) as the main surface. Will be laminated. Further, the wall surface of the trench 16 having a V-shaped cross section is, for example, a nonpolar surface (m-plane (10-10) or a-plane (11-20)), or semipolar surface ((10-1-1), (10- 1-3), (11-22), and the like.

  The intrinsic GaN layer 8 has a nonpolar surface (m-plane (10-10) or a-plane (11-20)) or semipolar surface ((10-1-1), (10-1-3)). , (11-22), etc.) may be grown on the sapphire substrate 1. In this case, the N-type AlGaN layer 9, the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7 are laminated with the corresponding crystal plane as the main surface accordingly. .

The gate insulating film 19 can be made of, for example, nitride or oxide. More specifically, if the gate insulating film is made of silicon nitride (Si _x N _y ) or silicon oxide, the charge at the interface with the P-type GaN layer 6 can be reduced, and the carrier mobility in the channel region 21 can be reduced. Can be improved. That is, channel resistance can be reduced.
The gate electrode 20 is made of a conductive material such as a Ni—Au alloy, a Ni—Ti—Au alloy, a Pd—Au alloy, a Pd—Ti—Au alloy, a Pd—Pt—Au alloy, Pt, Al, or polysilicon. The

  The drain electrode 15 is preferably made of a metal containing at least Al. For example, the drain electrode 15 can be made of a Ti—Al alloy. Similarly, the source electrode 25 is preferably made of a metal containing Al, for example, a Ti—Al alloy. By forming the drain electrode 15 and the source electrode 25 with a metal containing Al, good contact with a wiring layer (not shown) can be obtained. In addition, the drain electrode 15 and the source electrode 25 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide). .

Next, the operation of the MIS field effect transistor will be described.
A bias voltage that is positive on the drain electrode 15 side is applied between the source electrode 25 and the drain electrode 15. As a result, a reverse voltage is applied to the PN junction at the interface between the superlattice N-type layer 5 and the P-type GaN layer 6, and as a result, between the superlattice N-type layers 5 and 7, that is, between the source and drain. Is cut off. In this state, when a predetermined voltage that is positive on the gate electrode 20 side is applied between the source electrode 25 and the gate electrode 20, a bias for the P-type GaN layer 6 is applied to the gate electrode 20. As a result, electrons are induced in the channel region 21 of the P-type GaN layer 6 to form an inversion channel. The superlattice N-type layers 5 and 7 conduct through the inversion channel. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 20, the source and the drain are conducted, and when no bias is applied to the gate electrode 20, the source and the drain are cut off. In this way, a normally-off operation is possible.

  When an inversion channel is formed in the channel region 21, electrons supplied from the source electrode 25 flow from the superlattice N-type layer 7 through the channel region 21 into the superlattice N-type layer 5, and are two-dimensional electrons. It goes to the drain electrode 15 via the gas 28. Since the two-dimensional electron gas 28 is widely distributed at the interface between the intrinsic GaN layer 8 and the N-type AlGaN layer 9, the electrons flowing from the channel region 21 into the superlattice N-type layer 5 are superlattice N-type layer 5. Flows into the two-dimensional electron gas 28 through a wide area. In this manner, the current concentration can be reduced and the on-resistance can be suppressed despite the structure in which the drain electrode 15 is taken out in the lateral direction of the nitride semiconductor multilayer structure portion 2.

The superlattice N-type layer 7 as the source layer itself has a low resistance, and the superlattice structure promotes current diffusion in the lateral direction. Therefore, the resistance from the source electrode 25 to the channel region 21 can be suppressed.
Further, the superlattice N-type layer 5 as the drain layer itself has a low resistance, and the superlattice structure promotes current diffusion in the lateral direction. Therefore, since electrons from the channel region 21 can be diffused over a wide range, current concentration can be suppressed and a reduction in resistance can be achieved.

Thus, the on-resistance as a whole can be kept low by the action of the superlattice N-type layers 5 and 7.
Of course, only one of the superlattice N-type layers 5 and 7 sandwiching the P-type GaN layer 6 may be used as a normal N-type III-V group nitride semiconductor layer (such as an N-type GaN layer or an N-type AlGaN layer). An on-resistance reduction effect can be obtained.

2A to 2E are schematic cross-sectional views showing a method of manufacturing the MIS field effect transistor of FIG. 1 in the order of steps.
First, an intrinsic GaN layer 8 is formed on the sapphire substrate 1 by a lateral selective epitaxial growth method (see Patent Document 2). On the intrinsic GaN layer 8, an N-type AlGaN layer 9, a superlattice N-type layer 5, a P-type GaN layer 6, and a superlattice N-type layer 7 are grown in this order by epitaxial growth. Thus, the nitride semiconductor multilayer structure portion 2 is formed on the sapphire substrate 1 (see FIG. 2A). Superlattice N-type layers 5 and 7 can be formed, for example, by molecular beam epitaxy.

  The sapphire substrate 1 formed with the intrinsic GaN layer 8 by lateral selective epitaxial growth is regarded as a “substrate”, and the group III-V nitride semiconductor layer stacked above the intrinsic GaN layer 8 is “nitrided”. It may be considered that the “physical semiconductor multilayer structure” is configured. Further, a sapphire substrate (bare substrate) previously formed with a GaN layer by lateral selective epitaxial growth is used as the sapphire substrate 1, and the intrinsic GaN layer 8 is formed on the sapphire substrate 1 by normal epitaxial growth. It may be. Even in this case, the intrinsic GaN layer 8 inherits dislocations from the underlying layer, and thus has a region having a high dislocation density and a region having a low dislocation density (dislocation-free region).

  When the intrinsic GaN layer 8 is formed, the impurity may not be intentionally doped, or epitaxial growth may be performed while doping Mg, C, or Fe as a P-type dopant. This is for correcting this because when the GaN layer is epitaxially grown without adding a P-type dopant, it becomes slightly N-type. Mg, C, or Fe may be used as a P-type dopant added when the P-type GaN layer 6 is epitaxially grown.

For example, Si may be used as an N-type dopant when epitaxially growing the N-type AlGaN layer 9 and the superlattice N-type layers 5 and 7.
After the nitride semiconductor multilayer structure portion 2 is formed, the nitride semiconductor multilayer structure portion 2 is etched in stripes as shown in FIG. 2B. That is, a groove 30 having a rectangular cross section is formed by etching from the superlattice N-type layer 7 through the P-type GaN layer 6 and the superlattice N-type layer 5 to the middle layer thickness of the N-type AlGaN layer 9. . Thereby, on the sapphire substrate 1, a plurality of nitride semiconductor multilayer structures 2 are shaped into stripes, and a lead portion 10 made of an extension of the superlattice N-type layer 9 is simultaneously formed. A pair of source electrode trenches 24 is formed along both sides of each shaped nitride semiconductor multilayer structure portion 2. As described above, the source electrode trench 24 is a groove having a rectangular cross section extending from the superlattice N-type layer 7 to the P-type GaN layer 6.

The source electrode trench 24 can be formed, for example, by dry etching (anisotropic etching) using plasma. Furthermore, after that, a wet etching process for improving the inner wall surface of the trench damaged by the dry etching may be performed as necessary. Thereby, the contact resistance of the source electrode 25 can be reduced. For wet etching, it is preferable to use a basic solution such as KOH (potassium hydroxide) or NH ₄ OH (ammonia water).

In this way, after the source electrode trench 24 is formed, the drain electrode 15 and the source electrode 25 are formed, and the state shown in FIG. 2B is obtained. The drain electrode 15 is formed so as to be in contact with the bottom surface of the groove 30, that is, the surface of the lead portion 10 (extension portion of the N-type AlGaN layer 9).
Next, as shown in FIG. 2C, a trench 16 having a V-shaped cross section is formed along the longitudinal direction of the nitride semiconductor multilayer structure portion 2 in the vicinity of the intermediate portion in the width direction of each nitride semiconductor multilayer structure portion 2. . The formation position of the trench 16 is determined such that the non-dislocation region of the P-type GaN layer 6 is exposed from the side wall to form the wall surface 17. The trench 16 is formed by dry etching (anisotropic etching) using plasma from the superlattice N-type layer 7 through the P-type GaN layer 6 to the superlattice N-type layer 5. And a wet etching process for improving an exposed surface damaged by dry etching. That is, by performing wet etching on the wall surface 17 damaged by dry etching, a new wall surface 17 from which the damaged surface layer has been removed appears.

For wet etching, it is preferable to use a basic solution such as KOH (potassium hydroxide) or NH ₄ OH (ammonia water). Thereby, the wall surface 17 with little damage can be obtained. By reducing the damage to the wall surface 17, the crystal state of the channel region 21 can be kept good, and the interface between the wall surface 17 and the gate insulating film 19 can be a good interface. The level can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed.

Next, as shown in FIG. 2D, a gate insulating film 19 that covers the wall surface 17 of the V-shaped trench 16 and covers the edge of the trench 16 is formed. For the formation of the gate insulating film 19, it is preferable to apply an ECR (Electron Cyclotron Resonance) sputtering method.
Thereafter, as shown in FIG. 2E, the gate electrode 20 is formed, whereby the MIS field effect transistor having the structure shown in FIG. 1 can be obtained.

  The plurality of nitride semiconductor multilayer structures 2 formed on the sapphire substrate 1 in stripes form unit cells, respectively. The drain electrode 15, the gate electrode 20, and the source electrode 25 of the plurality of nitride semiconductor multilayer structures 2 are commonly connected at positions not shown. The drain electrode 15 can be shared between adjacent nitride semiconductor multilayer structures 2.

  As described above, according to this embodiment, normally-off operation is possible by adopting a vertical transistor structure in which the superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 are stacked. Therefore, a field effect transistor having a high withstand voltage that can flow a large current can be realized. Further, since the intrinsic GaN layer 8 and the N-type AlGaN layer 9 are stacked on the sapphire substrate 1 and the drain electrode 15 is formed in contact with the lead portion 10 of the N-type AlGaN layer 9, the superlattice N-type layer 5 is formed. The electrons that have flowed in flow into the two-dimensional electron gas 28 through a wide range of the superlattice N-type layer 5 and move toward the drain electrode 15 provided on the side of the nitride semiconductor multilayer structure portion 2. Thereby, while adopting a structure in which the drain electrode 15 is taken out in the lateral direction, the concentration of a large current can be relaxed, and thus the on-resistance can be effectively reduced. In addition, while using the insulating sapphire substrate 1, a vertical field effect transistor can be formed, and current concentration can be reduced.

  Further, as described above, the use of the superlattice N-type layers 5 and 7 can reduce the overall on-resistance. Further, since the P-type GaN layer 6 is epitaxially grown on the superlattice N-type layer 5, it can have good crystallinity. Thereby, since the channel region 21 has excellent crystallinity, the reliability can be improved. Moreover, since the crystallinity of the P-type GaN layer 6 is good, the amount of P-type dopant to be added during the epitaxial growth of the P-type GaN layer 6 can be reduced.

FIG. 3 is a schematic cross-sectional view for explaining the configuration of a MIS field effect transistor according to the second embodiment of the present invention. In FIG. 3, the same reference numerals as those in FIG. 1 are given to the portions corresponding to those in FIG.
In this embodiment, a conductive substrate 41 is used. The nitride semiconductor multilayer structure portion 2 is formed on one surface of the conductive substrate 41. In this embodiment, the nitride semiconductor multilayer structure portion 2 is superposed on the superlattice N-type layer 5 formed on the surface of the conductive substrate 41, the P-type GaN layer 6 laminated thereon, and the laminate. And a superlattice N-type layer 7. The drain electrode 15 is formed in contact with the other surface of the conductive substrate 41. Therefore, in this embodiment, the drain electrode 15 is electrically connected to the superlattice N-type layer 5 via the conductive substrate 41. Other configurations are the same as those of the first embodiment described above, and the operations are also the same.

Since the conductive substrate 41 is in contact with the superlattice N-type layer 5 over the entire surface thereof, electrons supplied to the superlattice N-type layer 5 through the channel region 21 are superlattice N-type. It goes to the conductive substrate 41 through a wide area of the layer 5 and flows into the drain electrode 15 through this conductive substrate 41. Thus, as the conductive substrate 41 capable of suppressing current concentration, a ZnO substrate, Si substrate, GaAs substrate, GaN substrate, or SiC substrate can be applied. Of these, it is most preferable to use a GaN substrate. By using the GaN substrate as the conductive substrate 41, the lattice constant with the superlattice N-type layer 5 formed on the surface thereof can be matched. Therefore, a GaN substrate is used as the conductive substrate 41, and the superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 are sequentially epitaxially grown on the surface of the conductive substrate 41, thereby reducing lattice defects. The nitride semiconductor multilayer structure portion 2 can be obtained.

  When a conductive substrate 41 having a C-plane (0001) main surface is used, superlattice N-type layer 5, P-type GaN layer 6 and superlattice N-type layer 7 stacked on this conductive substrate 41 by epitaxial growth are: It is also laminated with the C plane (0001) as the main surface. The wall surface 17 of the trench 16 having a V-shaped cross section is, for example, a nonpolar surface (m-plane (10-10) or a-plane (11-20)), or semipolar surface ((10-1-1)), (10 −1-3), (11-22), etc.).

As the conductive substrate 41, the main surface is a nonpolar surface (m-plane (10-10) or a-plane (11-20)) or semipolar surface ((10-1-1), (10-1-3), (11-22) or the like may be used. In this case, the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7 are laminated with the corresponding crystal plane as the main surface.
4A to 4E are schematic cross-sectional views showing the method of manufacturing the field effect transistor of FIG. 3 in the order of steps. The superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 are epitaxially grown in this order on the conductive substrate 41, thereby forming the nitride semiconductor multilayer structure portion 2 (see FIG. 4A). .

  Next, source electrode trenches 24 having a rectangular cross section are formed in a stripe shape with respect to nitride semiconductor multilayer structure portion 2, and source electrodes 25 are embedded in source electrode trenches 24 (FIG. 4B). Since the field effect transistor of this embodiment has a structure in which the drain electrode 15 is taken out from the lower surface side (the side opposite to the nitride semiconductor multilayer structure portion 2) of the conductive substrate 41, a plurality of nitride semiconductor multilayer structure portions 2 are provided. It is not necessary to divide into two, and it can be used in an integrated state on the conductive substrate 41.

  Next, as in the case of the first embodiment, a trench 16 having a V-shaped cross section is formed by dry etching in the vicinity of an intermediate portion between adjacent source electrode trenches 24, and the wall surface 17 is damaged by wet etching. The layer is removed (see FIG. 4C). 4D, after the gate insulating film 19 covering the wall surface 17 of the trench 16 is formed, the drain electrode 15 and the gate electrode 20 are formed as shown in FIG. 4E. In this case, the drain electrode 15 is formed in contact with the lower surface of the conductive substrate 41.

  In this manner, a field effect transistor having a plurality of cells can be manufactured using each trench 16 as a unit cell. Adjacent cells share a source electrode 25 disposed therebetween. As in the case of the first embodiment described above, the gate electrode 20 and the source electrode 25 of the plurality of cells are commonly connected at positions not shown. The drain electrode 15 is formed in contact with the conductive substrate 41 and is a common electrode for all cells.

  FIG. 5 is a schematic cross-sectional view for explaining the configuration of a MIS field effect transistor according to the third embodiment of the present invention. In FIG. 5, parts corresponding to the parts shown in FIG. 3 are given the same reference numerals. In this embodiment, the substrate is not provided, and the drain electrode 15 is formed in contact with the surface of the nitride semiconductor multilayer structure 2 opposite to the gate electrode 20. More specifically, the drain electrode 15 is deposited so as to cover almost the entire lower surface of the superlattice N-type layer 5 (surface opposite to the gate electrode 20). Therefore, the field effect transistor can be formed extremely thin, and the thickness of the entire element from the drain electrode 15 to the upper surface of the gate electrode 20 or the source electrode 25 can be 30 μm or less. Further, the electrons flowing into the superlattice N-type layer 5 diffuse and flow over a wide range of the superlattice N-type layer 5 and flow into the drain electrode 15. Therefore, current concentration can be suppressed.

6A to 6F are schematic sectional views showing a method of manufacturing the field effect transistor of FIG. 5 in the order of steps. The superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 are epitaxially grown in this order on the substrate 45, thereby forming the nitride semiconductor multilayer structure portion 2 (see FIG. 6A).
As the substrate 45, a sapphire substrate, ZnO substrate, Si substrate, GaAs substrate, GaN substrate, or SiC substrate can be applied. It is most preferable to use a GaN substrate from the viewpoint of matching the lattice constant with the nitride semiconductor layer. However, for example, a GaN epitaxial growth layer is formed on the sapphire substrate by lateral selective epitaxial growth, and this is used as the substrate 45. On the GaN epitaxial growth layer, the superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice The N-type layer 7 may be epitaxially grown in order.

  If a substrate 45 whose principal surface is a C-plane (0001) is used, the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7 stacked on the substrate 45 by epitaxial growth have a C-plane (0001). ) Is laminated as a main surface. Further, the wall surface 17 of the trench 16 having a V-shaped cross section formed later is, for example, a nonpolar surface (m-plane (10-10) or a-plane (11-20)) or semipolar surface ((10-1-1)). , (10-1-3), (11-22), etc.). The main surface of the substrate 45 is a nonpolar surface (m-plane (10-10) or a-plane (11-20)) or semipolar surface ((10-1-1), (10-1-3), (11 -22)) may be used. In this case, the superlattice N-type layer 5, the P-type GaN layer 6 and the superlattice N-type layer 7 are laminated with the corresponding crystal plane as the main surface.

  Next, the source electrode trenches 24 having a rectangular cross section are formed in a stripe shape in the nitride semiconductor multilayer structure portion 2, and the source electrodes 25 are embedded in the source electrode trenches 24 (FIG. 6B). Since the field effect transistor of this embodiment has a structure in which the drain electrode 15 is taken out from the lower surface side (the side opposite to the gate electrode 20) of the nitride semiconductor multilayer structure portion 2, a plurality of nitride semiconductor multilayer structure portions 2 are formed. There is no need to split.

  Next, as in the case of the first embodiment, a trench 16 having a V-shaped cross section is formed by dry etching in the vicinity of an intermediate portion between adjacent source electrode trenches 24, and the wall surface 17 is damaged by wet etching. The layer is removed (see FIG. 6C). Further, as shown in FIG. 6D, a gate insulating film 19 covering the wall surface 17 of the trench 16 is formed, and a gate electrode 20 is formed so as to cover this.

Next, as shown in FIG. 6E, the substrate 45 is removed. The removal of the substrate 45 can be performed by a laser lift-off method in which the substrate 45 is peeled off by applying laser light from the surface of the substrate 45, and can also be performed by a CMP (Chemical Mechanical Polishing) process or an etching process. .
Thereafter, as shown in FIG. 6F, the drain electrode 15 is formed. In this case, the drain electrode 15 is formed in contact with the superlattice N-type layer 5.

  In this manner, a field effect transistor having a plurality of cells can be manufactured using each trench 16 as a unit cell. As in the case of the second embodiment described above, adjacent cells share the source electrode 25 disposed therebetween. The gate electrodes 20 and the source electrodes 25 of the plurality of cells are commonly connected at positions not shown. The drain electrode 15 is formed in contact with the superlattice N-type layer 5 and is a common electrode for all cells.

  FIG. 7 is a schematic cross-sectional view for explaining the configuration of a MIS field effect transistor according to the fourth embodiment of the present invention. In FIG. 7, parts corresponding to the parts shown in FIG. 3 are given the same reference numerals as in FIG. In this embodiment, the gate insulating film 50 includes an AlGaN regrowth layer 51 regrown (epitaxially grown) from the wall surface 17 of the trench 16 and an insulating film 52 formed by being laminated on the surface of the AlGaN regrowth layer 51. Is formed. The gate insulating film 50 covers the wall surface 17 of the trench 16 and is formed over the region reaching the edge of the trench 16 on the upper surface of the superlattice N-type layer 7 in the same manner as the gate insulating film 19 in the above-described embodiment. ing.

  The AlGaN regrowth layer 51 is epitaxially grown from the wall surface 17 which is the GaN crystal surface after the trench 16 is formed by dry etching and the wall surface 17 is prepared by wet etching. The aluminum composition of the AlGaN regrowth layer 51 is 50% or more and less than 100%. The AlGaN regrowth layer 51 preferably does not contain In. The wall surface 17 on which the AlGaN regrowth layer 51 is formed has a nonpolar plane (m-plane (10-10) or a-plane (11-20)) or semipolar plane ((10-1-1), (10- 1-3), (11-22) and the like.

The insulating film 52 stacked on the AlGaN regrowth layer 51 can be, for example, a nitride or an oxide. The insulating film 52 improves the insulation properties of the gate insulating film 50 as a whole, thereby contributing to the suppression of the gate leakage current. If the insulating property of the AlGaN regrowth layer 51 is sufficient, the insulating film 52 may be omitted.
According to the configuration of this embodiment, since the interface between the gate insulating film 50 and the wall surface 17 is a joint surface between the GaN crystal and the AlGaN crystal, it is a stable interface. Can be reduced. As a result, the mobility of the channel region 21 can be improved and the leakage current can be suppressed. As a result, the reliability of the device can be improved.

8A to 8F are schematic sectional views showing the method of manufacturing the field effect transistor of FIG. 7 in the order of steps. The superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 are epitaxially grown in this order on the conductive substrate 41, thereby forming the nitride semiconductor multilayer structure portion 2 (see FIG. 8A). .
Next, trenches 16 having a V-shaped cross section are formed in a stripe shape on the nitride semiconductor multilayer structure portion 2 by dry etching, and a damaged layer on the wall surface 17 is removed by wet etching (see FIG. 8B). Then, as shown in FIG. 8C, the AlGaN regrowth layer 51 is formed by epitaxial growth from the wall surface 17 of the trench 16. The AlGaN regrowth layer 51 is an intrinsic semiconductor layer and is grown to a thickness of about 1000 mm, for example.

Thereafter, as shown in FIG. 8D, a source electrode trench 24 having a rectangular cross section is formed in the vicinity of an intermediate portion between adjacent V-shaped trenches 16, and a source electrode 25 is formed so as to be embedded therein.
Thereafter, as shown in FIG. 8E, an insulating film 52 is laminated on the AlGaN regrowth layer 51.
After the gate insulating film 50 is thus formed, the gate electrode 20 is formed. Thereafter, as shown in FIG. 8F, the drain electrode 15 is formed. The drain electrode 15 is formed in contact with the lower surface of the conductive substrate 41.

In this manner, a field effect transistor having a plurality of cells can be manufactured using each trench 16 as a unit cell. The gate electrode 20 and the source electrode 25 of the plurality of cells are commonly connected at positions not shown. The drain electrode 15 is formed in contact with the conductive substrate 41 and is a common electrode for all cells.
As mentioned above, although four embodiment of this invention was described, this invention can also be implemented with another form. For example, the structure of the gate insulating film 50 shown in FIG. 7 can be used in place of the gate insulating film 19 of the first embodiment (FIG. 1) and the third embodiment (FIG. 5).

  Furthermore, in the above-described embodiment, the example in which the V-shaped trench 16 is formed in the nitride semiconductor multilayer structure 2 has been described, but the shape of the trench 16 may be other than an inverted trapezoid, U shape, rectangle, trapezoid, and the like. The shape may also be Further, the wall surface 17 does not need to be an inclined surface inclined with respect to the substrate, and does not need to be a flat surface. That is, the wall surface 17 may be a plane perpendicular to the substrate or a curved surface.

  In the above-described embodiment, the gate insulating film 19 and the gate electrode 20 are stacked on both the pair of wall surfaces 17 of the trench 16. However, these stacked structures are formed only on one wall surface 17. It is good. Further, for example, the nitride semiconductor multilayer structure portion 2 is etched at a position indicated by a two-dot chain line 60 in FIG. 3, and a device is formed using only one side of the two-dot chain line 60. Good. In this case, a trench having a V-shaped cross section is not formed in the nitride semiconductor multilayer structure portion 2, but a wall surface 17 extending over the superlattice N-type layer 5, the P-type GaN layer 6, and the superlattice N-type layer 7 is formed. become.

  In addition, various design changes can be made within the scope of matters described in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view for explaining the structure of a MIS field effect transistor according to a first embodiment of the invention. 2A to 2E are schematic cross-sectional views showing a method of manufacturing the MIS field effect transistor of FIG. 1 in the order of steps. FIG. 5 is a schematic cross-sectional view for explaining a configuration of a MIS field effect transistor according to a second embodiment of the present invention. 4A to 4E are schematic cross-sectional views showing the method of manufacturing the field effect transistor of FIG. 3 in the order of steps. It is an illustration sectional view for explaining the composition of the MIS field effect transistor concerning a 3rd embodiment of this invention. 6A to 6F are schematic sectional views showing a method of manufacturing the field effect transistor of FIG. 5 in the order of steps. It is an illustration sectional view for explaining the composition of the MIS type field effect transistor concerning a 4th embodiment of this invention. 8A to 8F are schematic sectional views showing the method of manufacturing the field effect transistor of FIG. 7 in the order of steps.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sapphire substrate 2 Nitride semiconductor laminated structure part 5 Superlattice N type layer 6 P type GaN layer 7 Superlattice N type layer 8 True GaN layer 9 N type AlGaN layer 10 Lead part 15 Drain electrode 16 Trench 17 Wall surface 19 Gate insulating film 20 gate electrode 21 channel region 24 source electrode trench 25 source electrode 28 two-dimensional electron gas 30 groove 41 conductive substrate 45 substrate 50 gate insulating film 51 AlGaN regrowth layer 52 insulating film

Claims (26)

First conductivity type first group III-V nitride semiconductor layer, second conductivity type second group III-V nitride semiconductor layer stacked on the first group III-V nitride semiconductor layer, and second type III-V A third group III-V nitride semiconductor layer of the first conductivity type stacked on a group nitride semiconductor layer, wherein at least one of the first and third group III-V nitride semiconductor layers has a composition A nitride semiconductor multilayer structure, which is a superlattice semiconductor layer made of different nitrides, and
Gate insulation formed on the wall formed across the first, second and third III-V nitride semiconductor layers so as to straddle the first, second and third III-V nitride semiconductor layers A membrane,
A gate electrode made of a conductive material formed to face the second group III-V nitride semiconductor layer with the gate insulating film interposed therebetween;
A drain electrode electrically connected to the first III-V nitride semiconductor layer;
A MIS field-effect transistor including a source electrode electrically connected to the third III-V nitride semiconductor layer.   2. The MIS field effect transistor according to claim 1, wherein the superlattice semiconductor layer is made of an AlGaN superlattice layer having a different Al composition.   The MIS field effect transistor according to claim 1 or 2, wherein the superlattice layer constituting the superlattice semiconductor layer has a thickness of 10 to 100 mm.   A trench is formed from the third group III-V nitride semiconductor layer through the second group III-V nitride semiconductor layer to reach the first group III-V nitride semiconductor layer. The MIS type field effect transistor according to any one of claims 1 to 3, wherein each forms the wall surface.   5. The source electrode according to claim 1, wherein the source electrode is provided in contact with both the second III-V nitride semiconductor layer and the third III-V nitride semiconductor layer. 6. MIS type field effect transistor. The nitride semiconductor multilayer structure is disposed on the opposite side of the first III-V group nitride semiconductor layer from the second group III-V nitride semiconductor layer. Further comprising a group V nitride semiconductor layer;
The MIS field effect transistor according to claim 1, wherein the drain electrode is connected to the fourth group III-V nitride semiconductor layer.   The nitride semiconductor multilayer structure is disposed on the opposite side of the first III-V group nitride semiconductor layer from the second group III-V nitride semiconductor layer, and contains the first conductivity type containing Al. The MIS field effect transistor according to claim 1, further comprising a fourth group III-V nitride semiconductor layer.   The MIS field effect transistor according to claim 7, wherein the drain electrode is connected to the fourth group III-V nitride semiconductor layer.   The MIS field effect transistor according to claim 1, wherein the nitride semiconductor multilayer structure is formed on a substrate.   The MIS field effect transistor according to claim 9, wherein the substrate is an insulating substrate. The MIS field effect transistor according to claim 9, wherein the substrate is an Al ₂ O ₃ substrate, a ZnO substrate, a Si substrate, a GaAs substrate, a GaN substrate, or a SiC substrate.   The substrate is a substrate having a region having a high dislocation density and a region having a low dislocation density in the horizontal direction, and the gate electrode is disposed so as to face a region grown from a region having a low dislocation density. The MIS field effect transistor according to any one of claims 9 to 11. The nitride semiconductor multilayer structure is disposed on one surface of a conductive substrate;
The MIS field effect transistor according to claim 1, wherein the drain electrode is connected to the other surface of the conductive substrate.   The MIS field effect transistor according to claim 1, wherein the drain electrode is connected to the first III-V nitride semiconductor layer.   The MIS type electric field according to any one of claims 1 to 5, wherein the drain electrode is formed in contact with the surface opposite to the gate electrode with respect to the nitride semiconductor multilayer structure portion. Effect transistor.   The MIS field effect transistor according to claim 1, wherein the first, second, and third group III-V nitride semiconductor layers are stacked with a C-plane as a main surface.   The MIS type field effect according to any one of claims 1 to 15, wherein the first, second and third group III-V nitride semiconductor layers are stacked with a nonpolar plane or a semipolar plane as a main plane. Transistor.   The wall surface of the said 1st, 2nd and 3rd III-V group nitride semiconductor layer in which the said gate insulating film is formed is a nonpolar surface or a semipolar surface, It is any one of Claims 1-17 MIS field effect transistor.   The MIS field effect transistor according to claim 1, wherein the gate insulating film is a nitride or an oxide.   The MIS field effect transistor according to claim 1, wherein the gate insulating film is made of silicon nitride or silicon oxide.   21. The MIS field effect transistor according to claim 1, wherein the conductive material constituting the gate electrode is made of a single metal or an alloy containing at least one of Al, Au, and Pt. .   21. The MIS field effect transistor according to claim 1, wherein the conductive material constituting the gate electrode includes polysilicon.   The MIS field effect transistor according to any one of claims 1 to 22, wherein the source electrode or the drain electrode is made of a material containing at least Al.   The MIS field effect transistor according to any one of claims 1 to 22, wherein the source electrode or the drain electrode is made of an alloy material containing at least Ti and Al.   The MIS field effect transistor according to any one of claims 1 to 22, wherein a material constituting the source electrode or the drain electrode contains Mo or Mo compound, Ti or Ti compound, or W or W compound. Forming a first III-V nitride semiconductor layer of a first conductivity type on a substrate;
Forming a second conductivity type second group III-V nitride semiconductor layer on the first group III-V nitride semiconductor layer; and
A step of stacking and forming the first conductivity type third group III-V nitride semiconductor layer on the second group III-V nitride semiconductor layer;
A wall surface forming step of forming a wall surface straddling the first, second and third group III-V nitride semiconductor layers;
Forming a gate insulating film on the wall surface so as to straddle the first, second, and third group III-V nitride semiconductor layers;
Forming a gate electrode made of a conductive material so as to face the second group III-V nitride semiconductor layer with the gate insulating film interposed therebetween;
Forming a drain electrode so as to be electrically connected to the first III-V nitride semiconductor layer;
Forming a source electrode so as to be electrically connected to the third group III-V nitride semiconductor layer,
At least one of the step of forming the first III-V group nitride semiconductor layer and the step of forming the third group III-V nitride semiconductor layer forms a superlattice semiconductor layer made of nitride having a different composition A method for manufacturing a MIS field effect transistor.

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