JP4190754B2 - Method for manufacturing field effect transistor - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor (FET) and a manufacturing method thereof, and more particularly, to a metal-insulator-semiconductor (MIS) FET using a wide gap semiconductor in a channel layer and a manufacturing method thereof.
[0002]
[Prior art]
MISFETs using wide-gap semiconductors such as GaN and AlGaN for the channel layer have an on-resistance that is more than an order of magnitude lower than MISFETs using Si, GaAs, etc., and have high withstand voltage, high-temperature operation and large current operation. It is attracting attention as a possible device.
[0003]
An example of a conventional GaN-based MISFET will be described with reference to FIG.
On the sapphire substrate 50, a GaN buffer layer (not shown), an undoped GaN layer (not shown), and a p-type GaN channel layer 52 doped with Mg (magnesium) impurities are sequentially laminated. Further, an n-type impurity such as Si (silicon) is added to the surface of the p-type GaN channel layer 52 using a resist pattern formed on the p-type GaN channel layer 52 by photolithography as a mask. The n-type GaN source region 54 and the n-type GaN drain region 56 are formed opposite to both sides of the central portion to which no n-type impurity is added.
[0004]
Further, on the n-type GaN source region 54 and the n-type GaN drain region 56, for example, Al (aluminum) and Ti (titanium) are sequentially deposited and stacked, and the source electrode 58 and the drain electrode 60 having an Al / Ti stacked structure are stacked. Are formed respectively. Further, on the n-type GaN source region 54 and the n-type GaN drain region 56 and the p-type GaN channel layer 52 in the central portion sandwiched between, for example via a gate insulating film 62 made of SiO ₂ film, Al / Ti A gate electrode 64 having a laminated structure is formed.
[0005]
Here, the p-type GaN channel layer 52 sandwiched between the opposing n-type GaN source region 54 and n-type GaN drain region 56 becomes the channel region of the MISFET, and the length thereof becomes the channel length L.
Thus, the conventional GaN-based MISFET has a planar structure substantially the same as that of a MISFET using Si or GaAs.
[0006]
In addition, regarding the formation of the source region and the drain region, instead of the above method, a resist pattern is formed on the p-type GaN channel layer 52 using a photolithography technique, and the p-type GaN is formed using this resist pattern as a mask. There is also a method in which the channel layer 52 is selectively etched to form two recesses facing each other, and an n-type GaN layer is selectively embedded and grown in the recess.
[0007]
In any case, the length of the p-type GaN channel layer 52 sandwiched between the n-type GaN source region 54 and the n-type GaN drain region 56, that is, the channel length L is formed on the p-type GaN channel layer 52. Therefore, the channel length L of the GaN-based MISFET is about 6 μm.
[0008]
[Problems to be solved by the invention]
As described above, in the conventional GaN-based MISFET, since the channel length L is defined by the processing accuracy by the photolithography technique, there is a limit to achieving a sufficiently short channel length. For this reason, although the p-type GaN channel layer 52 has a wider band gap than Si, GaAs, etc., there is a problem that the on-resistance during the operation of the MISFET cannot be sufficiently reduced.
[0009]
Further, since the source electrode 58 and the drain electrode 60 having an Al / Ti laminated structure are used, the contact resistance with the n-type GaN source region 54 and the n-type GaN drain region 56 is, for example, 2 × 10 ⁻⁴ Ωcm ^{2 on} average. There was also a problem of becoming very high.
In this way, the conventional MISFET using a wide gap semiconductor such as GaN or AlGaN for the channel layer can theoretically reduce the on-resistance during operation by an order of magnitude or more compared to the MISFET using Si or GaAs. Nevertheless, a suitable device structure for utilizing the advantages of such a wide gap semiconductor has not yet been clarified.
[0010]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a high breakdown voltage FET capable of sufficiently reducing the on-resistance during operation and a method for manufacturing the same.
[0013]
[Means for Solving the Problems]
In the present invention, the first crystal is formed on the substrate by continuous crystal growth to form a stacked structure in which a source layer and a drain layer are arranged above and below a channel layer made of a nitride III- V compound semiconductor. and steps, is selectively removed by etching the laminated structure, the to expose an inclined surface or a vertical surface having a predetermined angle to the side surface of the laminated structure, exposed surfaces of the source layer and the drain layer a second step of, on the entire surface of the source layer and the drain layer and the inclined surface or the vertical surface, after forming a gate insulating film, on the gate insulating film, a third step of forming an insulating film When the insulating film is selectively etched away, after the gate insulating film at a position of the channel layer in the inclined surface or the vertical surface is a contact hole for exposing the contact holes And a fourth step of forming a gate electrode by filling a predetermined conductive material in the cell. A method of manufacturing a field effect transistor is provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
As shown in FIG. 1, in an example of the GaN-based MISFET according to the present embodiment, for example, a GaN buffer layer (not shown), an undoped GaN layer 12, an n-type GaN drain on a semi-insulating sapphire substrate 10. A layer 14, for example, a p-type GaN channel layer 16 having a thickness of 30 nm, and an n-type GaN source layer 18 are sequentially stacked. That is, the n-type GaN source layer 18 and the n-type GaN drain layer 14 are disposed above and below the p-type GaN channel layer 16.
[0015]
Further, the laminated structure composed of the n-type GaN source layer 18, the p-type GaN channel layer 16, and the n-type GaN drain layer 14 has a mesa shape in which both side surfaces are inclined surfaces having a predetermined angle in the lamination direction. Has been processed. That is, both side surfaces of the p-type GaN channel layer 16 form part of this mesa-shaped inclined surface.
Further, the SiO ₂ gate insulating film 24 is formed on the entire surface of the mesa shape, and the inclined both side surfaces of the p-type GaN channel layer 16 are covered with the SiO ₂ gate insulating film 24. In addition, on the SiO ₂ gate insulating film 24, a portion other than the inclined surface of the laminated structure described above and a portion excluding a gate electrode, a source electrode, and a drain electrode, which will be described later, are provided as a pressure-resistant and heat-resistant resin. An interlayer insulating film 26 made of polyimide is formed.
[0016]
Then, the source electrode 32S and the two drain electrodes 32Da that are ohmic-connected to the n-type GaN source layer 18 and the n-type GaN drain layer 14 through contact holes opened in the interlayer insulating film 26 and the SiO ₂ gate insulating film 24, respectively. , 32 dB is formed, also through the opened contact holes in the interlayer insulating film 26 and the SiO ₂ gate insulating film 24, the SiO ₂ gate insulating film 24 on both sides which are inclined in the p-type GaN channel layer 16 Two gate electrodes 40Ga and 40Gb that are in contact with each other are formed.
[0017]
The source electrode 32S and the drain electrodes 32Da and 32Db are TaSi, which is an electrode material having good adhesion to the SiO ₂ gate insulating film 24 and having low contact resistance with the n-type GaN source layer 18 and the n-type GaN drain layer 14. In addition, a TaSi / Au laminated structure in which Au (gold) is laminated in order from the bottom. The gate electrodes 40Ga and 40Gb have a Ni / Au stacked structure in which Ni (nickel) and Au are sequentially stacked.
[0018]
Here, the surface composed of the source electrode 32S and the drain electrodes 32Da and 32Db, the gate electrodes 40Ga and 40Gb, and the interlayer insulating film 26 is a flat surface.
In this way, the source electrode 32S and the drain electrode 32Da are ohmically connected to the n-type GaN source layer 18 and the n-type GaN drain layer 14, respectively, and the p-type is sandwiched between the n-type GaN source layer 18 and the n-type GaN drain layer 14. A gate electrode 40Ga is provided on one inclined side surface of the GaN channel layer 16 via an SiO ₂ gate insulating film 24, thereby constituting an enhancement type first MISFET 42a.
[0019]
Similarly, the source electrode 32S and the drain electrode 32Db are ohmically connected to the n-type GaN source layer 18 and the n-type GaN drain layer 14, respectively, and the SiO ₂ gate insulating film 24 is formed on the other inclined side surface of the p-type GaN channel layer 16. A gate electrode 40Gb is provided through the second electrode, thereby forming an enhancement type second MISFET 42b. And these 1st and 2nd MISFET42a, 42b is arrange | positioned adjacent to the both sides which mesa shape opposes.
[0020]
In this FET structure, the vicinity of the inclined side surfaces of the p-type GaN channel layer 16 having a thickness of 30 nm sandwiched between the n-type GaN source layer 18 and the n-type GaN drain layer 14 is the channel length L shown in the figure. A channel region having The channel length L is a function of the thickness of the channel layer 16 and the rising angle of the inclined surface formed in the laminated structure. For example, if the rising angle of the inclined surface is θ and the thickness of the channel layer 16 is d, d · sin ⁻¹ θ is obtained.
[0021]
Therefore, the channel length L in this FET structure can be controlled by the thickness of the p-type GaN channel layer 16 if the rising angles θ of the inclined surfaces of the stacked structure are the same. A dramatic shortening of the channel length from the μm order to the nm order, which is controlled by the dimensional accuracy of the resist pattern, can be achieved easily and with high precision. Therefore, it is possible to realize a MISFET that can perform a switching operation with a sufficiently small on-resistance.
[0022]
As described above, according to the present embodiment, since the p-type GaN channel layer 16 having a sufficiently large band gap as compared with Si, GaAs or the like is used, high-temperature operation is possible and gate breakdown voltage is significantly increased. Can do.
Incidentally, when the inventors made a prototype of a GaN-based MISFET as shown in FIG. 1 and measured its characteristics, the on-resistance when the gate-source voltage V _GS = 0 V was 1 as compared with the conventional case. about digit decreases, it became 10mΩcm ^2. Moreover, the gate breakdown voltage exceeded 400V.
[0023]
In addition, since the first and second MISFETs 42a and 42b are formed using two opposed mesa-shaped inclined surfaces, a combination of these two MISFETs facilitates a large current operation. . Further, it is possible to contribute to higher density and higher integration of an integrated circuit composed of these MISFETs.
In the above embodiment, the case where the p-type GaN channel layer 16 having a thickness of 30 nm is used and the channel length L along the inclined surface of the p-type GaN channel layer 16 is 40 nm has been described. The thickness of the channel layer 16 and the channel length L defined by the thickness and the inclination angle are not limited to the above case, and can take various values depending on the required MISFET characteristics. .
[0024]
Incidentally, when the inventors calculated the change in the on-resistance when the thickness of the p-type GaN channel layer 16 was changed, the result shown in the graph of FIG. 2 was obtained. As is apparent from this graph, it is confirmed that the on-resistance decreases as the thickness of the p-type GaN channel layer 16 decreases. However, it should also be noted that if the p-type GaN channel layer 16 becomes too thin, gate control becomes ineffective, and good FET operation becomes difficult.
[0025]
In addition, instead of forming the first and second MISFETs 42a and 42b adjacent to each other using two opposed mesa-shaped inclined surfaces as in the above-described embodiment, only one inclined surface is used. Of course, it is also possible to form a MISFET. On the other hand, if the mesa shape is a polygonal frustum shape, for example, a quadrangular frustum shape, four MISFETs can be formed adjacent to each other using the four inclined surfaces. In this case, it is possible to operate at a higher current and contribute to further higher density and higher integration of the integrated circuit.
[0026]
It is also possible to adopt a rectangular shape as the mesa shape, make the side surface of the mesa shape a vertical surface, and use this vertical surface instead of the inclined surface in the above embodiment to form a MISFET. In the FET structure in this case, the vicinity of the vertical side surface of the p-type GaN channel layer sandwiched between the n-type GaN source layer and the n-type GaN drain layer is a channel region, and the thickness of the p-type GaN channel layer is Immediate channel length L is obtained.
[0027]
Further, instead of the semi-insulating sapphire substrate 10, a conductive semiconductor substrate made of, for example, SiC, Si, GaAs, GaP or the like may be used.
Further, instead of the p-type GaN channel layer 16, a p-type channel layer made of GaN doped with Mg impurities, InGaN, AlGaN, InGaNAs, InGaNP, or AlInGaNP, or SiC doped with Al impurities or B (boron) impurities. It may be used.
[0028]
Further, in place of the n-type GaN source layer 18 and the n-type GaN drain layer 14, doped with Si impurity doped InGaN, AlGaN, InGaNAs, InGaNP, or AlInGaNP, or N (nitrogen) impurity or P (phosphorus) impurity. An n-type source layer and an n-type drain layer made of SiC may be used.
[0029]
【Example】
An example of a method for manufacturing the GaN-based MISFET according to the above embodiment will be described with reference to FIGS.
First, a series of crystal growth was performed on the semi-insulating sapphire substrate 10 by, for example, a gas source MBE (Molecular Beam Epitaxy) method using an ultra vacuum growth apparatus.
[0030]
That is, at a growth temperature of 640 ° C., Ga (gallium) with a partial pressure of 4 × 10 ⁻⁵ Pa and N radicalized with a partial pressure of 4 × 10 ⁻⁴ Pa are used as a source gas, and a GaN buffer layer (not shown) is formed. The film was grown to a thickness of 50 nm. Continuously, at a growth temperature of 850 ° C., an undoped GaN layer 12 was grown to a thickness of 1000 nm using Ga with a partial pressure of 1.33 × 10 ⁻³ Pa and N with a partial pressure of 6.65 × 10 ⁻³ Pa. .
[0031]
The continuous, at a growth temperature 850 ° C., a partial pressure of 6.65 × 10 ^-4 Pa of Ga and partial pressure 6.65 × 10 ^-3 Pa using an N, the partial pressure of 6.65 × 10 ^-6 Pa Si was added as a dopant, and an n-type GaN drain layer 14 having a carrier concentration of about 1 × 10 ¹⁹ cm ⁻³ was grown to a thickness of 200 nm. Further continuously, at a growth temperature 850 ° C., using N of the partial pressure 6.65 × 10 ^-7 Pa of Ga and partial pressure 6.65 × 10 ^-3 Pa, the partial pressure of 6.65 × 10 ^-6 Pa Mg was added as a dopant to grow a p-type GaN channel layer 16 having a carrier concentration of about 5 × 10 ¹⁸ cm ⁻³ to a thickness of 30 nm.
[0032]
Further continuously, at a growth temperature 850 ° C., using N of the partial pressure 6.65 × 10 ^-4 Pa of Ga and partial pressure 6.65 × 10 ^-3 Pa, the partial pressure of 6.65 × 10 ^-4 Pa Si was added as a dopant, and an n-type GaN source layer 18 having a carrier concentration of about 1 × 10 ¹⁹ cm ⁻³ was grown to a thickness of 200 nm. Thus, a stacked structure was formed in which the p-type GaN channel layer 16 was sandwiched between the n-type GaN source layer 18 and the n-type GaN drain layer 14 (see FIG. 3).
[0033]
At this time, an organic metal gas such as TEG (Ga (C ₂ H ₅ ) ₃ ; triethylgallium) or TMG (Ga (CH ₃ ) ₃ ; trimethylgallium) was used as the Ga source. As the N source, for example, (CH ₃ ) ₂ · N ₂ H ₄ ; dimethylhydrazine), (CH ₃ ) ₂ · N ₂ H ₄ ; dimethylhydrazine), NH ₃ (ammonia), or the like was used. SiH ₄ (monosilane) or the like was used as the Si source. As the Mg source, organic Mg such as dicyclopentadienyl Mg was used.
[0034]
Further, instead of the gas source MBE method, a series of crystal growth may be performed using a MOCVD (Metal Organic Chemical Vapor Deposition) method.
Next, an SiO ₂ film 20 having a thickness of 200 nm was formed on the n-type GaN source layer 18 by, for example, a plasma CVD (Chemical Vapor Deposition) method. Instead of the SiO ₂ film 20, an SiN _x film or an AlN film may be formed. Subsequently, a resist film was applied onto the SiO ₂ film 20 and then patterned using a lithography technique to form a resist pattern 22 having a predetermined shape (see FIG. 4).
[0035]
Then, using the resist pattern 22 as a mask, for example, a dry etching method using a wet etching method or CF ₄ using BHF, and selectively removed by etching the SiO ₂ film 20 was patterned into a predetermined shape. Thereafter, the resist pattern 22 was removed by, for example, a method using acetone or methanol or an O ₂ ashing method.
[0036]
Subsequently, by using a patterned SiO ₂ film 20 as a mask by an ECR (Electron Cyclotron Resonance) plasma etching method or a RIBE (Reactive Ion Beam Etching) method using a methane-based gas, A part of the n-type GaN source layer 18, the p-type GaN channel layer 16, and the n-type GaN drain layer 14 was selectively etched away in order to form a mesa shape. The opposite side surfaces of the mesa shape are inclined surfaces in which a part of the n-type GaN source layer 18, the p-type GaN channel layer 16, and the n-type GaN drain layer 14 are exposed. That is, the inclined side surface of the p-type GaN channel layer 16 forms a part of the mesa-shaped inclined surface.
[0037]
At this time, both inclined side surfaces of the p-type GaN channel layer 16 sandwiched between the n-type GaN source layer 18 and the n-type GaN drain layer 14 become channel regions of the MISFET to be manufactured. The channel length L is the channel length L. This channel length L is defined by the thickness of the p-type GaN channel layer 16 and the conditions of mesa processing, and is mainly defined by the thickness of the p-type GaN channel layer 16 and is 40 nm here (see FIG. 5). .
[0038]
Next, after the SiO ₂ film 20 was removed, a SiO ₂ gate insulating film 24 was formed to a thickness of 50 nm on the entire mesa shape by, eg, thermal CVD or plasma CVD. Thus, the inclined both side surfaces of the p-type GaN channel layer 16 were covered with the SiO ₂ gate insulating film 24. Subsequently, an interlayer insulating film 26 made of polyimide as a pressure resistant and heat resistant resin was formed on the entire surface of the SiO ₂ gate insulating film 24 to a thickness of 3000 nm (see FIG. 6).
[0039]
Next, after applying an EB (Electron Beam) resist film on the interlayer insulating film 26, patterning is performed using the EB lithography technique to form a resist pattern 28 that opens the source and drain formation planned regions (FIG. 7).
Next, by using this resist pattern 28 as a mask, the interlayer insulating film 26 and the SiO ₂ gate insulating film 24 are selectively removed by etching sequentially by the RIBE method using a dry etching apparatus, so that the n-type GaN source layer 18 is exposed. At the same time when the contact hole 30S was opened, two contact holes 30Da and 30Db where the n-type GaN drain layer 14 was exposed were opened. Thereafter, the resist pattern 28 was removed by, for example, a method using acetone or methanol or an O ₂ ashing method (see FIG. 8).
[0040]
Next, the n-type GaN source layer 18 has good adhesion to the SiO ₂ gate insulating film 24 over the entire surface of the interlayer insulating film 26 where the contact holes 30S, 30Da, 30Db are opened by, for example, sputtering deposition using Ar plasma. In addition, TaSi and Au, which are electrode materials having a low contact resistance with the n-type GaN drain layer 14, are stacked in order from the bottom to form a TaSi / Au layer 32, and contact holes 30 </ b> S and 30 Da are formed by the TaSi / Au layer 32. , 30 Db was filled. Instead of the TaSi / Au layer 32, for example, a WSi / Au layer, a TaSi layer, an AlSi / Au layer, a NiSi / Au layer, or the like may be formed (see FIG. 9).
[0041]
Next, the TaSi / Au layer 32 and the interlayer insulating film 26 are polished by, for example, CMP (Chemical Mechanical Polishing), and the TaSi / Au layer 32 is separated only in the contact holes 30S, 30Da, and 30Db. While remaining, the surface composed of the TaSi / Au layer 32 and the interlayer insulating film 26 was made a flat surface.
[0042]
Thus, the source electrode 32S composed of the TaSi / Au layer 32 in the contact hole 30S that is in ohmic contact with the n-type GaN source layer 18 was formed. At the same time, two drain electrodes 32Da and 32Db composed of the TaSi / Au layer 32 in the contact holes 30Da and 30Db that are ohmic-connected to the n-type GaN drain layer 14 were formed (see FIG. 10).
[0043]
Next, an SiO ₂ film 34 having a thickness of 200 nm was formed on the entire surface of the interlayer insulating film 26, the source electrode 32S, and the drain electrodes 32Da and 32Db by, for example, plasma CVD. Subsequently, after applying an EB resist film on the SiO ₂ film 34, patterning was performed using an EB lithography technique to form a resist pattern 36 having an opening in a gate formation scheduled region (see FIG. 11).
[0044]
Next, by using the resist pattern 36 as a mask, the SiO ₂ film 34 and the interlayer insulating film 26 are selectively removed in order by the RIBE method using a dry etching apparatus, and the inclined both side surfaces of the p-type GaN channel layer 16 are removed. Two contact holes 38Ga and 38Gb were opened to expose the SiO ₂ gate insulating film 24 covering the substrate. Thereafter, the resist pattern 36 was removed by, for example, a method using acetone or methanol or an O ₂ ashing method. (See FIG. 12).
[0045]
Next, Ni and Au are stacked in this order from the bottom on the entire surface of the SiO ₂ film 34 in which the contact holes 38Ga and 38Gb are opened, for example, by sputtering using Ar plasma to form the Ni / Au layer 40. The Ni / Au layer 40 fills the contact holes 38Ga and 38Gb (see FIG. 13).
Then, for example, CMP to polish the Ni / Au layer 40 and the SiO ₂ film 34 to the source electrode 32S and the drain electrode 32 Da, the surface of such 32Db exposed, contact holes 38Ga, only Ni / Au layer 38Gb 40 was separated and left, and the surface composed of the Ni / Au layer 40, the source electrode 32S, the drain electrodes 32Da and 32Db, and the interlayer insulating film 26 was made flat. Then, two gate electrodes 40Ga and 40Gb made of the Ni / Au layer 40 in the contact holes 38Ga and 38Gb in contact with the SiO ₂ gate insulating film 24 were formed.
[0046]
Thus, the source electrode 32S and the drain electrodes 32Da and 32Db are ohmically connected to the n-type GaN source layer 18 and the n-type GaN drain layer 14, respectively, and the upper and lower sides are sandwiched between the n-type GaN source layer 18 and the n-type GaN drain layer 14. Enhancement-type first and second MISFETs 42a and 42b provided with gate electrodes 40Ga and 40Gb provided on both inclined side surfaces of the p-type GaN channel layer 16 via the SiO ₂ gate insulating film 24 are formed adjacent to each other. (See FIG. 14).
[0047]
Next, although illustration is omitted, an interlayer insulating film made of, for example, polyimide is formed on each of these electrodes and the interlayer insulating film 26 by using a multilayer wiring technique, and through a contact hole opened in the interlayer insulating film. Then, wiring layers were formed which were appropriately connected to the source electrode 32S, the drain electrodes 32Da and 32Db, and the gate electrodes 40Ga and 40Gb. Thus, a predetermined integrated circuit composed of the first and second MISFETs 42a, 42b and the like connected to each other by the wiring layer was formed.
[0048]
Through a series of steps as described above, a GaN-based MISFET as shown in FIG. 1 was produced.
As described above, according to the manufacturing method according to the present embodiment, since the CMP method is used when forming the source electrode 32S, the drain electrodes 32Da and 32Db, and the gate electrodes 40Ga and 40Gb, each electrode is in contact with each other. Although the heights of the n-type GaN source layer 18, the n-type GaN drain layer 14, and the SiO ₂ gate insulating film 24 are different from each other, the surface formed of these electrodes and the interlayer insulating film 26 can be made flush with each other. become. Accordingly, the multilayer wiring process after the formation of the first and second MISFETs 42a and 42b can be facilitated.
[0049]
【The invention's effect】
As described above in detail, according to the present invention, the channel layer made of a wide gap semiconductor is formed on the channel layer side surface in the inclined surface or the vertical surface provided in the stacked structure sandwiched between the source layer and the drain layer. Since the gate electrode is provided through the gate insulating film, the side surface of the channel layer on the inclined surface or the vertical surface becomes a channel region, and the channel length can be controlled by the thickness of the channel layer. Accordingly, it is possible to realize a MISFET that can achieve a short channel length easily and with high accuracy and can perform a switching operation with a sufficiently small on-resistance.
[0050]
In addition, since a wide gap semiconductor is used for the channel layer, high-temperature operation is possible and the gate breakdown voltage can be significantly increased.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a GaN-based MISFET according to an embodiment of the present invention.
2 is a graph showing the relationship between the p-type GaN channel layer thickness and on-resistance in the GaN-based MISFET of FIG.
3 is a process cross-sectional view (No. 1) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
4 is a process cross-sectional view (No. 2) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
FIG. 5 is a process cross-sectional view (part 3) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1;
6 is a process cross-sectional view (No. 4) for explaining the manufacturing method of the GaN-based MISFET shown in FIG. 1; FIG.
7 is a process cross-sectional view (No. 5) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
8 is a process cross-sectional view (No. 6) for explaining the manufacturing method of the GaN-based MISFET shown in FIG. 1; FIG.
FIG. 9 is a process cross-sectional view (No. 7) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1;
10 is a process cross-sectional view (No. 8) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
11 is a process cross-sectional view (No. 9) for explaining the manufacturing method of the GaN-based MISFET shown in FIG. 1; FIG.
12 is a process cross-sectional view (No. 10) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
13 is a process cross-sectional view (No. 11) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
14 is a process cross-sectional view (No. 12) for explaining the method of manufacturing the GaN-based MISFET shown in FIG. 1; FIG.
FIG. 15 is a schematic cross-sectional view showing a conventional GaN-based MISFET.
[Explanation of symbols]
10 Sapphire substrate 12 Undoped GaN layer 14 n-type GaN drain layer 16 p-type GaN channel layer 18 n-type GaN source layer 20 SiO ₂ film 22 resist pattern 24 SiO ₂ gate insulating film 26 interlayer insulating film 28 resist patterns 30S, 30Da, 30Db Contact hole 32 TaSi / Au layer 32S Source electrode 32Da, 32Db Drain electrode 34 SiO ₂ film 36 Resist pattern 38Ga, 38Gb Contact hole 40 Ni / Au layer 40Ga, 40Gb Gate electrode 42a First MISFET
42b Second MISFET
L channel length

Claims (3)

A first step of performing continuous crystal growth on a substrate to form a stacked structure in which a source layer and a drain layer are disposed above and below a channel layer made of a nitride-based III-V compound semiconductor; A second step of selectively removing the laminated structure by etching to expose an inclined surface or a vertical surface having a predetermined angle on the side surface of the laminated structure and exposing the surfaces of the source layer and the drain layer; And a third step of forming an insulating film on the gate insulating film after forming a gate insulating film on the entire surface of the source layer, the drain layer, and the inclined surface or the vertical surface;
After selectively removing the insulating film by etching to open a contact hole where the gate insulating film is exposed at the channel layer on the inclined surface or the vertical surface, a predetermined conductive material is formed in the contact hole. A fourth step of forming a gate electrode,
A method for producing a field effect transistor, comprising: When forming the gate electrode in the fourth step, a predetermined conductive material is deposited on the entire surface of the insulating film in which the contact hole is opened, and then the conductive material is polished to form the contact hole. the filled with a conductive material separated, a method of manufacturing a field effect transistor of claim 1 wherein within. After the third step, the insulating film and the gate insulating film are selectively removed by etching in order to form a contact hole exposing the source layer and the drain layer, and the insulation in which the contact hole is opened A predetermined conductive material is deposited on the entire surface of the film, the conductive material is polished and the conductive material is separated and filled in the contact holes, and a source electrode and a drain electrode made of the conductive material are provided. The method of manufacturing a field effect transistor according to claim 2 , further comprising a step of forming the source layer and the drain layer, respectively.

Images