JP4748501B2 - High electron mobility transistor - Google Patents

Description

  The present invention relates to a high electron mobility transistor made of a nitride compound semiconductor.

  Nitride-based compound semiconductor materials such as GaN, InGaN, AlGaN, and AlInGaN have a higher band gap energy than GaAs-based III-V group compound semiconductor materials, and electronic devices using these materials have a heat resistant temperature. High and excellent at high temperature operation. In recent years, electronic devices such as FETs using GaN are expected to be applied as power supply devices.

FIG. 3 shows a high electron mobility transistor which is one of FETs using a nitride compound semiconductor according to the prior art. In this high electron mobility transistor, for example, on a substrate 1 such as a sapphire substrate, a buffer layer 2 made of GaN, an electron transit layer 3 made of undoped GaN, and an undoped Al _x which is thinner than the electron transit layer 3. A layer structure (heterojunction structure) is formed by sequentially stacking electron supply layers 4 made of Ga _1-x N (0 <x <1). On the electron supply layer 4, a source electrode S, a gate electrode G, and a drain electrode D are arranged in a plane (see Patent Document 1). In order to reduce the contact resistance between each electrode and the electron supply layer 4, an n-GaN contact region 5 doped with an n-type impurity at a high concentration is provided.

  Here, at the heterojunction interface between the electron transit layer 3 and the electron supply layer 4, a piezoelectric field is generated due to the piezoelectric effect based on crystal distortion, and a two-dimensional electron gas 6 is formed immediately below the junction interface between the two. The

  Further, as shown in FIG. 4, there is also a high electron mobility transistor in which the intermediate layer 8 made of AlN is disposed between the electron supply layer 4 and the electron transit layer 3 in the high electron mobility transistor shown in FIG. . In this case, an intermediate layer 8 made of a nitride-based compound semiconductor having a band gap energy larger than that of the electron supply layer 4 is disposed between the electron transit layer 3 and the electron supply layer 4, so that a higher density can be achieved. A two-dimensional electron gas 6 is formed, and the resistance of the electron transit layer 3 can be lowered.

  When the source electrode S and the drain electrode D of the high electron mobility transistor having such a configuration are operated, electrons supplied to the electron transit layer 3 travel at a high speed in the two-dimensional electron gas 6 and move to the drain electrode D. To do. At this time, when the voltage applied to the gate electrode G is changed, the thickness of the depletion layer formed immediately below the gate electrode G is changed, so that the electron travel layer 3 between the source electrode S and the drain electrode D travels. Electronic control can be performed.

JP 2003-179082 A

  In the high electron mobility transistor in which the intermediate layer 8 is inserted between the electron supply layer 4 and the electron transit layer 3 as shown in FIG. 4, the process from the source electrode S (or drain electrode D) to the electron transit layer 3 is performed. In the current path, the intermediate layer 8 having a large resistance, specifically, AlN as an insulator is inserted, so that the contact resistance is apparently increased, and the resistance between the source and the drain is increased. There was a problem to do.

Therefore, as a method of reducing the contact resistance, a method of performing ion implantation of Si or the like in a specific region corresponding to the contact region and performing a heat treatment to reduce the resistance can be considered. However, the ion implantation into the nitride is very difficult to activate the implanted ions, and a sufficient low resistance layer cannot be realized. In some cases, recovery from damage caused by ion implantation becomes a problem.
In addition, since the band gap energy of the intermediate layer 8 is large, there is a problem that a rising offset voltage is generated when the high electron mobility transistor is driven.

  Therefore, the problem to be solved by the present invention is that even in the high electron mobility transistor as shown in FIG. 4 in which the intermediate layer 8 is disposed between the electron supply layer 4 and the electron transit layer 3, the source-drain connection is performed. It is an object of the present invention to provide a device that has a low resistance and hardly generates a rising offset voltage.

  The invention according to claim 1 is a high electron mobility transistor including a heterojunction structure of an electron transit layer made of a nitride compound semiconductor and an electron supply layer and a contact region in contact with an electrode, and the electron transit layer and the electron supply. An intermediate layer made of a nitride compound semiconductor having a larger band gap energy than the electron supply layer is provided between the layers, and the contact region is in contact with the electron transit layer.

  According to a second aspect of the present invention, in the high electron mobility transistor according to the first aspect, the contact region is disposed so as to be in contact with a two-dimensional electron gas existing in the electron transit layer. .

The invention according to claim 3 is the high electron mobility transistor according to claim 1 or 2, wherein the electron transit layer is GaN, and the electron supply layer is Al _x Ga ₁ -xN (0 <x <1). The intermediate layer is characterized by Al _y Ga _1-y N (0 <y ≦ 1) and x <y.

The invention according to claim 4 is the high electron mobility transistor according to any one of claims 1 to 3, wherein the contact region is In _z Ga _1-z N (0 <z ≦ 1). Features.

The invention according to claim 5 is the high electron mobility transistor according to any one of claims 1 to 4, wherein the conductivity type of the contact region is n-type and the carrier concentration is 1 × 10 ¹⁶ / cm. It is characterized by ³ or more.

The invention according to claim 6 is the high electron mobility transistor according to claim 4 or claim 5, wherein the In composition z of In _z Ga _{1 -z} N constituting the contact region is from the electrode to the electron transit layer. It is characterized by decreasing in the direction of.

  The high electron mobility transistor according to the present invention has a low resistance between the source and the drain, and does not generate a rising offset voltage when driven.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of an embodiment of a high electron mobility transistor according to the present invention.
For example, a buffer layer 2 is formed on a substrate 1 such as a sapphire substrate, and a heterojunction structure in which an electron transit layer 3 and an electron supply layer 4 that is thinner than the electron transit layer 3 are sequentially laminated is formed on the buffer layer 2. Has been. A source electrode S, a gate electrode G, and a drain electrode D are arranged in a plane. Here, reference numeral 8 denotes an intermediate layer disposed between the electron transit layer 3 and the electron supply layer 4.

  Here, the buffer layer 2, the electron transit layer 3, and the electron supply layer 4 are made of a nitride compound semiconductor, and the band gap energy of the nitride compound semiconductor constituting the electron supply layer 4 is It is larger than the band gap energy of the nitride-based compound semiconductor to be formed. Reference numeral 11 denotes a contact region formed in a region where the source electrode S and the drain electrode D are formed, and made of a nitride compound semiconductor doped with an n-type impurity at a high concentration.

  Since nitride compound semiconductors having different compositions have different lattice constants, a piezoelectric field is generated at the heterojunction interface between the electron transit layer 3 and the electron supply layer 4 by a piezoelectric effect based on crystal distortion. A two-dimensional electron gas 6 is formed immediately below the joint interface between the two.

  When the source electrode S and the drain electrode D are operated by the action of the two-dimensional electron gas 6, the electrons supplied to the electron transit layer 3 travel at a high speed in the two-dimensional electron gas 6 and move to the drain electrode D. At this time, if the voltage applied to the gate electrode G is changed, the thickness of the depletion layer immediately below the gate electrode G changes, so that the electrons traveling in the electron transit layer 3 between the source electrode S and the drain electrode D are controlled. Can be performed.

  In the high electron mobility transistor according to the present invention, an intermediate layer 8 is disposed between the electron transit layer 3 and the electron supply layer 4. The magnitude of the band gap energy of the intermediate layer 8 is larger than the band gap energy of the electron supply layer 4. Therefore, the magnitude of the piezoelectric effect based on crystal distortion at the heterojunction interface between the intermediate layer 8 and the electron transit layer 3 is determined at the heterojunction interface between the electron transit layer 3 without the intermediate layer 8 and the electron supply layer 4. It becomes larger than the magnitude of the piezoelectric effect based on crystal distortion.

  Therefore, the concentration of the two-dimensional electron gas 6 immediately below the heterojunction interface between the intermediate layer 8 and the electron transit layer 3 is the heterojunction between the electron transit layer 3 and the electron supply layer 4 where the intermediate layer 8 is not disposed. It becomes larger than the concentration of the two-dimensional electron gas 6 immediately below the interface.

  Furthermore, the high electron mobility transistor according to the present invention is characterized in that a contact region 11 for forming an ohmic junction with the source electrode S and the drain electrode D is in contact with the electron transit layer 3.

  The contact region 11 is in contact with the electron transit layer 3, thereby contacting the two-dimensional electron gas existing in the electron transit layer 3, so that electrons traveling in the two-dimensional electron gas 6 move directly to the contact region 11. can do. That is, the contact region 11 is directly electrically connected to the electron transit layer 3. Therefore, the resistance between the source and the drain does not increase despite the presence of the intermediate layer 8. Furthermore, when the band gap energy of the contact region 11 is smaller than the band gap energy of the electron transit layer 3, electrons traveling in the two-dimensional electron gas 6 are likely to move to the contact region 11, thereby further increasing the resistance. Can be suppressed.

  In order to contact the contact region 11 and the electron transit layer 3, for example, a recess 10 (see FIG. 2) that penetrates the intermediate layer 8 and reaches the electron transit layer 3 is provided. The contact region 11 may be embedded. At this time, embedding is performed so as to contact the two-dimensional electron gas 6 existing in the electron transit layer 3.

As specific nitride compound semiconductors of the electron transit layer 3, the electron supply layer 4, and the intermediate layer 8, GaN, Al _x Ga _1-x N (0 <x <1), and AlN can be exemplified. This is because such a nitride-based compound semiconductor satisfies the above requirements. Further, when the intermediate layer 8 is made of AlN, the property of the layer is close to that of an insulator, so that it is significant that the contact region 11 and the electron transit layer 3 are in contact as in the present embodiment.

  Here, in order to exhibit the effect of increasing the concentration of the two-dimensional electron gas 6 by disposing the intermediate layer 8 when using the above specific nitride-based semiconductor, the thickness of the electron supply layer 4 is increased. It is necessary to set the thickness to an optimum thickness. That is, if the electron supply layer 4 is too thin, sufficient electrons are not supplied from the electron supply layer 4 to the electron transit layer 3, so that the concentration of the two-dimensional electron gas decreases. On the other hand, when the thickness of the electron supply layer 4 is too thick, dislocations easily enter the electron supply layer 4. Considering these two points, the upper limit of the thickness of the electron supply layer 4 is 100 nm, and the lower limit is 10 nm. Note that the optimum thickness of the electron supply layer 4 is about 30 nm.

In addition, In _z Ga _1-z N (0 <z ≦ 1) can be exemplified as a specific nitride-based compound semiconductor in the contact region 11 in this case. By using this material, the band gap energy of the contact region 11 can be made smaller than the band gap energy of the electron transit layer 3 made of GaN. Thereby, the electrons that have traveled in the two-dimensional electron gas 6 can easily move to the contact region 11.

The contact region 11 made of In _z Ga _1-z N (0 <z ≦ 1) is preferably n-type and has a carrier concentration of 1 × 10 ¹⁶ / cm ³ or more. By doing so, an offset voltage is less likely to be generated.

Further, in order to make it difficult for the offset voltage to be generated, it is desirable that the In composition Ga of In _z Ga _{1 -z} N constituting the contact region 11 on the electrode side in contact with the contact region 11 is an inclined composition. . By doing so, the barrier between the contact region 11 and the electrode can be adjusted small.

  The InGaN In constituting the contact region 11 on the electrode side in contact with the contact region 11 has an inclined composition means that the contact region 11 in the part in contact with the source electrode S and the drain electrode D in FIG. The In composition of InGaN is a (0 <a ≦ 1), which means that the composition gradually decreases from the electrode toward the electron transit layer 3. Then, the decrease of the In composition stops at the position of the predetermined contact region 11 from the electrode with the composition being b (0 <b <a ≦ 1).

An embodiment of a high electron mobility transistor according to the present invention is shown in FIG. In this high electron mobility transistor, a buffer layer 2 made of a GaN layer having a thickness of 50 nm is formed on a substrate 1 such as a sapphire substrate, an electron transit layer 3 made of a GaN layer having a thickness of 400 nm, and a thickness of 30 nm. A heterojunction structure in which electron supply layers 4 made of undoped Al _0.2 Ga _0.8 N layers are sequentially stacked is formed on the buffer layer 2. A source electrode S, a gate electrode G, and a drain electrode D are arranged in a plane. An intermediate layer 8 made of AlN having a thickness of 1 nm is disposed between the electron transit layer 3 made of a GaN layer and the electron supply layer 4 made of an Al _0.2 Ga _0.8 N layer.

In this embodiment, since the intermediate layer 8 made of AlN having a larger band gap energy than the band gap energy of the electron supply layer 4 made of the Al _0.2 Ga _0.8 N layer is disposed, the intermediate layer 8 and the electron transit layer 3 The difference in crystal strain can be increased. Therefore, the concentration of the two-dimensional electron gas 6 immediately below the joint interface between the two can be increased.

  In Example 1, a recess 10 (see FIG. 2) that penetrates the electron supply layer 4 and the intermediate layer 8 and reaches the electron transit layer 3 is provided so that the contact region 11 and the electron transit layer 3 are in contact with each other. Then, the contact region 11 is disposed here. Thereby, the contact region 11 comes into contact with the electron transit layer 3 and is electrically connected to each other. In this state, the two-dimensional electron gas 6 present in the electron transit layer 3 is in contact.

  In the high electron mobility transistor having the above configuration, when the source electrode S and the drain electrode D are operated by the action of the two-dimensional electron gas 6, electrons supplied to the electron transit layer 3 are high-speed in the two-dimensional electron gas 6. It travels and moves to the drain electrode D. At this time, if the voltage applied to the gate electrode G is changed, the thickness of the depletion layer immediately below the gate electrode G changes, so that the electrons traveling between the source electrode S and the drain electrode D can be controlled. .

  Further, the contact region 11 is in contact with the electron transit layer 3 and is in contact with the two-dimensional electron gas 6 present in the electron transit layer 3. Therefore, the electrons that have traveled in the two-dimensional electron gas 6 can move directly to the contact region 11. Therefore, the resistance between the source and the drain does not increase despite the presence of the intermediate layer 8.

The high electron mobility transistor shown in FIG. 1 can be manufactured by the following steps.
1) First, on the sapphire substrate 1, ammonia (12 L / min) and TMGa (100 cm ³ / min) are used, and the degree of vacuum is 100 hPa, the growth temperature is 1100 ° C. and the thickness is 50 nm by MOCVD (Metal Chemical Vapor Deposition) method. A GaN layer (buffer layer 2) is formed, and further, TMGa (100 cm ³ / min) and ammonia (12 L / min) are used thereon, and a 400 nm thick GaN layer (electron transit layer) at a growth temperature of 1050 ° C. 3) is formed, TMAl (50 cm ³ / min), ammonia (12 L / min) is used, an undoped AlN layer (intermediate layer 8) having a thickness of 5 nm at a growth temperature of 1050 ° C., and further, TMAl ( ^{50cm 3 / min) TMGa (100cm} 3 / min), ammonia (12L / m using n), the undoped Al _0.2 Ga _0.8 N layer having a thickness of 30nm at a growth temperature of 1050 ° C. (carrier concentration of ^{1 × 10 16 / cm 3)} ( Fig. 2 was deposited an electron supply layer 4) (a) The indicated layer structure A ₀ was epitaxially grown.

2) Next, after depositing the SiO ₂ layer 9 on the epitaxial wafer using a plasma CVD apparatus, the gate portion is masked using photolithography and chemical etching, and openings are provided in portions to be the source and drain. A layer structure A ₁ is produced (FIG. 2B). Then, a recess 10 is formed using a mixed gas for etching such as methane / hydrogen / argon to produce a layer structure A ₂ (FIG. 2C). Here, the etching depth of the recess 10 is, for example, 50 nm, and is deep enough to penetrate the electron supply layer 4 and the intermediate layer 8 and reach the electron transit layer 3.

3) Next, a layer structure A _{3 in} which the Si-doped n-GaN contact region 11 is arranged in the recess 10 is produced (FIG. 2D). As an apparatus, an MOCVD apparatus was used, and a high doping concentration of 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ was set so that the thickness was about 100 nm. After implantation the contact region 11, after removing the undoped AlGaN layer (electron supply layer 4) on the SiO ₂ film 9 with hydrofluoric acid, again, to form an SiO ₂ film on the entire surface to a plasma CVD method again entire surface.

4) Then, patterning is performed to expose the surface of the n-GaN contact region 11 by opening the portion where the source electrode and the drain electrode are to be formed using the SiO ₂ film where the gate electrode is to be formed as a mask. Then, a Si-based alloy (thickness: 200 nm) was deposited thereon to form a source electrode S and a drain electrode D. Next, the mask is removed, and conversely, Pt / Au (thickness is 100 nm / thickness) using the SiO ₂ film that covers the source electrode S and the drain electrode D and has an opening in the portion to be the gate. 200 nm) is deposited to form the gate electrode G, and the field effect transistor shown in FIG. 1 is completed.

The high electron mobility transistor according to this example is the same as the high electron mobility transistor shown in FIG. 1 except for the contact region 11.
In of InGaN constituting the contact region 11 on the side in contact with the electrode of the high electron mobility transistor according to this example has a gradient composition.

  That is, the In composition of InGaN constituting the contact region 11 in the portion in contact with the source electrode S and the drain electrode D is 0.5, but the composition gradually decreases from the electrode toward the electron transit layer 3. The composition of the mold.

  By doing so, the difference in the barrier at the junction of the source electrode S, the drain electrode D and the contact region 11 can be reduced to about 0.1 eV. Thereby, the resistance in the ohmic junction is lowered.

  In order to realize such a gradient composition, only step 3) needs to be changed in the manufacturing process of the high electron mobility transistor according to Example 1 consisting of steps 1) to 4). That is, TMIn may be used to fill the contact region 11 with the MOCVD apparatus, and the flow rate may be gradually decreased.

  The field effect transistor shown in FIG. 1 does not include an intermediate layer having a large resistance in the current path from the source electrode S (drain electrode) to the electron transit layer 3, so that the resistance between the source and drain can be lowered. it can. Specifically, the on-resistance is reduced to 1/3 compared to the conventional structure shown in FIG. 4, and the rising offset voltage caused by the AlN arrangement can be eliminated. In addition, the maximum current value was improved to 1.5 times the conventional value, and the effect of this structure was confirmed.

It is sectional drawing which shows embodiment of the high electron mobility transistor based on this invention. 1 is a layer structure during manufacturing of a high electron mobility transistor according to the present invention, (a) is A ₀ , (b) is A ₁ , (c) is A ₂ , and (d) is a sectional view of A ₃ . . It is sectional drawing which shows one of the high electron mobility transistors concerning a prior art. It is sectional drawing which shows another one of the high electron mobility transistors concerning a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Electron travel layer 4 Electron supply layer 5 Contact region 6 Two-dimensional electron gas 7 Concave portion 8 Intermediate layer 9 SiO ₂ film 10 Concave portion 11 Contact region

Claims (5)

An electron transit layer in which a two-dimensional electron gas is formed, an electron supply layer that supplies electrons to the electron transit layer, and a band gap energy between the electron transit layer and the electron supply layer and higher than that of the electron supply layer. A nitride compound semiconductor layer formed by heterojunction with a large intermediate layer;
  A source electrode and a drain electrode;
  A contact region formed in the nitride-based compound semiconductor layer so that the source and drain electrodes are in contact with the electron transit layer;
With
  The contact region is made of In. _z Ga _1-z A high electron mobility transistor including N (0 <z ≦ 1), wherein a composition z of In decreases from the source electrode and the drain electrode toward the electron transit layer. In the contact region, the decrease in the composition z of In stops at a predetermined position from the source electrode and the drain electrode.
The high electron mobility transistor according to claim 1. The contact region is in contact with a two-dimensional electron gas existing in the electron transit layer.
The high electron mobility transistor according to claim 1 . The electron transit layer is GaN, the electron supply layer is _{Al x Ga 1-x N (} 0 <x <1), the intermediate layer includes _{Al y Ga 1-y N (} 0 ≦ y ≦ 1), and, x <y
The high electron mobility transistor according to any one of claims 1 to 3 . The contact region has an n-type conductivity and a carrier concentration of 1 × 10 ¹⁶ / cm ³ or more.
The high electron mobility transistor according to any one of claims 1 to 4 .

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