JP5510325B2 - Field effect transistor - Google Patents

Description

  The present invention relates to a field effect transistor.

  Group III nitride compound semiconductors such as GaN have a large band gap, high breakdown field strength, and high electron mobility. In recent years, research and development of a field effect transistor capable of operating at high withstand voltage and at high speed using the group III nitride compound semiconductor as a constituent material has been advanced. For example, Non-Patent Document 1 (Shinichi Iwakami et al., “AlGaN / GaN Heterostructure Field-Effect Transistors (HFETs) on Si Substrates for Large-Current Operation”, Jpn. J. Appl. Phys. , Vol. 43, No. 7A, pp. L831-L833, 2004) and Patent Document 1 (Japanese Patent Laid-Open No. 2007-31740). In general, the distance between the source electrode and the drain electrode may be increased in order to improve the breakdown voltage, but there is a problem that the chip size is increased when the distance between the source electrode and the drain electrode is increased.

FIG. 1 is a cross-sectional view schematically showing the structure of the field effect transistor disclosed in Non-Patent Document 1. As shown in FIG. 1, in this field effect transistor, an AlN layer 1102, a GaN / AlN superlattice layer 1103, an undoped GaN layer 1104, and an undoped AlGaN layer 1105 are stacked on the (111) plane of a silicon substrate 1101. It has a structure. A source electrode 1106 and a drain electrode 1107 are formed on the AlGaN layer 1105. The source electrode 1106 and the drain electrode 1107 are Ti / Al electrodes that are in ohmic contact with the AlGaN layer 1105. A silicon oxide (SiOx) film 1108 is formed on the source electrode 1106, the drain electrode 1107, and the AlGaN layer 1105.
On the AlGaN layer 1105, a gate electrode 1109 is formed in the opening of the silicon oxide film 1108, and a protective film (SiNx film) 1110 covering the gate electrode 1109 is formed. Gold plating layers 1111 and 1111 are formed on the upper surface of the source electrode 1106 and the upper surface of the drain electrode 1107, respectively.
In the field effect transistor of FIG. 1, the distance between the source electrode 1106 and the drain electrode 1107 is about 16 μm, which is large. Such a structure makes it possible to achieve a breakdown voltage of 350 V or higher.
Shinichi Iwakami, Masataka Yanagihara, Osamu Machida, Emiko Chino, Nobuo Kaneko, Hirokazu Goto and Kohji Ohtsuka, "AlGaN / GaN Heterostructure Field-Effect Transistors (HFETs) on Si Substrates for Large-Current Operation", Japanese Journal of Applied Physics, Vol .43, No.7A, pp.L831-L833, 2004. JP 2007-31740 A

However, even if the distance between the source electrode 1106 and the drain electrode 1107 is increased, the electric field strength distribution in the channel region is not uniform due to the influence of the fixed charges at the interface between the silicon oxide film 1108 and the AlGaN layer 1105 and the vicinity thereof. It becomes. As a result, the electric field concentrates on the drain end of the gate electrode 1109 (the end of the gate electrode 1109 on the drain electrode 1107 side). Therefore, the maximum electric field strength expected from the physical property value of the dielectric breakdown voltage of GaN cannot be obtained as the average electric field strength between the gate electrode 1109 and the drain electrode 1107, and the distance between the source electrode 1106 and the drain electrode 1107 is increased. However, there is a problem that it is difficult to increase the breakdown voltage.
Further, in the field effect transistor of FIG. 1, the distance between the source electrode 1106 and the drain electrode 1107 is about 16 μm, and there is a problem that the chip size becomes large.
In view of the above, the present invention provides a field effect transistor capable of realizing a high breakdown voltage and a reduction in chip size.

According to the present invention, a substrate;
A drift layer formed on the substrate;
An electron barrier layer formed above the drift layer;
An electron transit layer formed on the electron barrier layer;
A gate electrode formed on the electron transit layer;
An electron conduction region on one side of the gate electrode in the gate length direction and extending from the electron transit layer to a region closer to the substrate than the electron barrier layer;
A source electrode on the other side in the gate length direction of the gate electrode and formed on the electron transit layer;
A drain electrode electrically connected to one end of the electron conducting region on the substrate side through the drift layer;
A field effect transistor is provided.

  According to the present invention, it is possible to provide a field effect transistor capable of increasing the breakdown voltage and reducing the chip size.

  The above-described object and other objects, features, and advantages will become more apparent from the preferred embodiments described below and the accompanying drawings.

It is sectional drawing which shows the structure of a field effect transistor roughly. 1 is a cross-sectional view schematically showing the structure of a field effect transistor according to a first embodiment of the present invention. It is sectional drawing which shows roughly the structure of the field effect transistor which is a modification of 1st Embodiment. It is sectional drawing which shows roughly the structure of the field effect transistor which is a modification of 1st Embodiment. It is sectional drawing which shows roughly the structure of the field effect transistor of 2nd Embodiment which concerns on this invention. It is sectional drawing which shows roughly the structure of the field effect transistor which is a modification of 2nd Embodiment. It is sectional drawing which shows roughly the structure of the field effect transistor of 3rd Embodiment concerning this invention. It is sectional drawing which shows roughly the structure of the field effect transistor which is a modification of 3rd Embodiment. It is sectional drawing which shows roughly the structure of the field effect transistor of 4th Embodiment concerning this invention. It is sectional drawing which shows roughly the structure of the field effect transistor which is a modification of 4th Embodiment. It is sectional drawing which shows roughly the structure of the field effect transistor of the modification of this invention. It is sectional drawing which shows roughly the structure of the field effect transistor concerning 1st Embodiment. It is a top view which shows roughly the structure of the field effect transistor of the modification of this invention. It is a top view which shows roughly the structure of the field effect transistor of the modification of this invention. It is a top view which shows roughly the structure of the field effect transistor of the modification of this invention.

Embodiments according to the present invention will be described below with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and detailed description thereof is appropriately omitted so as not to overlap.
Moreover, this application claims the priority on the basis of Japanese application Japanese Patent Application No. 2008-203493 for which it applied on August 6, 2008, and takes in those the indications of all here.

(First embodiment)
FIG. 2 is a sectional view schematically showing the structure of the field effect transistor 10 of the first embodiment according to the present invention. The field effect transistor 10 includes a high-concentration n-type semiconductor layer 102, a drift layer 103, an electric field relaxation layer 104, an electron barrier layer 105, an electron transit layer 106, and an electron supply layer 107 stacked in this order on a substrate 101. It has a structure. An insulating film 110 is formed on the stacked structure, and a gate insulating film 111 and a gate electrode 112 are formed in an opening formed in the insulating film 110. The gate insulating film 111 has a function of suppressing gate leakage current.

  On one side of the left and right sides of the gate electrode 112 (both sides in the direction parallel to the substrate surface) (in other words, one side of the gate electrode 112 in the gate length direction), an etching processing surface formed in the stacked structure is formed. An electron conduction region 108 is formed. The electron conduction region 108 is provided so as to extend from one end of the electron transit layer 106 to a region closer to the substrate 101 than the p-type electron barrier layer 105. On the other side of the left and right sides of the gate electrode 112 (the other side of the gate electrode 112 in the gate length direction), a source electrode 109 is formed on the electron supply layer 107.

  A drain electrode 114 is formed on the back surface of the substrate 101. The drain electrode 114 is electrically connected to one end of the electron conduction region 108 on the substrate side through the substrate 101, the high concentration n-type semiconductor layer 102, and the drift layer 103.

  The upper surface of the electron transit layer 106 is heterojunction to the electron supply layer 107, and when the field effect transistor 10 is operated, two-dimensional electron gas is present at and near the heterojunction interface in response to application of a bias voltage to the gate electrode. A channel region is formed. At this time, electrons injected from the source electrode 109 can move to the drain electrode 110 through the channel region and the electron conduction region 108. The electron transit layer 106 is formed continuously in one growth step without going through a process step such as photolithography or dry etching.

The electron supply layer 107 is a layer that is heterojunction with the upper surface of the electron transit layer 106 and is made of a group III nitride compound semiconductor such as GaN, InN, or AlN. The electron supply layer 107 is made of, for example, In _a Al _b Ga ₁ -abN (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1).
In order to supply electrons from the electron supply layer 107 to the electron transit layer 106, the electron supply layer 107 is made of a material or composition having a smaller electron affinity than the electron transit layer 106. In the field effect transistor 10 of the first embodiment, it is possible to generate two-dimensional electron gas at and near the heterojunction interface between the electron transit layer 106 and the electron supply layer 107 mainly by the piezo effect and the spontaneous polarization effect. Yes. For example, when the AlGaN layer (electron supply layer) 107 is heterojunction with the upper surface of the undoped GaN layer (electron transit layer) 106, positive space fixed charge is generated at the heterojunction interface due to both spontaneous polarization and piezoelectric polarization. Then, electrons are attracted. The attracted electrons form a two-dimensional electron gas on the GaN layer side of the heterojunction interface. Note that by introducing an n-type impurity such as Si, S, Se, or O into the electron supply layer 107 having a larger band gap than the electron transit layer 106, the concentration of the two-dimensional electron gas at the heterojunction interface and its vicinity is introduced. Can also be adjusted (modulation doping).

The electron transit layer 106 may be made of, for example, a group III nitride compound semiconductor such as GaN, InN, or AlN. Electron transit layer 106 is composed of, for _example, a _{In c Al d Ga 1- c-} d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1, c + d ≦ 1). An n-type impurity such as Si, S, Se, or O, or a p-type impurity such as beryllium (Be), carbon (C), or magnesium (Mg) may be added to the electron transit layer 106. However, if the impurity concentration in the electron transit layer 106 becomes too high, the mobility of electrons decreases due to the influence of Coulomb scattering, so the impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The electron barrier layer 105 is a p-type nitride semiconductor layer having an acceptor concentration of 1 × 10 ¹³ cm ⁻² or more in terms of surface density. Examples of the p-type impurity introduced into the electron barrier layer 105 at a high concentration include Be, C, and Mg. Examples of the constituent material of the electron barrier layer 105 include a group III nitride such as GaN, InN, and AlN. A physical compound semiconductor is mentioned. The concentration of the p-type impurity introduced into the electron barrier layer 105 can be set to a desired value. However, in order to maintain the formation of a potential barrier against electrons in a high voltage region, 1 × 10 ¹⁸ cm ⁻³ or more It is desirable that

The electric field relaxation layer 104 is composed of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). In order to suppress punch-through and obtain high breakdown voltage performance, the composition of the electric field relaxation layer 104 is controlled so that negative polarization charges are distributed almost uniformly within the electric field relaxation layer 104. When the upper surface of the electric field relaxation layer 104 is a gallium surface that is a group III surface, the electric field is reduced by gradually or stepwise decreasing the Al composition ratio y of the electric field relaxation layer 104 from the substrate 101 side toward the source electrode 109 side. Negative polarization charges can be distributed substantially uniformly in the laminating layer 104 in the stacking direction. Alternatively, by gradually or stepwise increasing the In composition ratio x of the electric field relaxation layer 104 from the substrate 101 side toward the source electrode 109 side, negative polarization charges are generated in the lamination direction in the electric field relaxation layer 104. It can also be distributed almost uniformly. Alternatively, the Al composition ratio y of the electric field relaxation layer 104 decreases gradually or stepwise from the substrate 101 side toward the source electrode 109 side, and the In composition ratio x of the electric field relaxation layer 104 decreases from the substrate 101 side to the source electrode. The negative polarization charge may be distributed substantially uniformly in the stacking direction inside the electric field relaxation layer 104 by increasing gradually or stepwise toward the 109 side.

  Since the electric field relaxation layer 104 has such a composition, the electric field relaxation layer 104 has an energy band structure in which the conduction band and the valence band are bent so as to form a convex shape toward the vacuum level due to the piezoelectric effect and the spontaneous polarization effect. Since the convex energy band is formed with fixed charges due to the piezoelectric effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength. Therefore, punch-through can be suppressed, and the pressure resistance performance can be improved.

Examples of the n-type impurity introduced into the electric field relaxation layer 104 include silicon (Si), sulfur (S), selenium (Se), and oxygen (O). The n-type impurity concentration can be set to a desired value, but is preferably 1 × 10 ¹⁸ cm ⁻³ or less in order to relax the electric field. In particular, in order to ensure high breakdown voltage performance, the n-type impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The drift layer 103 may be made of a group III nitride compound semiconductor such as GaN, InN, or AlN. Examples of the n-type impurity introduced into the drift layer 103 include Si, S, Se, and O. The impurity concentration can be set to a desired value, but is preferably 1 × 10 ¹⁸ cm ⁻³ or less in order to reduce electric field concentration. In particular, when the pressure resistance is increased, the concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The high-concentration n-type semiconductor layer 102 may be made of a group III nitride compound semiconductor into which an n-type impurity such as Si, S, Se, or O is introduced at a high concentration. Examples of the group III nitride compound semiconductor include GaN, InN, and AlN. The impurity concentration can be set to a desired value, but is preferably a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more in order to reduce the resistance. However, if the substrate 101 has a sufficiently low resistance, the formation of the high-concentration n-type semiconductor layer 102 may be omitted.

  In this embodiment, a conductive group III nitride compound semiconductor substrate made of GaN, AlN, or the like is used as the substrate 101, but the substrate 101 is not limited to this. For example, a silicon substrate or a silicon carbide substrate may be used for the substrate 101. In order to provide conductivity, it is desirable to add an n-type impurity such as Si, S, Se, or O to the substrate 101.

  As shown in FIG. 2, the gate electrode 112 includes a protrusion protruding in the direction of the electron transit layer 106 (substrate 101 side), and the source electrode 109 side and the electron conduction region 108 from the protrusion on the gate insulating film 111. And a flange extending to each side. The flange extending to the electron conductive region 108 side of the gate electrode 112 is longer than the flange extending to the source electrode 109 side of the gate electrode 112. Thereby, the electric field concentration in the vicinity of the gate electrode 112 can be reduced.

  The gate electrode 112 only needs to be made of a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, and may have a structure in which a plurality of metal layers are stacked. The gate electrode 112 may be formed using a semiconductor material that is in Schottky contact with the base electron supply layer 107 instead of a metal material. However, this semiconductor material is preferably a material that does not react with the insulating film 111 and the protective film 113.

The manufacturing method of the field effect transistor 10 includes the following basic steps (a) to (h).
(A) A high-concentration n-type semiconductor layer 102, a drift layer 103, an electric field relaxation layer 104, an electron barrier layer 105, an electron on a substrate 101 by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxial growth (MBE). A step of continuously epitaxially growing a laminated structure including a plurality of compound semiconductor layers constituting the traveling layer 106 and the electron supply layer 107 in this order.
(B) The stacked structure is etched on one of the left and right sides of the region where the gate electrode 112 is to be formed, and extends from one end of the electron transit layer 106 to a region closer to the substrate 101 than the electron barrier layer 105. Forming an etched surface.
(C) A step of forming the electron conductive region 108 on the etched surface.
(D) A step of forming the source electrode 109 via the electron supply layer 107 on the electron transit layer 106 on the other of the left and right sides of the region where the gate electrode 112 is to be formed.
(E) A step of forming the drain electrode 114 on the back surface of the substrate 101.
(F) A step of forming the patterned insulating film 110.
(G) A step of forming the gate insulating film 111 and the gate electrode 112 in the opening of the insulating film 110 on the electron transit layer 106.
(H) A step of forming a protective film 113 that covers the entire element except a part of the electrode surface.

In the step (a), it is preferable that the high concentration n-type semiconductor layer 102, the drift layer 103, the electric field relaxation layer 104, the electron barrier layer 105, the electron transit layer 106, and the electron supply layer 107 are continuously grown.
The electron conduction region 108 is located on the opposite side of the source electrode 109 with the gate electrode 112 interposed therebetween in plan view from the substrate surface side.
In the present embodiment, the electron conduction region 108 extends from the electron supply layer 107 side to the drift layer 103 side, one end is in contact with the electron supply layer 107 and the electron transit layer 106, and the other end is an electron. It is in contact with a region (in this embodiment, the drift layer 103) located on the substrate side with respect to the barrier layer. More specifically, the electron conduction region 108 is provided in contact with the electron supply layer 107, the electron transit layer 106, the electron barrier layer 105, and the drift layer 103. The electron conduction region 108 is formed up to the middle of the thickness of the drift layer 103.
The electron conductive region 108 can be formed, for example, by introducing an n-type impurity into the laminated structure from the etched surface of the laminated structure and activating the introduced n-type impurity by heat treatment (see FIG. 12). ). The etched surface can be obtained by dry etching the laminated structure on the substrate 101. For example, the electron conduction region 108 can be formed by ion-implanting n-type impurities such as silicon into the etched surface and activating the implanted ions by heat treatment.
Alternatively, the electron conduction region 108 can be formed by depositing amorphous or polycrystalline silicon on the etched surface by, for example, CVD, and then diffusing the deposited silicon into a laminated structure by heat treatment (FIG. 12). reference). Note that not only the impurity diffusion region in which silicon is diffused by the heat treatment but also silicon that is not diffused in the stacked structure forms the electron conductive region 108 as a conductive film. Silicon may be solid-phase diffused on the etched surface.
Alternatively, the electron conductive region 108 may be formed by forming a metal conductive film on the etched surface of the laminated structure, for example, by sputtering (see FIG. 12). Here, it is desirable to cause the semiconductor layer constituting the stacked structure and the metal conductive film to react with each other by heat treatment. Metal conductive films are tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), gold (Au), tantalum (Ta), What is necessary is just to comprise with 1 type, or 2 or more types of metal materials selected from the group which consists of zirconium (Zr) and yttrium (Y). It is preferable to form a metal conductive film in ohmic contact on the etched surface.
Alternatively, the electron conductive region 108 may be formed by re-growing a compound semiconductor layer such as an n-type GaN layer on the etched surface of the stacked structure by the MOVPE method or the MBE method (see FIG. 2).

  In the present embodiment, the electron conductive region 108 is formed on the etched surface of the laminated structure. Alternatively, the electron conduction region 108 may be formed by ion-implanting n-type impurities into the stacked structure and performing heat treatment from the surface of the stacked structure to a depth reaching the region of the drift layer 103 (see FIG. 2). The acceleration voltage at the time of ion implantation is controlled so that the implantation depth of n-type impurity ions reaches the drift layer 103.

  After the formation of the electron conduction region 108, a source electrode 109 that is in ohmic contact with the electron supply layer 107 is formed by a lift-off process (step (d)). More specifically, a resist pattern is formed on the stacked structure using photolithography, and then a metal layer is formed on the resist pattern and the stacked structure by sputtering. Then, the electrode pattern of the source electrode 109 can be formed by removing the resist pattern and the metal material on the resist pattern at the same time. The drain electrode 114 is formed by forming a single-layer or multilayer metal film by, for example, a vacuum deposition method.

  Each of the source electrode 109 and the drain electrode 114 includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), or gold (Au). As long as it is made of a metal material, it may have a structure in which a plurality of metal layers are laminated.

  Thereafter, an insulating film is formed so as to cover the entire laminated structure, and this insulating film is patterned to form an insulating film 110 having an opening as shown in FIG. Further, by performing dry etching on the electron supply layer 107 using the insulating film 110 as a mask, a recess (recess structure) is formed in the electron supply layer 107. Then, a gate insulating film 111 and a gate electrode 112 having a T-shaped cross-sectional shape are formed in the recess of the electron supply layer 107 and the opening of the insulating film 110 (step (g)).

  In the present embodiment, as a preferred configuration, a configuration is adopted in which the length of the collar portion on the electron conductive region 108 side of the gate electrode 112 is longer than the collar portion of the gate electrode 112 on the source electrode 109 side. Is not to be done. The length of the collar portion of the gate electrode 112 on the electron conducting region 108 side is equal to the length of the collar portion of the gate electrode 112 on the source electrode 109 side, or the collar portion of the gate electrode 112 on the electron conducting region 108 side is the gate electrode. There may be a form shorter than the flange portion of 112 on the source electrode 109 side. However, if the butt portion on the source electrode 109 side of the gate electrode 112 is too long compared to the ridge portion on the electron conduction region 108 side of the gate electrode 112, the gain reduction due to the increase in the gate capacitance increases.

  After the formation of the gate electrode 112, a protective film 113 that covers the gate electrode 112 is formed on the stacked structure by a CVD method (step (h)). The insulating film 110, the gate insulating film 111, and the protective film 113 are made of, for example, a group consisting of silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti), and tantalum (Ta). What is necessary is just to comprise with the 1 type (s) or 2 or more types of selected oxide or nitride. Instead of an inorganic compound such as oxide or nitride, the protective film 113 may be formed of an organic insulator.

The effects exhibited by the field effect transistor 10 of the first embodiment are as follows.
The electron conduction region 108 is on the opposite side of the left and right sides of the gate electrode 112 from the source electrode 109 side, and extends from one end of the electron transit layer 106 to a region closer to the substrate 101 than the electron barrier layer 105. Yes. The drain electrode 114 is formed on the back surface of the substrate 101 so as to be electrically connected to one end of the electron conduction region 108 on the substrate 101 side through the drift layer 103 and the high-concentration n-type semiconductor layer 102. Therefore, in the drift layer 103, electrons as carriers flow from the electron conduction region 108 side toward the substrate 101.
Since current flows in the drift layer 103 perpendicularly to the surface of the semiconductor layer, the drift layer 103 is not easily affected by the fixed charge on the surface of the electron supply layer 107, and has a breakdown voltage close to the dielectric breakdown voltage of the drift layer 103 itself. can do.
In the transistor having such a structure, the potential can be reduced in the drift layer 103 and electric field concentration in the vicinity of the gate electrode 112 can be suppressed.
That is, the transistor of this embodiment can be configured such that the potential of the electron conduction region 108 is lower than the drain potential, the potential drops in the drift layer 103, and the electric field is concentrated. As described above, in the drift layer 103, a very high breakdown voltage can be secured and the electric field concentration in the vicinity of the gate electrode 112 can be suppressed because the potential of the electron conduction region 108 is lower than the drain potential. is there.
Therefore, as described in the background art, it is possible to reduce the chip size as compared with the case where the source electrode and the drain electrode are arranged at a large distance on the same plane in order to secure a withstand voltage. .

  In the drift layer 103, carriers flow from the electron conduction region 108 side toward the substrate 101, so that the electron movement path in the drift layer 103 is at the interface between the electron supply layer 107 and the insulating film 110 of the field effect transistor 10. Less susceptible to the generated fixed charge. Therefore, the electric field distribution in the movement path of electrons as carriers is likely to be uniform, and the maximum electric field strength close to the bulk value of the dielectric breakdown voltage can be secured, so that a small chip size can be realized and the breakdown voltage performance can be improved.

The withstand voltage performance of the field effect transistor 10 is that a voltage path between the source electrode 109 and the drain electrode 114 via the electric field relaxation layer 104 and the electron barrier layer 105 and an electron conduction region between the source electrode 109 and the drain electrode 114. 108 and the voltage path through the drift layer 103. In the present embodiment, as described above, in the electric field relaxation layer 104 made of the In _x Al _y Ga _1-xy N layer, one or both of the Al composition ratio y and the In composition ratio x change gradually or stepwise. Therefore, an energy band structure in which the conduction band and the valence band are bent toward the vacuum level by the piezo effect and the spontaneous polarization effect is formed inside the electric field relaxation layer 104. Since this convex energy band is formed with fixed charges due to the piezo effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength. Therefore, punch-through is suppressed, and a higher breakdown voltage can be achieved.

As shown in FIG. 2, the collar portion of the gate electrode 112 that extends from the opening of the insulating film 110 toward the electron conduction region 108 extends from the opening of the gate electrode 112 toward the source electrode 109. It is longer than the existing heel part. Thereby, the electric field concentration in the vicinity of the gate electrode 112 can be relaxed, and a high breakdown voltage can be achieved. In addition, since the electric field intensity distribution in the channel region is made uniform, current collapse can be suppressed. Here, the current collapse is a phenomenon in which when a large bias is applied to the drain electrode or the gate electrode, the resistance of the channel region increases and the drain current decreases.
Therefore, it is possible to provide a field effect transistor 10 having high-frequency characteristics using a channel of a two-dimensional electron gas, high breakdown voltage performance, and enabling a reduction in chip size.

(Modification of the first embodiment)
FIG. 3 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 10A, which is a modification of the first embodiment. The structure of the field effect transistor 10A is the same as that of the first embodiment except that the end of the electron conduction region 108 on the substrate 101 side reaches the field relaxation layer 104 but does not reach the drift layer 103. The structure of the transistor 10 is the same. A drain electrode 114 is formed on the back surface of the substrate 101. The drain electrode 114 is electrically connected to one end of the electron conduction region 108 on the substrate 101 side through the substrate 101, the high-concentration n-type semiconductor layer 102, the drift layer 103, and the electric field relaxation layer 104.
In this modification, an electric field relaxation layer 104 is interposed between the electron conduction region 108 and the drift layer 103. Therefore, the breakdown voltage performance of the field effect transistor 10A of the present modification depends on the voltage path through the electric field relaxation layer 104 and the electron barrier layer 105 between the source electrode 109 and the drain electrode 114, and the source electrode 109 and the drain electrode 114. It depends on the voltage path through the electron conduction region 108, the electric field relaxation layer 104, and the drift layer 103. As described above, the electric field relaxation layer 104 composed of the In _x Al _y Ga _1-xy N layer has a composition in which one or both of the Al composition ratio y and the In composition ratio x change gradually or stepwise. In the electric field relaxation layer 104, an energy band structure is formed in which the conduction band and the valence band are bent toward the vacuum level by the piezoelectric effect and the spontaneous polarization effect. Since this convex energy band is formed with fixed charges due to the piezo effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength. Therefore, the electric field strength in the drift layer 103 is relaxed by the electric field relaxation layer 104 interposed between the electron conduction region 108 and the drift layer 103, so that the breakdown voltage can be further improved.

(Modification 2 of the first embodiment)
FIG. 4 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 10B which is a modification of the first embodiment. The structure of the field effect transistor 10B has a potential control electrode 117 for controlling the potential of the electron conductive region 108 via a potential control insulating film (insulating film) 116 on the opposite side of the drift layer 103 of the electron conductive region 108. Is arranged.
The potential control insulating film 116 preferably contains at least one of aluminum, silicon, hafnium, zirconium, and tantalum titanium and at least one of oxygen and nitrogen.
In particular, the potential control insulating film 116 preferably has a dielectric constant of 6 or more from the viewpoint of securing a large capacitance C1 described later.
For example, as the potential control insulating film 116, it is preferable to use aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, or the like.
The thickness of the potential control insulating film 116 is preferably 10 nm or more from the viewpoint of preventing dielectric breakdown of the insulating film. Moreover, in order to suppress that the capacity | capacitance C1 becomes small, it is preferable that it is 400 nm or less.

In the field effect transistor having the potential control electrode 117 as in this modification, when the electron conduction region 108 is a metallic material, no current flows at the time of pinch-off, so the potential of the electron conduction region 108 is equal to the potential control electrode 117. And the capacitance C 1 between the electron conduction regions 108 and the ratio of the electron conduction region 108 and the capacitance C 2 of the high-concentration n-type semiconductor layer 102. For example, when the potential control electrode 117 is grounded, that is, 0 V, and the potential of the high-concentration n-type semiconductor layer 102 that is equal to the drain voltage is Vd, the potential Vc of the electron conduction region 108 is Vc = C2Vd / (C1- C2). That is, by setting the capacitance C1 between the potential control electrode 117 and the electron conduction region 108 to a value larger than the capacitance C2 between the electron conduction region 108 and the high-concentration n-type semiconductor layer 102, the potential Vc of the electron conduction region 108 is drained. The potential can be made much lower than the voltage Vd.
When the potential Vc of the electron conduction region 108 is lower than the drain voltage Vd, it is considered that a voltage drop occurs in the drift layer 103 (note that the potential of the high concentration n-type semiconductor layer 102 is approximately the same as the drain voltage Vd). is there).
Therefore, the electric field can be concentrated in the drift layer 103 having a dielectric breakdown voltage close to the physical property value (3 MV / cm) of the material constituting the drift layer 103, and the electric field concentration at the drain end of the gate electrode 112 can be suppressed. Therefore, the off breakdown voltage can be improved. Even when the electron conduction region is formed of a semiconductor material, the potential on the potential control insulating film 116 side of the electron conduction region 108 can be regarded as Vc, and the same effect can be expected.
Note that when the potential control electrode is connected to the gate electrode, the off breakdown voltage can be similarly improved. Furthermore, there is an effect of reducing the on-resistance, but on the other hand, there is a possibility that the gain is lowered due to an increase in the gate capacitance.

(Second Embodiment)
Next, a second embodiment according to the present invention will be described. FIG. 5 is a cross-sectional view schematically showing the structure of the field effect transistor 20 of the second embodiment.
In this field effect transistor 20, a buffer layer 215, a high-concentration n-type semiconductor layer 202, a drift layer 203, a field relaxation layer 204, an electron barrier layer 205, an electron transit layer 206, and an electron supply layer 207 are arranged in this order on a substrate 201. It has a laminated structure. An insulating film 210 is formed on the stacked structure, and a gate electrode 212 is formed in an opening formed in the insulating film 210.

On one side (one side in the gate length direction) of the left and right sides of the gate electrode 212 (both sides in the direction parallel to the substrate surface), an electron conduction region 208 is formed on the etched surface formed in the stacked structure. ing. The electron conduction region 208 is provided so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the p-type electron barrier layer 205. A source electrode 209 is formed on the electron supply layer 207 on the other of the left and right sides of the gate electrode 212.
A drain electrode 214 is formed on the high concentration n-type semiconductor layer 202 on the surface side of the substrate 201, and the drain electrode 214 conducts electrons through the high concentration n-type semiconductor layer 202 and the drift layer 203. The region 208 is electrically connected to one end on the substrate 201 side.

The upper surface of the electron transit layer 206 is heterojunction to the electron supply layer 207, and when the field effect transistor 20 is operated, a channel region of a two-dimensional electron gas is formed at and near the heterojunction interface. At this time, electrons injected from the source electrode 209 can move to the drain electrode 214 through the channel region and the electron conduction region 208.
The electron supply layer 207 is a layer heterojunction with the upper surface of the electron transit layer 206 and made of a group III nitride compound semiconductor such as GaN, InN, or AlN. The electron supply layer 207 is made of, for example, In _a Al _b Ga ₁ -abN (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1).
In order to supply electrons from the electron supply layer 207 to the electron transit layer 206, the electron supply layer 207 is made of a material or composition having a smaller electron affinity than the electron transit layer 206. Similar to the field effect transistor 10 of the first embodiment, the field effect transistor 20 of the second embodiment has a heterojunction between the electron transit layer 206 and the electron supply layer 207 mainly due to a piezo effect or a spontaneous polarization effect. Two-dimensional electron gas can be generated at and near the interface. Note that by introducing an n-type impurity such as Si, S, Se, or O into the electron supply layer 207 having a larger band gap than the electron transit layer 206, the concentration of the two-dimensional electron gas at the heterojunction interface and its vicinity is introduced. Can also be adjusted (modulation doping).

The electron transit layer 206 may be made of, for example, a group III nitride compound semiconductor such as GaN, InN, or AlN.
The electron transit layer 206 is composed of, for _example, a _{In c Al d Ga 1- c-} d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1, c + d ≦ 1).
In this embodiment, no impurity is added to the electron transit layer 206, but n-type impurities such as Si, S, Se, and O, beryllium (Be), carbon (C), or A p-type impurity such as magnesium (Mg) may be added. However, if the impurity concentration in the electron transit layer 206 becomes too high, the mobility of electrons decreases due to the influence of Coulomb scattering, so the impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The electron barrier layer 205 is a p-type nitride semiconductor layer having an acceptor concentration of 1 × 10 ¹³ cm ⁻² or more in terms of surface density. Examples of the p-type impurity introduced into the electron barrier layer 205 at a high concentration include Be, C, and Mg. Examples of the constituent material of the electron barrier layer 205 include a group III nitride such as GaN, InN, and AlN. A physical compound semiconductor is mentioned. The p-type impurity concentration introduced into the electron barrier layer 205 can be set to a desired value. However, in order to maintain the formation of a potential barrier against electrons in a high voltage region, 1 × 10 ¹⁸ cm ⁻³ or more It is desirable that

The electric field relaxation layer 204 is composed of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1). In order to suppress punch-through and obtain high breakdown voltage performance, the composition of the electric field relaxation layer 204 is controlled so that negative polarization charges are distributed almost uniformly within the electric field relaxation layer 204. In the case where the upper surface of the electric field relaxation layer 204 is a gallium surface that is a group III surface, the Al composition ratio y of the electric field relaxation layer 204 is gradually decreased from the substrate 201 side toward the source electrode 209 side. Inside, negative polarization charges can be distributed almost uniformly in the stacking direction. Alternatively, by gradually increasing the In composition ratio x of the electric field relaxation layer 204 from the substrate 201 side toward the source electrode 209 side, the negative polarization charge is substantially uniform in the stacking direction inside the electric field relaxation layer 204. It can also be distributed. Alternatively, the Al composition ratio y of the electric field relaxation layer 204 is gradually decreased from the substrate 201 side toward the source electrode 209 side, and the In composition ratio x of the electric field relaxation layer 204 is moved from the substrate 201 side toward the source electrode 209 side. Accordingly, the negative polarization charge may be distributed almost uniformly in the stacking direction inside the electric field relaxation layer 204 by increasing gradually or stepwise.

Since the electric field relaxation layer 204 has such a composition, it has an energy band structure in which the conduction band and the valence band are bent toward the vacuum level by the piezo effect and the spontaneous polarization effect. Since the convex energy band is formed with fixed charges due to the piezoelectric effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength. Therefore, punch-through can be suppressed, and the pressure resistance performance can be improved.
Examples of the n-type impurity introduced into the electric field relaxation layer 204 include silicon (Si), sulfur (S), selenium (Se), and oxygen (O). The n-type impurity concentration can be set to a desired value, but is preferably 1 × 10 ¹⁸ cm ⁻³ or less in order to relax the electric field. In particular, in order to ensure high breakdown voltage performance, the n-type impurity concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The drift layer 203 may be made of a group III nitride compound semiconductor such as GaN, InN, or AlN, for example. Examples of the n-type impurity introduced into the drift layer 203 include Si, S, Se, and O. The impurity concentration can be set to a desired value, but is preferably 1 × 10 ¹⁸ cm ⁻³ or less in order to reduce electric field concentration. In particular, when the pressure resistance is increased, the concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

  The high-concentration n-type semiconductor layer 202 may be made of a group III nitride compound semiconductor into which an n-type impurity such as Si, S, Se, or O is introduced at a high concentration. Examples of the group III nitride compound semiconductor include GaN, InN, and AlN. The impurity concentration can be set to a desired value, but is preferably a high concentration of 1 × 10 18 cm −3 or more in order to reduce the resistance.

  In this embodiment, a group III nitride compound semiconductor substrate such as GaN or AlN is used as the substrate 201, but the substrate 201 is not limited to this. For example, a silicon substrate, a sapphire substrate, or a silicon carbide substrate may be used for the substrate 201. The buffer layer 215 formed on the substrate 201 may be made of a group III nitride compound semiconductor such as AlN, GaN, or AlGaN. The buffer layer 215 may include a superlattice structure (for example, an AlGaN / GaN superlattice structure) that is lattice-matched to the upper surface of the substrate 201 or a composition modulation structure.

  As shown in FIG. 5, the gate electrode 212 protrudes in the direction of the electron transit layer 206 (substrate 201 side), and extends from the protrusion to the source electrode 209 side and the electron conduction region 208 side. And a buttock. The flange extending to the electron conductive region 208 side of the gate electrode 212 is longer than the flange extending to the source electrode 209 side of the gate electrode 212. Thereby, electric field concentration in the vicinity of the gate electrode 212 can be reduced.

The gate electrode 212 may be made of a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, and may have a structure in which a plurality of metal layers are stacked. The gate electrode 212 may be formed using a semiconductor material that is in Schottky contact with the base electron supply layer 207 instead of a metal material. However, this semiconductor material is preferably a material that does not react with the insulating film 210 or the protective film 213.
The manufacturing method of the field effect transistor 20 includes the following basic steps (a) to (h).
(A) A buffer layer 215, a high-concentration n-type semiconductor layer 202, a drift layer 203, an electric field relaxation layer 204, an electron barrier are formed on the substrate 201 by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). A step of continuously epitaxially growing each layer of a stacked structure including a plurality of compound semiconductor layers constituting the layer 205, the electron transit layer 206, and the electron supply layer 207 in this order.
(B) The stacked structure is etched on one of the left and right sides of the region where the gate electrode 212 is to be formed to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the electron barrier layer 205. Forming an etched surface.
(C) A step of forming an electron conductive region 208 on the etched surface.
(D) A step of forming the source electrode 209 via the electron supply layer 207 on the electron transit layer 206 on the other of the left and right sides of the region where the gate electrode 212 is to be formed.
(E) A step of forming a drain electrode 214 that is electrically connected to one end of the electron conduction region 208 on the substrate 201 side.
(F) A step of forming a patterned insulating film 210.
(G) A step of forming the gate electrode 212 in the opening of the insulating film 210 on the electron transit layer 206.
(H) A step of forming a protective film 213 that covers the entire element except a part of the electrode surface.

The electron conduction region 208 is located on the opposite side of the source electrode 209 with the gate electrode 212 interposed therebetween as viewed from the substrate surface side.
In the present embodiment, the electron conduction region 208 extends from the electron supply layer 207 side to the drift layer 203 side, one end is in contact with the electron supply layer 207, and the other end is in contact with the drift layer 203. Yes. More specifically, the electron conduction region 208 is provided in contact with the electron supply layer 207, the electron transit layer 206, the electron barrier layer 205, and the drift layer 203. The electron conduction region 208 is formed up to the middle of the thickness of the drift layer 203.
The electron conduction region 208 can be created by the same method as the electron conduction region 108 of the first embodiment. For example, the n-type impurity can be formed by introducing an n-type impurity into the laminated structure from the etched surface of the laminated structure and activating the introduced n-type impurity by heat treatment. The etched surface can be obtained by dry etching the laminated structure on the substrate 201. For example, the electron conduction region 208 can be formed by ion-implanting n-type impurities such as silicon into the etched surface and activating the implanted ions by heat treatment. Alternatively, the electron conduction region 208 can be formed by depositing amorphous or polycrystalline silicon on the etched surface by, for example, CVD, and then diffusing the deposited silicon into a laminated structure by heat treatment. Note that not only the impurity diffusion region in which silicon is diffused by the heat treatment but also silicon not diffused in the stacked structure constitutes the electron conductive region 208 as a conductive film. Silicon may be solid-phase diffused on the etched surface.

  Alternatively, the electron conductive region 208 may be formed by forming a metal conductive film on the etched surface of the laminated structure, for example, by sputtering. Here, it is desirable to cause the semiconductor layer constituting the stacked structure and the metal conductive film to react with each other by heat treatment. Metal conductive films are tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), gold (Au), tantalum (Ta), What is necessary is just to comprise with 1 type, or 2 or more types of metal materials selected from the group which consists of zirconium (Zr) and yttrium (Y). It is preferable to form a metal conductive film in ohmic contact on the etched surface.

Alternatively, the electron conductive region 208 may be formed by re-growing a compound semiconductor layer such as an n-type GaN layer on the etched surface of the stacked structure by the MOVPE method or the MBE method.
After the formation of the electron conduction region 208, the source electrode 209 and the drain electrode 214 are formed by a lift-off process (steps (d) and (e)). More specifically, a part of the upper surface of the high concentration n-type semiconductor layer 202 is exposed by dry etching to form a region where the drain electrode 214 is to be formed. Next, a resist pattern is formed on the stacked structure using photolithography, and then a metal layer is formed on the resist pattern and the stacked structure by sputtering. Thereafter, by removing the resist pattern and the metal material on the resist pattern at the same time, the electrode patterns of the source electrode 209 and the drain electrode 214 that are in ohmic contact with the electron supply layer 207 and the high-concentration n-type semiconductor layer 202, respectively, are obtained. Can be formed.
Each of the source electrode 209 and the drain electrode 214 includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), or gold (Au). As long as it is made of a metal material, it may have a structure in which a plurality of metal layers are laminated.

  Thereafter, an insulating film is formed so as to cover the entire laminated structure, and the insulating film is patterned to form an insulating film 210 having an opening as shown in FIG. Further, by performing dry etching on the electron supply layer 207 using the insulating film 210 as a mask, a recess (recess structure) is formed in the electron supply layer 207. Then, a gate electrode 212 having a T-shaped cross section is formed in the recess of the electron supply layer 207 and the opening of the insulating film 210 (step (g)).

  In the present embodiment, as a preferred configuration, a configuration is adopted in which the length of the collar portion of the gate electrode 212 on the electron conduction region 208 side is longer than the collar portion of the gate electrode 212 on the source electrode 209 side. Is not to be done. The length of the collar part of the gate electrode 212 on the electron conduction region 208 side and the length of the collar part of the gate electrode 212 on the source electrode 209 side are equal, or the collar part of the gate electrode 212 on the electron conduction region 208 side is the gate electrode. There may be a form shorter than the buttocks of 212 on the source electrode 209 side. However, if the collar part of the gate electrode 212 on the source electrode 209 side is too long compared to the collar part of the gate electrode 212 on the electron conduction region 208 side, the gain reduction due to the increase in the gate capacitance becomes large.

  After the formation of the gate electrode 212, a protective film 213 that covers the gate electrode 212 is formed on the stacked structure by a CVD method (step (h)). The insulating film 210 and the protective film 213 are, for example, one type selected from the group consisting of silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti), and tantalum (Ta). Or what is necessary is just to comprise by 2 or more types of oxides or nitrides. Instead of an inorganic compound such as oxide or nitride, the protective film 213 may be formed of an organic insulator.

The effects produced by the field effect transistor 20 of the second embodiment are as follows.
The electron conduction region 208 is on the opposite side of the left and right sides of the gate electrode 212 from the source electrode 209 side, and extends from one end of the electron transit layer 206 to a region closer to the substrate 201 than the electron barrier layer 205. Yes. The drain electrode 214 is electrically connected to one end of the electron conduction region 208 on the substrate 201 side via the high concentration n-type semiconductor layer 202 and the drift layer 203.
Since current flows in the drift layer 203 perpendicularly to the semiconductor surface, the electric field distribution in the drift layer 203 is not easily affected by the fixed charge on the semiconductor surface, and a breakdown voltage close to the breakdown breakdown voltage of the drift layer 203 itself is ensured. Can do. Therefore, as the thickness of the drift layer 203 is increased, a higher breakdown voltage can be surely ensured. In the transistor having such a structure, electric field concentration is generated in the drift layer 203 and high breakdown voltage can be secured. Therefore, as described in the background art, it is possible to reduce the chip size as compared with the case where the source electrode and the drain electrode are arranged at a large distance on the same plane in order to secure a withstand voltage. .

  Similarly, in the drift layer 203, carriers flow from the electron conduction region 208 side toward the substrate 201, so that the electron movement path in the drift layer 203 is the electron supply layer 207, the insulating film 210, and the field effect transistor 20. It is difficult to be affected by the fixed charge generated at the interface. Therefore, the electric field distribution in the movement path of electrons as carriers is likely to be uniform, and the maximum electric field strength close to the bulk value of the dielectric breakdown voltage can be secured, so that a small chip size can be realized and the breakdown voltage performance can be improved.

In the present embodiment, the electric field relaxation layer 204 made of the In _x Al _y Ga _1-xy N layer has a composition in which one or both of the Al composition ratio y and the In composition ratio x gradually change as described above. Therefore, an energy band structure in which the conduction band and the valence band are bent toward the vacuum level is formed inside the electric field relaxation layer 204 by the piezoelectric effect and the spontaneous polarization effect. Since this convex energy band is formed with fixed charges due to the piezo effect and the spontaneous polarization effect, it is possible to suppress an increase in local electric field strength. Therefore, punch-through is suppressed, and a higher breakdown voltage can be achieved.
As shown in FIG. 5, the collar portion of the gate electrode 212 extending from the opening of the insulating film 210 toward the electron conduction region 208 extends from the opening of the gate electrode 212 toward the source electrode 209. Longer than the heel part. Thereby, the electric field concentration in the vicinity of the gate electrode 212 can be relaxed, and a high breakdown voltage can be achieved. In addition, since the electric field intensity distribution in the channel region is made uniform, current collapse can be suppressed.
Therefore, it is possible to provide a field effect transistor 20 having high-frequency characteristics using a channel of a two-dimensional electron gas, high breakdown voltage performance, and enabling a reduction in chip size.

(Modification of the second embodiment)
FIG. 6 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 20A that is a modification of the second embodiment. In the structure of the field effect transistor 20A, a potential control electrode 117 for controlling the potential of the electron conductive region 208 via the potential control insulating film 116 is disposed on the opposite side of the drift layer 203 of the electron conductive region 208. .
Such a field effect transistor 20A can provide the same effects as those of the second modification of the first embodiment.

(Third embodiment)
Next, a third embodiment according to the present invention will be described. FIG. 7 is a cross-sectional view schematically showing the structure of the field effect transistor 30 of the third embodiment.
This field effect transistor 30 has a stacked structure in which a buffer layer 215, a high-concentration n-type semiconductor layer 202, a drift layer 203, a field relaxation layer 204, an electron barrier layer 205, and an electron transit layer 206 are stacked in this order on a substrate 201. Have This laminated structure has the same composition as the laminated structure of the second embodiment (FIG. 5) and is formed by the same manufacturing method as the laminated structure of the second embodiment. An insulating film 310 is formed on the stacked structure in FIG. 7, and a gate insulating film 311 and a gate electrode 312 are formed in an opening formed in the insulating film 310.

On one side (one side in the gate length direction) of the left and right sides of the gate electrode 312 (both sides in the direction parallel to the substrate surface), an electron conduction region 308 is formed on the etched surface formed in the stacked structure. ing. The electron conduction region 308 is provided so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the p-type electron barrier layer 205. A source electrode 309 is formed on the electron transit layer 206 on the other of the left and right sides of the gate electrode 312.
A drain electrode 214 is formed on the high concentration n-type semiconductor layer 202 on the surface side of the substrate 201, and the drain electrode 214 conducts electrons through the high concentration n-type semiconductor layer 202 and the drift layer 203. The region 308 is electrically connected to one end on the substrate 201 side.

  As shown in FIG. 7, the gate electrode 312 protrudes in the direction of the electron transit layer 206 (substrate 201 side), and extends from the protrusion to the source electrode 309 side and the electron conduction region 308 side, respectively. And a buttock. The collar part extending to the electron conductive region 308 side of the gate electrode 312 is longer than the collar part extending to the source electrode 309 side of the gate electrode 312. Thereby, the electric field concentration near the gate electrode 312 can be reduced.

  The gate electrode 312 may be made of a metal material such as W, Mo, Si, Ti, Pt, Nb, Al, or Au, and may have a structure in which a plurality of metal layers are stacked. The gate electrode 312 may be formed using a semiconductor material that is in Schottky contact with the underlying electron transit layer 206 instead of a metal material. However, this semiconductor material is preferably a material that does not react with the insulating film 310 or the protective film 313.

The manufacturing method of the field effect transistor 30 includes the following basic steps (a) to (h).
(A) A buffer layer 215, a high-concentration n-type semiconductor layer 202, a drift layer 203, an electric field relaxation layer 204, an electron barrier are formed on the substrate 201 by metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE). A step of continuously epitaxially growing each layer constituting a stacked structure including a plurality of compound semiconductor layers constituting the layer 205 and the electron transit layer 206 in this order.
(B) The stacked structure is etched on one of the left and right sides of the region where the gate electrode 312 is to be formed so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the electron barrier layer 205. Forming an etched surface.
(C) A step of forming an electron conductive region 308 on the etched surface.
(D) A step of forming the source electrode 309 on the electron transit layer 206 on the other of the left and right sides of the region where the gate electrode 312 is to be formed.
(E) A step of forming a drain electrode 214 that is electrically connected to one end of the electron conduction region 308 on the substrate 201 side.
(F) A step of forming a patterned insulating film 310.
(G) A step of forming the gate insulating film 311 and the gate electrode 312 in the opening of the insulating film 310 on the electron transit layer 206.
(H) A step of forming a protective film 313 that covers the entire element except a part of the electrode surface.

The electron conduction region 308 is located on the opposite side of the source electrode 309 with the gate electrode 312 interposed therebetween as viewed from the substrate surface side.
In the present embodiment, the electron conduction region 308 extends from the electron transit layer 206 side to the drift layer 203 side, one end portion is in contact with the electron transit layer 206, and the other end portion is in contact with the drift layer 203. Yes. More specifically, the electron conduction region 308 is provided in contact with the electron transit layer 206, the electron barrier layer 205, and the drift layer 203. The electron conduction region 308 is formed up to the middle of the thickness of the drift layer 203.
The electron conduction region 308 may be formed by the same manufacturing method as the electron conduction region 208 (FIG. 5) of the second embodiment. After the formation of the electron conduction region 308, the source electrode 309 and the drain electrode 214 are formed by a lift-off process (steps (d) and (e)). More specifically, a part of the upper surface of the high concentration n-type semiconductor layer 202 is exposed by dry etching to form a region where the drain electrode 214 is to be formed. Next, a resist pattern is formed on the stacked structure using photolithography, and then a metal layer is formed on the resist pattern and the stacked structure by sputtering. Thereafter, by removing the resist pattern and the metal material on the resist pattern at the same time, the electrode patterns of the source electrode 309 and the drain electrode 214 that are in ohmic contact with the electron transit layer 206 and the high-concentration n-type semiconductor layer 202 are obtained. Can be formed.

  Each of the source electrode 309 and the drain electrode 214 includes tungsten (W), molybdenum (Mo), silicon (Si), titanium (Ti), platinum (Pt), niobium (Nb), aluminum (Al), or gold (Au). As long as it is made of a metal material, it may have a structure in which a plurality of metal layers are laminated.

  Thereafter, an insulating film is formed so as to cover the entire laminated structure, and the insulating film is patterned to form an insulating film 310 having an opening as shown in FIG. Then, a gate insulating film 311 and a gate electrode 312 having a T-shaped cross-sectional shape are formed in the opening of the insulating film 310 (step (g)).

  In the present embodiment, as a preferable configuration, a configuration is adopted in which the length of the flange portion of the gate electrode 312 on the electron conduction region 308 side is longer than that of the gate electrode 312 on the source electrode 309 side. Is not to be done. The length of the collar part of the gate electrode 312 on the electron conducting region 308 side and the length of the collar part of the gate electrode 312 on the source electrode 309 side are equal, or the collar part of the gate electrode 312 on the electron conducting region 308 side is the gate electrode. There may be a form shorter than the ridge portion of 312 on the source electrode 309 side. However, if the collar part of the gate electrode 312 on the source electrode 309 side is too long compared with the collar part of the gate electrode 312 on the electron conduction region 308 side, the gain reduction due to the increase in the gate capacitance increases.

  After the gate electrode 312 is formed, a protective film 313 that covers the gate electrode 312 is formed on the stacked structure by a CVD method (step (h)). The insulating film 310, the gate insulating film 311 and the protective film 313 are made of, for example, a group consisting of silicon (Si), magnesium (Mg), hafnium (Hf), aluminum (Al), titanium (Ti) and tantalum (Ta). What is necessary is just to comprise with the 1 type (s) or 2 or more types of selected oxide or nitride. Instead of an inorganic compound such as oxide or nitride, the protective film 313 may be formed of an organic insulator.

The effects produced by the field effect transistor 30 of the third embodiment are as follows.
Similar to the electron conduction region 208 of the second embodiment, the electron conduction region 308 of this embodiment is on the opposite side of the left and right sides of the gate electrode 312 from the source electrode 309 side, and is one end of the electron transit layer 206. To the region closer to the substrate 201 than the electron barrier layer 205. The drain electrode 214 is electrically connected to one end of the electron conduction region 308 on the substrate 201 side through the high concentration n-type semiconductor layer 202 and the drift layer 203. Therefore, in the drift layer 203, electrons as carriers flow from the electron conduction region 308 side toward the substrate 201. As described in the second embodiment, the breakdown voltage depends on the thickness of the drift layer 203. Therefore, the chip size can be reduced even if the drift layer 203 is thickened to increase the breakdown voltage. In addition, the electron movement path in the drift layer 203 is not easily affected by the fixed charge generated at the interface between the electron transit layer 206 of the field effect transistor 30 and the insulating film 310. Therefore, it is possible to realize a small chip size and improve the pressure resistance performance.

Similar to the second embodiment, also in this embodiment, the electric field relaxation layer 204 made of the In _x Al _y Ga _1-xy N layer has one or both of the Al composition ratio y and the In composition ratio x gradually increased. Therefore, punch-through is suppressed, and a higher breakdown voltage can be achieved.

As shown in FIG. 7, the collar portion of the gate electrode 312 extending from the opening of the insulating film 310 toward the electron conduction region 308 extends from the opening of the gate electrode 312 toward the source electrode 309. It is longer than the existing heel part. Thereby, the electric field concentration in the vicinity of the gate electrode 312 can be relaxed, and a high breakdown voltage can be achieved. In addition, since the electric field intensity distribution in the channel region is made uniform, current collapse can be suppressed.
Therefore, it is possible to provide a field effect transistor 30 that has good controllability of threshold voltage, has high withstand voltage performance, and can reduce the chip size. Since the field effect transistor 30 of this embodiment does not use the channel of the two-dimensional electron gas, it has low frequency characteristics.

(Modification of the third embodiment)
FIG. 8 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 30A, which is a modification of the third embodiment. In the structure of the field effect transistor 30A, a potential control electrode 117 is disposed on the opposite side of the electron conduction region 308 from the drift layer 203 via a potential control insulating film 116.
Such a field effect transistor 30A can achieve the same effects as those of the second modification of the first embodiment.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described. FIG. 9 is a cross-sectional view schematically showing the structure of the field effect transistor 40 of the fourth embodiment. The field effect transistor 40 has a stacked structure in which a buffer layer 215, a high-concentration n-type semiconductor layer 202, a drift layer 203, an electron barrier layer 205, and an electron transit layer 206 are stacked in this order on a substrate 201. An insulating film 210 is formed on the stacked structure, and a gate electrode 212 is formed in an opening formed in the insulating film 210.
On one side (one side in the gate length direction) of the left and right sides of the gate electrode 212 (both sides in the direction parallel to the substrate surface), an electron conduction region 408 is formed on the etched surface formed in the stacked structure. ing. The electron conduction region 408 is provided so as to extend from one end of the electron transit layer 206 to a region closer to the substrate 201 than the p-type electron barrier layer 205. A source electrode 209 is formed on the electron supply layer 207 on the other of the left and right sides of the gate electrode 212.

On the surface side of the substrate 201, a drain electrode 214 is formed on the high-concentration n-type semiconductor layer 202, and the drain electrode 214 is connected to the electron conduction region 408 via the high-concentration n-type semiconductor layer 202 and the drift layer 203. Is electrically connected to one end on the substrate 201 side.
The structure of the field effect transistor 40 of the fourth embodiment has the same composition as that of the structure of the second embodiment except that the field relaxation layer 204 (FIG. 5) of the second embodiment is not included. The field effect transistor 40 of the fourth embodiment is formed by the same manufacturing method as that of the second embodiment, except that the field relaxation layer 204 of the second embodiment is not formed. The electron conduction region 408 of this embodiment can be formed by the same manufacturing method as the electron conduction region 208 of the second embodiment.

  Since the field effect transistor 40 of the fourth embodiment does not include the field relaxation layer 204, the withstand voltage performance of the field effect transistor 40 of the present embodiment is slightly lower than that of the field effect transistor 20 of the second embodiment. However, a process for forming a composition in which one or both of the Al composition ratio y and the In composition ratio x of the electric field relaxation layer 204 is changed gradually or stepwise is not required, so that the fabrication becomes easy.

(Modification of the fourth embodiment)
FIG. 10 is a cross-sectional view schematically showing a cross-sectional structure of a field effect transistor 40A, which is a modification of the fourth embodiment. In the structure of the field effect transistor 40A, a potential control electrode 117 is disposed on the opposite side of the electron conduction region 408 from the drift layer 203 via a potential control insulating film 116.
In such a field effect transistor 40A, the same effects as those of the second modification of the first embodiment can be obtained.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in each of the above-described embodiments, the electron conductive regions 108, 208, and 308 are provided on the end side of the electron transit layers 106 and 206, but the present invention is not limited to this. For example, as shown in FIG. 11, the electron conduction region 108 may be disposed in the center of the drift layer 103, the electric field relaxation layer 104, the electron barrier layer 105, and the electron transit layer 106.
This transistor includes a plurality of source electrodes 109A and 109, and gate electrodes 112A and 112B. Specifically, when viewed from the substrate surface side, a gate electrode 112A is disposed adjacent to the source electrode 109A, an electron conduction region 108 is disposed next to the gate electrode 112A, and further, next to the electron conduction region 108. The gate electrode 112A is disposed, and the source electrode 109B is disposed next to the gate electrode 112B. The electron conductive region 108 is disposed so as to be sandwiched between the pair of source electrodes 109A and 109B.
The drain electrode 114 is disposed on the back side of the substrate 101, but may be disposed on the high concentration n-type semiconductor layer 102. Note that the drain electrode 114 may be arranged on the high concentration n-type semiconductor layer 102 before the drawing or on the back side.
Note that when the transistor as shown in FIG. 11 is formed, the source electrode 109, the gate electrode 112, and the electron conduction region 108 can be arranged as shown in FIGS.
FIG. 13 shows the arrangement of the source electrode 109, the gate electrode 112, and the electron conduction region 108 in a state where the drain electrode 114 is arranged on the back surface of the substrate 101 as shown in FIG. The gate electrode 112 is formed in a comb shape when viewed from the substrate surface side, and has a structure in which the electron conduction region 108 is disposed between the gate electrodes 112A and 112B.
The source electrode 109 is also formed in a comb shape when viewed from the substrate surface side, and the gate electrodes 112A and 112B and the electron conduction region 108 are disposed between the source electrodes 109A and 109B.
14 and 15 show a state in which the drain electrode 114 is formed on the high concentration n-type semiconductor layer 102. The arrangement of the gate electrode 112, the source electrode 109, and the electron conduction region 108 is the same as that in FIG.

Next, examples of the above embodiment will be described.
(First embodiment)
The field effect transistor of the first example has the same structure as the field effect transistor 10 of the first embodiment. As the substrate 101, an n-type GaN substrate having a (0001) plane (= c plane) as a main surface was used. An n-type GaN layer (impurity concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 200 nm) added with Si as the high-concentration n-type semiconductor layer 102 and an n-type GaN layer (impurity concentration) added with Si as the drift layer 103 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm), an AlyGa1-yN layer (film thickness: 300 nm) as the electric field relaxation layer 104, and a p-type GaN layer (1 × 10 6) with Mg added as the electron barrier layer 105. ¹⁹ cm ⁻³ , film thickness: 300 nm), a non-doped GaN layer (film thickness: 80 nm) as the electron transit layer 106, and an Al _x Ga _1-x N layer (Al composition ratio: x = 0.0) as the electron supply layer 107. 2, a film thickness: 40 nm) as a source electrode 109 and a drain electrode 114, a Ti / Al laminated structure (film thickness of Ti layer: 10 nm, film thickness of Al layer: 200 nm), insulating film 110 is a SiON film (film thickness: 80 nm), the gate electrode 112 is a Ni / Au stacked structure (Ni layer film thickness: 15 nm, Au layer film thickness: 400 nm), and the protective film 113 is a SiON film (film thickness: 80 nm), and an Al ₂ O ₃ film (film thickness: 10 nm) was used as the gate insulating film 111, respectively.
The electric field relaxation layer 104 has an Al composition ratio y = 0.3 on the surface on the substrate 101 side, an Al composition ratio y = 0 on the surface on the source electrode 109 side, and the Al composition ratio y is the electric field relaxation layer. It was formed so as to gradually decrease from the surface on the substrate 101 side of 104 toward the surface on the source electrode 109 side of the electric field relaxation layer 104. The depth of the recess (recess structure) formed in the electron supply layer 107 was 25 nm.
The electron conduction region 108 is formed by removing a part of the laminated structure by dry etching to form an etched surface that extends from the electron supply layer 107 to the drift layer 103, and a Si-doped GaN layer ( Impurity concentration: 8 × 10 ¹⁷ cm ⁻³ ) was grown again.
The field effect transistor 10 of the first embodiment manufactured in this way has high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and high breakdown voltage characteristics. confirmed.

(Second embodiment)
The field effect transistor of the second example has the same structure as the field effect transistor 10A (FIG. 3), which is a modification of the first embodiment. As the substrate 101, an n-type GaN substrate having a (0001) plane (= c plane) as a main surface was used. An n-type GaN layer (impurity concentration: 1 × 10 ¹⁹ cm ⁻³ , film thickness: 200 nm) added with Si as the high-concentration n-type semiconductor layer 102 and an n-type GaN layer (impurity concentration) added with Si as the drift layer 103 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm), and Si-doped n-type AlyGa1-yN layer (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 300 nm) as the electric field relaxation layer 104 A p-type GaN layer (1 × 10 ¹⁹ cm ⁻³ , film thickness: 300 nm) doped with Mg as the electron barrier layer 105, a non-doped GaN layer (film thickness: 80 nm) as the electron transit layer 106, and the electron supply layer 107 An Al _x Ga _1-x N layer (Al composition ratio: x = 0.2, film thickness: 40 nm) is used as a source electrode 109 and a drain electrode 114 as a Ti / Al stacked structure (Ti layer). Film thickness: 10 nm, Al layer film thickness: 200 nm), SiON film (film thickness: 80 nm) as the insulating film 110, and Ni / Au laminated structure (Ni layer film thickness: 15 nm, Au layer as the gate electrode 112) The protective film 113 is an SiON film (film thickness: 80 nm), and the gate insulating film 111 is an Al ₂ O ₃ film (film thickness: 10 nm).
The electric field relaxation layer 104 has an Al composition ratio y = 0.3 on the surface on the substrate 101 side, an Al composition ratio y = 0 on the surface on the source electrode 109 side, and the Al composition ratio y is the electric field relaxation layer. It was formed so as to gradually decrease from the surface on the substrate 101 side of 104 toward the surface on the source electrode 109 side of the electric field relaxation layer 104. The depth of the recess (recess structure) formed in the electron supply layer 107 was 25 nm.
The electron conduction region 108 is formed by removing a part of the laminated structure by dry etching to form an etched surface that extends from the electron supply layer 107 to the drift layer 103, and a Si-doped GaN layer ( Impurity concentration: 8 × 10 ¹⁷ cm ⁻³ ) was grown again.
The field effect transistor 10A according to the second embodiment manufactured as described above has a high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and a comparison with the first embodiment. Further, it was confirmed to have a high breakdown voltage characteristic.

(Third embodiment)
The field effect transistor of the third example has the same structure as the field effect transistor 10B (FIG. 4) of the first embodiment. As the substrate 101, an n-type GaN substrate having a (0001) plane (= c plane) as a main surface was used. An n-type GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 500 nm) added with Si as the high-concentration n-type semiconductor layer 102, and an n-type GaN layer (impurity concentration) added with Si as the drift layer 103 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm), an AlyGa1-yN layer (film thickness: 300 nm) as the electric field relaxation layer 104, and a p-type GaN layer (1 × 10 6) with Mg added as the electron barrier layer 105. ¹⁹ cm ⁻³ , film thickness: 300 nm), non-doped GaN layer (film thickness: 80 nm) as the electron transit layer 106, and Al x Ga 1-x N layer (Al composition ratio: x = 0.2, film thickness) as the electron supply layer 107. : 40 nm) as a source electrode 109 and a drain electrode 114 with a Ti / Al stacked structure (Ti layer thickness: 10 nm, Al layer thickness: 200 nm), insulating film 1 SiON film (film thickness: 80 nm) as 0, Ni / Au laminated structure (film thickness of Ni layer: 15 nm, film thickness of Au layer: 400 nm) as the gate electrode 112, and SiON film (film thickness: as the protective film 113) 80 nm), and an Al ₂ O ₃ film (film thickness: 30 nm) was used as the gate insulating film 111, respectively.
The electric field relaxation layer 104 has an Al composition ratio y = 0.3 on the surface on the substrate 101 side, an Al composition ratio y = 0 on the surface on the source electrode 109 side, and the Al composition ratio y is the electric field relaxation layer. It was formed so as to gradually decrease from the surface on the substrate 101 side of 104 toward the surface on the source electrode 109 side of the electric field relaxation layer 104. The depth of the recess (recess structure) formed in the electron supply layer 107 was 20 nm.
The electron conduction region 108 is formed by removing a part of the laminated structure by dry etching to form an etched surface that extends from the electron supply layer 107 to the drift layer 103, and a Si-doped GaN layer ( Impurity concentration: 8 × 10 ¹⁷ cm ⁻³ ) was grown again.
An Al ₂ O ₃ film (film thickness: 200 nm) is used as the potential control insulating film 116, and a Ti / Pt / Au laminated structure (film thickness of Ti layer: 15 nm, film thickness of Pt layer: 100 nm, Au layer) as the potential control electrode 117 The film thickness was 200 nm).
The field effect transistor 10B of the third embodiment manufactured in this way has a high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and a comparison with the first embodiment. Further, it was confirmed to have a high breakdown voltage characteristic.

(Fourth embodiment)
The field effect transistor of the fourth example has the same structure as the field effect transistor 20 of the second embodiment. As the substrate 201, a silicon carbide (SiC) substrate having a (0001) plane (= c plane) as a main surface was used. Drift of an AlN layer (film thickness: 100 nm) as the buffer layer 215 and an n-type GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 500 nm) doped with Si as the high-concentration n-type semiconductor layer 202 An n-type GaN layer doped with Si (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm) is used as the layer 203, and an In _x Ga _1-x N layer (film thickness: 200 nm) is used as the electric field relaxation layer 204. An In _x Ga _1-x N layer (In composition ratio: x = 0.1, impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 200 nm) to which Mg is added as the electron barrier layer 205 is used as the electron transit layer. 206, an InxGa1-xN layer (In composition ratio: x = 0.1, film thickness: 100 nm), and an electron supply layer 207, an AlxGa1-xN layer (Al composition ratio: x = 0.1, film thickness: 25 nm). Ti / Al / Nb / Au laminated structure as source electrode 209 and drain electrode 214 (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness: 35 nm, Au layer thickness: 50 nm) The insulating film 210 is a SiON film (film thickness: 80 nm), the gate electrode 212 is a Ni / Au laminated structure (Ni layer film thickness: 15 nm, the Au layer film thickness: 400 nm), and the protective film 213 is a SiON film. (Film thickness: 80 nm) was used.
The electric field relaxation layer 204 has an In composition ratio x = 0 on the surface on the substrate 201 side, an In composition ratio x = 0.1 on the surface on the source electrode 209 side, and the In composition ratio x is the electric field relaxation layer. The electric field relaxation layer 204 is formed so as to gradually increase from the surface on the substrate 201 side toward the surface on the source electrode 209 side of the electric field relaxation layer 204. The depth of the recess (recess structure) formed in the electron supply layer 207 was 15 nm.
In the electron conduction region 208, a part of the laminated structure is removed by dry etching to form an etched surface, and a Si-doped GaN layer (impurity concentration: 5 × 10 ¹⁷ cm ⁻³ ) is formed on the etched surface. Formed by regrowth.
The field effect transistor 20 of the fourth embodiment manufactured in this way has high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and high breakdown voltage characteristics. confirmed.

(5th Example)
The field effect transistor of the fifth example has the same structure as the field effect transistor 20A (FIG. 6) of the modification of the second embodiment. As the substrate 201, a silicon carbide (SiC) substrate having a (0001) plane (= c plane) as a main surface was used. Drift of an AlN layer (film thickness: 100 nm) as the buffer layer 215 and an n-type GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 500 nm) doped with Si as the high-concentration n-type semiconductor layer 202 An n-type GaN layer doped with Si (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm) is used as the layer 203, and an In _x Ga _1-x N layer (film thickness: 200 nm) is used as the electric field relaxation layer 204. An In _x Ga _1-x N layer (In composition ratio: x = 0.1, impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 200 nm) to which Mg is added as the electron barrier layer 205 is used as the electron transit layer. 206, an InxGa1-xN layer (In composition ratio: x = 0.1, film thickness: 100 nm), and an electron supply layer 207, an AlxGa1-xN layer (Al composition ratio: x = 0.1, film thickness: 25 nm). Ti / Al / Nb / Au laminated structure as source electrode 209 and drain electrode 214 (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness: 35 nm, Au layer thickness: 50 nm) The insulating film 210 is a SiON film (film thickness: 80 nm), the gate electrode 212 is a Ni / Au laminated structure (Ni layer film thickness: 15 nm, the Au layer film thickness: 400 nm), and the protective film 213 is a SiON film. (Film thickness: 80 nm) was used.
The electric field relaxation layer 204 has an In composition ratio x = 0 on the surface on the substrate 201 side, an In composition ratio x = 0.1 on the surface on the source electrode 209 side, and the In composition ratio x is the electric field relaxation layer. The electric field relaxation layer 204 is formed so as to gradually increase from the surface on the substrate 201 side toward the surface on the source electrode 209 side of the electric field relaxation layer 204. The depth of the recess (recess structure) formed in the electron supply layer 207 was 15 nm.
In the electron conduction region 208, a part of the laminated structure is removed by dry etching to form an etched surface, and a Si-added GaN layer (impurity concentration: 5 × 10 17 cm −3) is again formed on the etched surface. It was formed by growing.
An Al ₂ O ₃ film (film thickness: 100 nm) is used as the potential control insulating film 116, and a Ti / Pt / Au stacked structure is used as the potential control electrode 117 (Ti film thickness: 15 nm, Pt film thickness: 100 nm, Au layer) The film thickness was 200 nm).
The field effect transistor 20A of the fifth embodiment manufactured in this way has a high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and a comparison with the fourth embodiment. Further, it was confirmed to have a high breakdown voltage characteristic.

(Sixth embodiment)
The field effect transistor of the sixth example has the same structure as the field effect transistor 30 of the third embodiment. As the substrate 201, a silicon (Si) substrate having a (111) plane as a main surface was used. As the buffer layer 215, a two-layer structure of an Al x Ga 1-x N layer and an Aly Ga 1-y N layer (Al composition ratio: x = 0.2, y = 0.1, each film thickness is 100 nm), a high concentration n-type semiconductor layer 202 is used. N-type GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 1000 nm) added as Si, and GaN layer (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ ) added Si as the drift layer 203, A film thickness: 3000 nm), an Al-Ga1-yN layer (film thickness: 100 nm) as the electric field relaxation layer 204, and a p-type GaN layer to which Mg is added as the electron barrier layer 205 (impurity concentration: 2 × 10 ¹⁹ cm ⁻³⁾ thickness: the 200 nm), n-type GaN layer doped with Si as the electron transit layer 206 (dopant concentration: 1 × ¹⁰ 17 ^{cm -3,} film thickness: 200 nm), and a source electrode 309 and The rain electrode 214 has a Ti / Al / Nb / Au stacked structure (Ti layer thickness 15 nm, Al layer thickness: 60 nm, Nb layer thickness: 35 nm, Au layer thickness: 50 nm), and insulating film 310. SiN film (film thickness: 120 nm) as the gate insulating film 311, Al2O3 film (film thickness: 10 nm) as the gate electrode 312 Ni / Pt / Au laminated structure (Ni film thickness: 5 nm, Pt layer film : 35 nm, thickness of Au layer: 400 nm), and SiO 2 film (film thickness: 60 nm) as the protective film 313, respectively.
The electric field relaxation layer 204 has an Al composition ratio y = 0.2 on the surface on the substrate 201 side, an Al composition ratio y = 0 on the surface on the source electrode 309 side, and the Al composition ratio y is the electric field relaxation layer. The electric field relaxation layer 204 is formed so as to gradually decrease from the surface on the substrate 201 side toward the surface on the source electrode 309 side of the electric field relaxation layer 204.
The electron conductive region 308 is formed by removing a part of the laminated structure by dry etching to form an etched surface, and a Si-added GaN layer (impurity concentration: 1 × 10 ¹⁸ cm ⁻³ ) on the etched surface. Formed by regrowth.
It was confirmed that the field effect transistor 30 of the sixth example manufactured in this way had a small chip size and high breakdown voltage characteristics and good controllability of the threshold voltage.

(Seventh embodiment)
The field effect transistor of the seventh example has the same structure as the field effect transistor 30A (FIG. 8) of the third embodiment. As the substrate 201, a silicon (Si) substrate having a (111) plane as a main surface was used. The buffer layer 215 has a two-layer structure of an Al _x Ga _1-x N layer and an Al _y Ga _1-y N layer (Al composition ratio: x = 0.2, y = 0.1, each film thickness is 100 nm). An n-type GaN layer doped with Si (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 1000 nm) as the high-concentration n-type semiconductor layer 202, and a GaN layer doped with Si as the drift layer 203 (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 3000 nm), an Al _y Ga _1-y N layer (film thickness: 100 nm) as the electric field relaxation layer 204, and a p-type GaN layer to which Mg is added as the electron barrier layer 205 ( Impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , film thickness: 200 nm) and Si-doped n-type GaN layer (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 200 nm) as the electron transit layer 206, Source electrode 30 Further, a Ti / Al / Nb / Au laminated structure (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness: 35 nm, Au layer thickness: 50 nm) is insulated as the drain electrode 214. The film 310 is a SiN film (film thickness: 120 nm), the gate insulating film 311 is an Al 2 O 3 film (film thickness: 10 nm), and the gate electrode 312 is a Ni / Pt / Au stacked structure (Ni film thickness: 5 nm, Pt layer) Film of 35 nm and film thickness of Au layer: 400 nm) and SiO 2 film (film thickness: 60 nm) as the protective film 313, respectively.
The electric field relaxation layer 204 has an Al composition ratio y = 0.2 on the surface on the substrate 201 side, an Al composition ratio y = 0 on the surface on the source electrode 309 side, and the Al composition ratio y is the electric field relaxation layer. The electric field relaxation layer 204 is formed so as to gradually decrease from the surface on the substrate 201 side toward the surface on the source electrode 309 side of the electric field relaxation layer 204.
The electron conductive region 308 is formed by removing a part of the laminated structure by dry etching to form an etched surface, and a Si-added GaN layer (impurity concentration: 1 × 10 ¹⁸ cm ⁻³ ) on the etched surface. Formed by regrowth.
ZrO ₂ film (film thickness: 300 nm) is used as the potential control insulating film 116, and a Ti / Pt / Au laminated structure (Ti film thickness: 10 nm, Pt layer film thickness: 80 nm, Au layer film) as the potential control electrode 117 Thickness: 300 nm) was used.
The field effect transistor 30A of the seventh embodiment manufactured in this way has a small chip size and higher withstand voltage characteristics compared to the sixth embodiment, and has good controllability of the threshold voltage. It was confirmed.

(Eighth embodiment)
The field effect transistor of the eighth example has the same structure as the field effect transistor 40 of the fourth embodiment. As the substrate 201, a silicon (Si) substrate having a (111) plane as a main surface was used. As the buffer layer 215, an AlN layer (thickness: 200 nm) is used, and as the high-concentration n-type semiconductor layer 202, a Si-doped GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , thickness: 1000 nm) is used as the drift layer 203. An n-type GaN layer to which Si is added (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 4000 nm) is used as an electron barrier layer 205 and a p-type GaN layer to which Mg is added (impurity concentration: 2 × 10 ¹⁹ cm ^{−). 3} , film thickness: 300 nm), GaN layer (film thickness: 100 nm) as the electron transit layer 206, and Al _x Ga _1-x N layer (Al composition ratio: x = 0.25, film thickness) as the electron supply layer 207. : 20 nm) as a source electrode 209 and a drain electrode 214, a Ti / Al / Nb / Au stacked structure (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness) Thickness: 35 nm, Au layer thickness: 50 nm), SiN film (film thickness: 120 nm) as the insulating film 210, and Ni / Au laminated structure (Ni layer film thickness: 15 nm, Au layer film) as the gate electrode 212 And a SiN film (film thickness: 80 nm) was used as the protective film 213, respectively.
The depth of the recess (recess structure) formed in the electron supply layer 207 was 10 nm.
In the electron conduction region 408, a part of the laminated structure is removed by dry etching to form an etched surface, and a Si-doped GaN layer (impurity concentration: 5 × 10 ¹⁷ cm ⁻³ ) is formed on the etched surface. Formed by regrowth.
The field effect transistor 40 of the eighth embodiment manufactured in this way has high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and high breakdown voltage characteristics. confirmed.

(Ninth embodiment)
The field effect transistor of the ninth example has the same structure as the field effect transistor 40A (FIG. 10) of the modification of the fourth embodiment. As the substrate 201, a silicon (Si) substrate having a (111) plane as a main surface was used. As the buffer layer 215, an AlN layer (thickness: 200 nm) is used, and as the high-concentration n-type semiconductor layer 202, a Si-doped GaN layer (impurity concentration: 2 × 10 ¹⁹ cm ⁻³ , thickness: 1000 nm) is used as the drift layer 203. An n-type GaN layer to which Si is added (impurity concentration: 1 × 10 ¹⁷ cm ⁻³ , film thickness: 4000 nm) is used as an electron barrier layer 205 and a p-type GaN layer to which Mg is added (impurity concentration: 2 × 10 ¹⁹ cm ^{−). 3} , film thickness: 300 nm), GaN layer (film thickness: 100 nm) as the electron transit layer 206, and AlxGa1-xN layer (Al composition ratio: x = 0.25, film thickness: 20 nm) as the electron supply layer 207. Ti / Al / Nb / Au laminated structure as source electrode 209 and drain electrode 214 (Ti layer thickness: 15 nm, Al layer thickness: 60 nm, Nb layer thickness) 35 nm, Au layer thickness: 50 nm), SiN film (film thickness: 120 nm) as the insulating film 210, and Ni / Au laminated structure (Ni layer film thickness: 15 nm, Au layer film thickness: as the gate electrode 212) 400 nm) and a SiN film (film thickness: 80 nm) were used as the protective film 213, respectively.
The depth of the recess (recess structure) formed in the electron supply layer 207 was 10 nm.
In the electron conduction region 408, a part of the laminated structure is removed by dry etching to form an etched surface, and a Si-added GaN layer (impurity concentration: 5 × 10 17 cm −3) is again formed on the etched surface. It was formed by growing.
An HfO 2 film (film thickness: 300 nm) is used as the potential control insulating film 116, and a Ti / Pt / Au stacked structure is used as the potential control electrode 117 (film thickness of the Ti layer: 10 nm, film thickness of the Pt layer: 80 nm, film thickness of the Au layer) : 300 nm) was used.
The field effect transistor 40A of the ninth embodiment manufactured in this way has a high electron mobility (= about 2 × 10 ³ cm ² / V / sec), a small chip size, and a comparison with the eighth embodiment. Further, it was confirmed to have a high breakdown voltage characteristic.

The embodiments and various examples of the present invention have been described above with reference to the drawings. However, these are examples of the present invention, and various configurations other than the above can be adopted. For example, in the first, second, and fourth embodiments, when Schottky electrodes are used as the gate electrodes 112 and 212, Be, C, and B are added to the electron supply layers 107 and 207 in order to suppress gate leakage current. A p-type impurity such as Mg may be introduced.
In the first embodiment, each of the compound semiconductor layers 102 to 107 formed on the substrate 101 can have a desired thickness, but the lattice constant of the compound semiconductor layers 102 to 107 is the substrate 101. If the lattice constant is significantly different from the above, it is desirable to make it not more than the critical film thickness at which dislocation occurs. The same applies to the compound semiconductor layers 203 to 207 formed on the substrate 201 of the second, third, and fourth embodiments.
In the first embodiment, when the recess (recess structure) is formed in the electron supply layer 107, the depth of the recess can be set to an arbitrary thickness. For example, the recess may be formed by etching the electron supply layer 107 to a thickness greater than that of the electron supply layer 107. However, if the depth of the recess is set to a certain level or more, the effect of improving the breakdown voltage and the effect of reducing the current collapse can be obtained by the recess structure.
On the other hand, if the depth of the recess is set to a certain value or less, an increase in carriers and an improvement in mobility can be obtained in the channel region of the two-dimensional electron gas immediately below the gate electrode 112. From this viewpoint, the depth of the recess formed in the electron supply layer 107 is preferably 30% to 90% of the thickness of the electron supply layer 107. The same applies to the depth of the recess (recess structure) formed in the electron supply layer 207 of the second and fourth embodiments.
In the first embodiment, a III-V compound semiconductor substrate having a wurtzite crystal structure is used as the substrate 101, and the growth surface of the substrate 101 is set to a group III surface (= (0001) surface). Yes, but not limited to this. The growth surface of the substrate 101 may be a group V surface (= (000-1) surface). In this case, since the direction of the piezo electric field is reversed, the element structure is designed accordingly.
Further, in each of the embodiments, the drift layers 103 and 203 have the same width as the other layers (for example, the high-concentration n-type semiconductor layers 102 and 202 and the electric field relaxation layers 104 and 204). In addition, it may exist only directly under the electron conduction region.

Claims (19)

A substrate,
A drift layer which is an n-type group III nitride compound semiconductor layer formed on the substrate;
An electron barrier layer that is a p-type nitride semiconductor layer formed above the drift layer;
An electron transit layer that is a group III nitride compound semiconductor layer formed on the electron barrier layer;
A gate electrode formed on the electron transit layer;
An n-type electron conduction region on one side of the gate electrode in the gate length direction and extending from the electron transit layer to a region closer to the substrate than the electron barrier layer;
A source electrode on the other side in the gate length direction of the gate electrode and formed on the electron transit layer;
A drain electrode electrically connected to one end of the electron conducting region on the substrate side through the drift layer;
Equipped with a,
A field effect transistor , wherein a potential control electrode is provided on an opposite side of the electron conduction region to the drift layer via an insulating film . A substrate,
A drift layer which is an n-type group III nitride compound semiconductor layer formed on the substrate;
An electron barrier layer that is a p-type nitride semiconductor layer formed above the drift layer;
An electron transit layer that is a group III nitride compound semiconductor layer formed on the electron barrier layer;
A gate electrode formed on the electron transit layer;
An electron conduction region of a metal film on one side of the gate length direction of the gate electrode and extending from the electron transit layer to a region closer to the substrate than the electron barrier layer;
A source electrode on the other side in the gate length direction of the gate electrode and formed on the electron transit layer;
A drain electrode electrically connected to one end of the electron conducting region on the substrate side through the drift layer;
Equipped with a,
A field effect transistor , wherein a potential control electrode is provided on an opposite side of the electron conduction region to the drift layer via an insulating film . The field effect transistor according to claim 1 or 2 ,
The field effect transistor, wherein the potential control electrode is connected to the gate electrode. The field effect transistor according to claim 1 or 2 ,
A field effect transistor, wherein the potential control electrode is grounded. The field effect transistor according to any one of claims 1 to 4 ,
A field effect transistor having a dielectric constant of 6 or more. The field effect transistor according to any one of claims 1 to 5 ,
The field effect transistor characterized in that the insulating film contains at least one of aluminum, silicon, hafnium, zirconium, tantalum, and titanium and at least one of oxygen and nitrogen. The field effect transistor according to any one of claims 1 to 6 ,
A field effect transistor, wherein the thickness of the insulating film is 10 nm or more. A field effect transistor according to any one of claims 1-7,
A field effect transistor having a thickness of the insulating film of 400 nm or less. The field effect transistor according to any one of claims 1 to 8 ,
A plurality and a second source electrode, and a second gate electrode,
Viewed from the substrate side, the source electrode, the gate electrode, the electron conductive region, said second gate electrode, said second field effect transistors are arranged in the order of the source electrode. The field effect transistor according to any one of claims 1 to 9 ,
The electron barrier layer is a field effect transistor, which is a p-type nitride semiconductor layer having an acceptor concentration of 1 × 10 ¹³ cm ⁻² or more in surface density. A field effect transistor according to any one of claims 1 to 10, interposed between the electron barrier layer and the drift layer, and _{In x Al y Ga 1-x} -y N (0 ≦ an electric field relaxation layer made of x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1),
The field effect transistor, wherein the Al composition ratio of the electric field relaxation layer decreases from the substrate side toward the source electrode side. The field effect transistor according to any one of claims 1 to 10 ,
The electron barrier layer is formed on the drift layer;
An electric field relaxation layer interposed between the drift layer and the electron barrier layer and made of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) In addition,
The field effect transistor, wherein an In composition ratio of the electric field relaxation layer increases from the substrate side toward the source electrode side. The field effect transistor according to any one of claims 1 to 10 ,
The electron barrier layer is formed on the drift layer;
An electric field relaxation layer interposed between the drift layer and the electron barrier layer and made of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1) In addition,
The In composition ratio of the electric field relaxation layer increases from the substrate side toward the source electrode side, and the Al composition ratio of the electric field relaxation layer decreases from the substrate side toward the source electrode side. Field effect transistor. The field effect transistor according to any one of claims 1 to 13 ,
An electron supply layer that is a group III nitride compound semiconductor layer interposed between the source electrode and the electron transit layer and heterojunction to the upper surface of the electron transit layer;
A field effect transistor in which a two-dimensional electron gas is formed at and near the interface between the electron transit layer and the electron supply layer in response to application of a bias voltage to the gate electrode. 15. A field effect transistor according to claim 14 , wherein
The field effect transistor, wherein the electron supply layer has a smaller electron affinity than the electron transit layer. The field effect transistor according to any one of claims 1 to 13 ,
A field effect transistor, further comprising a gate insulating film interposed between the gate electrode and the electron transit layer. The field effect transistor according to any one of claims 1 to 16 ,
The drain electrode is a field effect transistor formed on a surface side of the substrate. The field effect transistor according to any one of claims 1 to 16 ,
The drain electrode is a field effect transistor formed on the back surface of the substrate and electrically connected to the electron conduction region via the substrate and the drift layer. The field effect transistor according to any one of claims 1 to 18 ,
The gate electrode is
A protrusion protruding in the direction of the electron transit layer;
A flange extending from the protrusion to the source electrode side and the electron conduction region side,
Have
A field effect transistor, wherein a flange extending toward the electron conductive region side of the gate electrode is longer than a flange extending toward the source electrode of the gate electrode.

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