JP5761976B2 - Semiconductor device, test apparatus, and manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device, a test apparatus, and a manufacturing method.

Conventionally, in a FET (field effect transistor) using a group III-V semiconductor such as GaN (gallium nitride), Ta (tantalum) oxide or the like is interposed between a gate electrode and a semiconductor layer to reduce gate leakage current. A reduced heterojunction semiconductor device (in particular, a high electron mobility transistor: HEMT = High Electron Mobility Transistor) is known (for example, see Patent Document 1).
Patent Document 1 JP 2006-245317 A

  However, a phenomenon called “current collapse” in which the current decreases due to the trap of the semiconductor surface becomes a problem, and the gate voltage is set to a DC voltage by using an insulating layer between the gate electrode and the semiconductor layer as Ta (tantalum) oxide or the like. In some cases, even if the DC characteristics of the current voltage are improved, the pulse characteristics are not improved. For example, a pulse width of about several μs such as a pulse characteristic from a state in which Vds (drain-source voltage) is given in tens of volts in advance and a negative voltage is also given in advance to Vgs (gate-source voltage). It was difficult to operate following the input gate signal.

  In order to solve the above problems, in the first aspect of the present invention, a semiconductor layer, a gate insulating film provided on the semiconductor layer, a gate electrode provided on the gate insulating film, and the gate insulating film are provided. A gate boundary film in contact with the gate electrode at least at a part of the end portion of the gate electrode on the gate insulating film, wherein the gate boundary film and the gate insulating film include the same type of insulating material. To do.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 shows a configuration example of a longitudinal section of a semiconductor device 100 according to the present embodiment. 2 shows a manufacturing flow of the semiconductor device 100 according to the present embodiment. A configuration example at the stage where the semiconductor layer 110 of the semiconductor device 100 according to the present embodiment is formed is shown. A configuration example at the stage where the source electrode 160 and the drain electrode 170 are formed on the semiconductor layer 110 according to the present embodiment is shown. A configuration example at the stage where the gate insulating film 120 is formed on the semiconductor layer 110 according to the present embodiment is shown. A configuration example at the stage where the gate electrode 130 is formed on the gate insulating film 120 according to the present embodiment is shown. A configuration example at the stage where the gate boundary film 140 is formed on the gate insulating film 120 and the gate electrode 130 according to the present embodiment is shown. A configuration example at the stage where the protective film 150 is formed on the gate boundary film 140 according to the present embodiment is shown. An example of pulse characteristics of a semiconductor device in which the gate boundary film 140 is not formed is shown. An example of pulse characteristics of the semiconductor device 100 according to the present embodiment is shown. A configuration example of a test apparatus 410 according to this embodiment is shown together with a device under test 400.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration example of a longitudinal section of a semiconductor device 100 according to the present embodiment. The semiconductor device 100 reduces gate leakage current and improves high frequency characteristics when a pulse is applied to the gate electrode. The semiconductor device 100 may be a FET. The semiconductor device 100 may be a HEMT. The semiconductor device 100 includes a substrate 10, a semiconductor layer 110, a gate insulating film 120, a gate electrode 130, a gate boundary film 140, a protective film 150, a source electrode 160, and a drain electrode 170.

  The substrate 10 forms a semiconductor layer 110 on the surface. The substrate 10 may be a crystal having a lattice constant substantially the same as the lattice constant of the semiconductor layer 110 so as to be formed while maintaining the crystallinity of the semiconductor layer 110. The substrate 10 may be a single crystal such as sapphire, SiC (silicon carbide), GaN, GaAs, or Si.

  The semiconductor layer 110 is formed of a III-V group compound semiconductor. The semiconductor layer 110 may have a heterojunction in which two or more kinds of semiconductors having different band gaps are joined with crystallinity. In this embodiment, the semiconductor layer 110 is a GaN-based semiconductor layer. The semiconductor layer 110 includes an electron transit layer 112, a spacer layer 114, an electron supply layer 116, and a protective layer 118.

  The electron transit layer 112 is formed on the surface of the substrate 10. In the electron transit layer 112, a layer called binary electron gas capable of flowing electrons at high speed is formed. The electron transit layer 112 may be an undoped i-type GaN layer to which no impurities are artificially added.

  The spacer layer 114 is formed on the electron transit layer 112. The spacer layer 114 is formed of a different kind of semiconductor material having a band gap different from that of the electron transit layer 112. Since the electron transit layer 112 and the spacer layer 114 form a heterojunction, the electron transit layer 112 can form a binary electron gas in a region of about 10 nm near the interface with the spacer layer 114. The spacer layer 114 may be an undoped i-type AlGaN layer.

  The electron supply layer 116 is formed on the spacer layer 114. The electron supply layer 116 supplies electrons to the electron transit layer 112 through the spacer layer 114. The electron supply layer 116 may be an n-type AlGaN layer doped with impurities.

  The protective layer 118 is formed on the electron supply layer 116. For example, the protective layer 118 prevents and protects the oxidation of Al or the like in the electron supply layer 116. The protective layer 118 may be an n-type GaN layer doped with impurities. Note that the protective layer 118 may be omitted when the influence of oxidation of Al or the like in the electron supply layer 116 is small.

The gate insulating film 120 is provided on the semiconductor layer 110. The gate insulating film 120 is formed of a high dielectric constant material that reduces leakage current that flows out through the tunnel effect or the like. For example, the gate insulating film 120 includes an insulating material such as Ta (tantalum) oxide, Hf (hafnium) oxide, HfAl (hafnium aluminum) oxide, La (lanthanum) oxide, or Y (yttrium) oxide. . As an example, the gate insulating film 120 includes Ta ₂ O ₅ (tantalum oxide).

  The gate electrode 130 is provided on the gate insulating film 120. The gate electrode 130 is formed as an electrode having an insulated gate structure for applying a gate voltage to the semiconductor layer 110 through the gate insulating film 120. The gate electrode may include Ni (nickel), Pt (platinum), Au (gold), Ti (titanium), or the like. The gate electrode 130 may have a wiring connection portion. The wiring connection portion may be electrically connected to an external circuit that supplies a gate voltage by gold plating or wire bonding.

  The gate boundary film 140 is provided on the gate insulating film 120 and is in contact with the gate electrode 130 at least at a part of the end of the gate electrode 130 on the gate insulating film 120. Here, the gate boundary film 140 may cover a region from at least a part of the region where the gate electrode 130 is not provided on the gate insulating film 120 to at least a part of the gate electrode 130. The gate boundary film 140 may be provided so as to cover the surface of the gate electrode 130 other than the wiring connection portion.

The gate boundary film 140 includes an insulating material such as Ta (tantalum) oxide, Hf (hafnium) oxide, HfAl (hafnium aluminum) oxide, La (lanthanum) oxide, or Y (yttrium) oxide. Good. As an example, the gate boundary film 140 includes Ta ₂ O ₅ (tantalum oxide).

  Here, the gate boundary film 140 and the gate insulating film 120 include the same kind of insulating material. For example, the gate boundary film 140 and the gate insulating film 120 are formed of substantially the same insulating material. Instead, the gate boundary film 140 and the gate insulating film 120 may have substantially the same main elements or main components. Instead, the gate boundary film 140 and the gate insulating film 120 may have substantially the same type or composition of elements contained in the main component of the insulating material.

  As a result, the semiconductor device 100 can prevent the formation of a different interface between the gate insulating film 120 and the gate boundary film 140 by forming a different material. Therefore, since the gate electrode 130 does not contact the heterogeneous interface at the electrode end portion, it is possible to prevent electrons from being trapped in a trap level or the like formed at the heterogeneous interface.

  The protective film 150 is an insulating film provided on the gate electrode 130 and the gate boundary film 140. The protective film 150 includes an insulating material different from the gate boundary film 140 and the gate insulating film 120. As an example, the protective film includes SiN (silicon nitride) as an insulating material. As a result, the semiconductor device 100 can reinforce the protective film on the surface and reduce trap levels and the like near the surface of the gate boundary film 140.

  The source electrode 160 and the drain electrode 170 are provided on the semiconductor layer 110. The source electrode 160 and the drain electrode 170 are preferably formed so as to be in contact with the electron supply layer 116. The source electrode 160 and the drain electrode 170 may be in ohmic contact with the semiconductor layer 110. The source electrode 160 and the drain electrode 170 may include Ni (nickel), Pt (platinum), Au (gold), Al (aluminum), Ti (titanium), or the like.

  Each of the source electrode 160 and the drain electrode 170 may have a wiring connection portion. Each wiring connection portion may be electrically connected to an external circuit to be connected to the source electrode 160 or the drain electrode 170 by gold plating or wire bonding.

  Here, the gate insulating film 120 may be provided between the source electrode 160 and the drain electrode 170. Further, the gate insulating film 120 may be provided so as to further cover at least part of the source electrode 160 and the drain electrode 170. In this case, the gate insulating film 120 may be provided so as to cover the surface of the source electrode 160 and the drain electrode 170 other than the wiring connection portion.

  The gate boundary film 140 may be provided so as to cover a region from the gate electrode 130 to the source electrode 160 and a region from the gate electrode 130 to the drain electrode 170. Further, the gate boundary film may be provided so as to further cover at least a part of the source electrode 160 and the drain electrode 170. In this case, the gate boundary film 140 may be provided so as to cover the surface of the source electrode 160 and the drain electrode 170 other than the wiring connection portion.

  FIG. 2 shows a manufacturing flow of the semiconductor device 100 according to the present embodiment. 3A to 3F show configuration examples of the semiconductor device 100 formed at each stage of the manufacturing flow.

  First, the semiconductor layer 110 is formed on the substrate 10 (S200). The semiconductor layer 110 may be formed by a MOVPE method (Metal Organic Vapor Phase Epitaxy), an MBE method (Molecular Beam Epitaxy), or the like. FIG. 3A shows a configuration example at a stage where the semiconductor layer 110 of the semiconductor device 100 according to this embodiment is formed.

  Next, the source electrode 160 and the drain electrode 170 are formed (S210). The source electrode 160 and the drain electrode 170 may be formed in a region where the electron supply layer 116 is exposed by removing the protective layer 118 by etching. Here, the region where the electrode is formed may be removed from the protective layer 118 by wet etching using a liquid chemical. Alternatively, the region where the electrode is formed may be removed by dry etching using reactive gas, ions, radicals, or the like.

  For example, the source electrode 160 and the drain electrode 170 are formed by vapor deposition in which a material is heated and vaporized or sublimated to adhere to the surface of the substrate. Instead, the source electrode 160 and the drain electrode 170 may be formed by sputtering. In addition, as an example, the source electrode 160 and the drain electrode 170 are formed by forming a reverse pattern of a pattern to be formed on a substrate with a photoresist or the like, depositing a thin film to be formed, and then removing unnecessary portions other than the pattern together with the photoresist. It is formed by the lift-off method to be removed.

  The source electrode 160 and the drain electrode 170 formed on the electron supply layer 116 are annealed at a temperature of about 500 ° C. or higher to form an ohmic junction. As an example, the source electrode 160 and the drain electrode 170 are annealed at 600 ° C. FIG. 3B shows a configuration example at a stage where the source electrode 160 and the drain electrode 170 are formed on the semiconductor layer 110 according to this embodiment.

Next, the gate insulating film 120 is formed on the semiconductor layer 110 (S220). The gate insulating film 120 may be formed by sputtering. For example, the gate insulating film 120 is formed by RF sputtering in which a high frequency voltage is applied to a target of an insulator to perform sputtering. Here, Ta ₂ O ₅ (tantalum oxide) may be used as the insulator target. As a result, the gate insulating film 120 can be made of Ta oxide.

  The gate insulating film 120 may have a thickness of 10 to 100 nm. More preferably, it may have a film thickness of 20 to 50 nm. FIG. 3C shows a configuration example at the stage where the gate insulating film 120 is formed on the semiconductor layer 110 according to this embodiment.

  Next, the gate electrode 130 is formed on the gate insulating film 120 (S230). For example, the gate electrode 130 is formed by vapor deposition. Alternatively, the gate electrode 130 may be formed by sputtering. For example, the gate electrode 130 is formed by a lift-off method. The gate electrode 130 may be formed by depositing a plurality of electrode materials. FIG. 3D shows a configuration example at the stage where the gate electrode 130 is formed on the gate insulating film 120 according to the present embodiment.

Next, a gate boundary film 140 that is in contact with the gate electrode 130 at least at a part of the end of the gate electrode 130 on the gate insulating film 120 is formed on the gate insulating film 120 using the same kind of insulating material as the gate insulating film 120. (S240). The gate boundary film 140 may be formed by sputtering. As an example, the gate boundary film 140 is formed by RF sputtering. Here, Ta ₂ O ₅ (tantalum oxide) may be used as the insulator target. As a result, the gate boundary film 140 can be made of the same Ta oxide as the gate insulating film 120.

  The gate boundary film 140 may have a thickness of 1 to 50 nm. More preferably, it may have a film thickness of 2 to 10 nm. FIG. 3E shows a configuration example at a stage where the gate boundary film 140 is formed on the gate insulating film 120 and the gate electrode 130 according to the present embodiment.

  Next, the protective film 150 including an insulating material different from the gate boundary film 140 and the gate insulating film 120 is formed on the gate electrode 130 and the gate boundary film 140 (S250). The protective film 150 may be formed by a CVD method (Chemical Vapor Deposition). As an example, the protective film 150 is formed of SiN having a thickness of 200 nm. FIG. 3F shows a configuration example at a stage where the protective film 150 is formed on the gate boundary film 140 according to the present embodiment.

  The semiconductor device 100 which is GaN HEMT is manufactured by the above Example. The semiconductor device 100 can form a GaN MIS (Metal-Insulator-Semiconductor) -HEMT structure having high breakdown voltage, high output, and high frequency characteristics.

  FIG. 4 shows an example of pulse characteristics of a semiconductor device in which the gate boundary film 140 is not formed. In the case of this semiconductor device, after forming the gate electrode 130 on the gate insulating film 120, the protective film 150 is formed. Therefore, a heterogeneous interface between the gate insulating film 120 and the protective film 150 is also formed in the vicinity of the gate electrode 130.

  In the figure, the horizontal axis represents the drain-source voltage Vds of the semiconductor device, and the vertical axis represents the current Ids flowing between the drain and source. Each current-voltage characteristic shows the result of applying a pulse voltage to Vds and the gate-source voltage Vgs. The current-voltage characteristics plotted with black circles indicate the current-voltage characteristics at a pulse width of 5 μs when Vgs is changed to 2, −2, −4, and −6 V from the state of Vds = 0 V and Vgs = 0 V.

  As an initial condition, since no voltage is applied to Vds and Vgs in the semiconductor device, it is considered that carriers are hardly trapped even if a trap level is formed in the vicinity of the gate electrode. Therefore, the current-voltage characteristics are observed to have substantially the same shape as the DC characteristics in which a DC voltage is applied to Vds and Vgs.

  The current-voltage characteristics plotted with white squares indicate the current voltage at a pulse width of 5 μs when Vgs is changed to 2, −2, −4, and −6 V from the state of Vds = 25 V and Vgs = −10 V. Show properties. That is, the white square current-voltage characteristics indicate pulse characteristics obtained by changing the initial conditions of the current-voltage characteristics plotted with black circles. Thus, it is observed that the current-voltage characteristics change significantly by changing the initial conditions.

  As a result, by applying a voltage to Vds and Vgs as an initial condition, a pulse voltage is applied as a result of trapping electrons as carriers in the trap level existing in the vicinity of the gate electrode 130 before applying the pulse voltage. In this case, it is considered that the time for compensating or relaxing the carrier is added and the pulse characteristics are affected. A decrease in current due to the trap existing in the vicinity of the gate electrode 130 in the pulse characteristics or the like is called current collapse.

  FIG. 5 shows an example of pulse characteristics of the semiconductor device 100 according to the present embodiment. The horizontal axis in the figure indicates Vds as in FIG. 4, and the vertical axis indicates Ids. Each current-voltage characteristic shows the result of applying a pulse voltage to Vds and Vgs, as in FIG.

  The current-voltage characteristics plotted with black circles indicate the current-voltage characteristics at a pulse width of 5 μs when Vgs is changed to 2, −2, −4, and −6 V from the state of Vds = 0 V and Vgs = 0 V. The current-voltage characteristics plotted with white squares indicate the current voltage at a pulse width of 5 μs when Vgs is changed to 2, −2, −4, and −6 V from the state of Vds = 25 V and Vgs = −10 V. Show properties.

  From the figure, it can be seen that the semiconductor device 100 according to the present example shows substantially the same current-voltage characteristic tendencies even when the initial conditions are changed. That is, it can be seen that the semiconductor device 100 reduces the phenomenon of current collapse by preventing the formation of interface states while reducing the gate leakage current.

  In the semiconductor device 100, the gate insulating film 120 and the gate boundary film 140, which are insulating films in the vicinity of the gate electrode 130, are made of the same type of insulating material, thereby preventing the formation of trap levels in the vicinity of the gate electrode 130 due to different interfaces. Therefore, the phenomenon of current collapse can be reduced in this way. In addition, since the semiconductor device 100 further includes the protective film 150 in addition to the gate boundary film 140, the protective film 150 can prevent the influence of trap levels existing in the gate boundary film 140.

  According to the semiconductor device 100 of the present embodiment described above, it has high breakdown voltage, high output, and high frequency characteristics, and improves high frequency characteristics when a pulse is applied to the gate electrode while reducing gate leakage current. Can do. Although the semiconductor device 100 of the present embodiment has been described with respect to the GaN MIS HEMT, the semiconductor device 100 may be a III-V group compound semiconductor MIS HEMT instead.

  Further, the semiconductor device 100 may be a pseudomorphic HEMT in which the electron transit layer 112 is changed to another material that matches the pseudo lattice to realize higher mobility and higher electron concentration.

  FIG. 6 shows a configuration example of the test apparatus 410 according to this embodiment together with the device under test 400. The test apparatus 410 tests at least one device under test 400 such as an analog circuit, a digital circuit, an analog / digital mixed circuit, a memory, and a system on chip (SOC). The test apparatus 410 inputs a test signal based on a test pattern for testing the device under test 400 to the device under test 400, and the device under test based on an output signal output from the device under test 400 according to the test signal. The quality of 400 is judged.

  The test apparatus 410 includes a test unit 420, a signal input / output unit 430, and a control device 440. The test unit 420 tests the device under test 400 by exchanging electrical signals with the device under test 400. The test unit 420 includes a test signal generation unit 423 and an expected value comparison unit 426.

  The test signal generator 423 generates a plurality of test signals to be supplied to the device under test 400. The test signal generator 423 may generate an expected value of the response signal output from the device under test 400 according to the test signal. The test signal generator 423 may be connected to the plurality of devices under test 400 via the signal input / output unit 430 to test the plurality of devices under test 400.

  The expected value comparison unit 426 compares the received data value received by the signal input / output unit 430 with the expected value. The expected value comparison unit 426 may receive the expected value from the test signal generation unit 423. The test apparatus 410 may determine pass / fail of the device under test 400 based on the comparison result of the expected value comparison unit 426.

  The signal input / output unit 430 is connected to one or more devices under test 400 and exchanges test signals between the test apparatus 410 and the device under test 400. The signal input / output unit 430 may be a performance board on which a plurality of devices under test 400 are mounted. The signal input / output unit 430 includes the semiconductor device 100.

  The semiconductor device 100 is provided in a transmission path between the device under test 400 and the test unit 420, and switches between electrically connecting or disconnecting the device under test 400 and the test unit 420. The test apparatus 410 may perform electrical connection or disconnection by the semiconductor device 100 according to the present embodiment. Instead, the test apparatus 410 may perform electrical connection or disconnection by an electronic circuit including the semiconductor device 100 according to the present embodiment.

  In this example, the example in which the signal input / output unit 430 is connected to one device under test 400 and one semiconductor device 100 is provided for each of the input signal line and the output signal line of one device under test 400 has been described. Instead, the signal input / output unit 430 may be connected to a plurality of devices under test 400, and one semiconductor device 100 may be provided for each of the input signal lines and the output signal lines of the plurality of devices under test 400. Further, when there is one signal input / output line connected from the signal input / output unit 430 to one device under test 400, one semiconductor device 100 may be provided in one input / output line.

  The control device 440 transmits a control signal to the test unit 420 and the signal input / output unit 430 in order to execute the test of the test device 410. The control device 440 transmits a control signal that causes the test unit 420 to generate a test signal or compare a test result with an expected value in accordance with a test program. Further, the control device 440 instructs connection of the semiconductor device 100 provided in the signal input / output line to be connected and disconnection of the semiconductor device 100 provided in the signal input / output line to be disconnected according to the test program. An instruction or the like is transmitted to the signal input / output unit 430.

  The above-described test apparatus 410 in the present embodiment has a high breakdown voltage, high output, and high frequency characteristics, and is a semiconductor device that improves high frequency characteristics when a pulse is applied to the gate electrode while reducing gate leakage current. 100 can be used to perform the test.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 substrate, 100 semiconductor device, 110 semiconductor layer, 112 electron transit layer, 114 spacer layer, 116 electron supply layer, 118 protective layer, 120 gate insulating film, 130 gate electrode, 140 gate boundary film, 150 protective film, 160 source electrode , 170 Drain electrode, 400 Device under test, 410 Test device, 420 Test unit, 423 Test signal generation unit, 426 Expected value comparison unit, 430 Signal input / output unit, 440 Control device

Claims (11)

A semiconductor layer formed on a substrate;
A gate insulating film formed on the formed semiconductor layer;
A gate electrode provided on the formed gate insulating film;
A gate boundary film provided on the gate insulating film and in contact with the gate electrode at least at a part of an end of the gate electrode on the gate insulating film;
An insulating protective film provided on the gate electrode and the gate boundary film;
With
The gate boundary film and the gate insulating film are formed of the same insulating material, and include tantalum, hafnium, hafnium aluminum, lanthanum, or yttrium.
The semiconductor device , wherein the protective film includes an insulating material different from the gate boundary film and the gate insulating film . The semiconductor device according to claim 1 , wherein the protective film includes silicon nitride as an insulating material. The gate boundary layer and the gate insulating film, a semiconductor device according to claim 1 or 2 comprising tantalum oxide as an insulating material. The gate boundary film, in any one of claims 1 to 3 from at least a portion of an area where the gate electrode is not provided in the gate insulating film covering a region extending on at least a portion of said gate electrode The semiconductor device described. A source electrode and a drain electrode provided on the semiconductor layer;
The gate insulating film is provided between the source electrode and the drain electrode;
The gate boundary layer The semiconductor device according to any one of claims 1 to 4 from region and said gate electrode extending to the source electrode from the gate electrode covers a region extending to the drain electrode. The semiconductor device according to claim 5 , wherein the gate insulating film is provided so as to further cover the surface of the source electrode and the drain electrode other than the wiring connection portion. The semiconductor device according to claim 5 , wherein the gate boundary film further covers at least a part of the source electrode and the drain electrode. The semiconductor layer, the semiconductor device according to any one of claims 1 formed by group III-V compound semiconductor 7. The semiconductor device, the semiconductor device according to any one of claims 1 to 8 is GaN HEMT. A test apparatus for testing a device under test,
A test section for transmitting an electrical signal to and from the device under test to test the device under test;
Wherein provided in the transmission path between the device under test and the test unit, the to any one of claims 1 to switch whether or disconnecting an electrical connection between the device under test and the test section 9 A semiconductor device according to the description;
A test apparatus comprising: A method for manufacturing a semiconductor device, comprising:
Forming a semiconductor layer on the substrate;
Forming a gate insulating film on the formed semiconductor layer;
Forming a gate electrode on the formed gate insulating film;
On the gate insulating film, forming a gate boundary film in contact with the gate electrode in at least a part of the end of the gate electrode on the gate insulating film, using the same insulating material as the gate insulating film;
Forming an insulating protective film including an insulating material different from the gate boundary film and the gate insulating film on the gate electrode and the gate boundary film;
With
The gate boundary film and the gate insulating film may be made of tantalum, hafnium, hafnium aluminum, lanthanum, or yttrium .

Images