WO2024040516A1 - Nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability - Google Patents

Nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability Download PDF

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WO2024040516A1
WO2024040516A1 PCT/CN2022/114810 CN2022114810W WO2024040516A1 WO 2024040516 A1 WO2024040516 A1 WO 2024040516A1 CN 2022114810 W CN2022114810 W CN 2022114810W WO 2024040516 A1 WO2024040516 A1 WO 2024040516A1
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Prior art keywords
nitride
switching element
electrode
conduction
terminal
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PCT/CN2022/114810
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French (fr)
Inventor
Rong Yang
Hui Yan
Sichao LI
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Innoscience (Zhuhai) Technology Co., Ltd.
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Application filed by Innoscience (Zhuhai) Technology Co., Ltd. filed Critical Innoscience (Zhuhai) Technology Co., Ltd.
Priority to CN202280004780.XA priority Critical patent/CN115769379B/en
Priority to CN202410084513.9A priority patent/CN117954486A/en
Priority to PCT/CN2022/114810 priority patent/WO2024040516A1/en
Publication of WO2024040516A1 publication Critical patent/WO2024040516A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2637—Circuits therefor for testing other individual devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention generally relates to electronic device with wafer-level dynamic on-resistance monitoring capability. More specifically, the present invention relates to gallium nitride (GaN) electronic device with dynamic on-resistance monitoring capability.
  • GaN gallium nitride
  • GaN gallium nitride
  • MOSFET silicon Metal Oxide Semiconductor Field Effect Transistor
  • HEMT GaN High-Electron-Mobility Transistor
  • MOSFET silicon Metal Oxide Semiconductor Field Effect Transistor
  • HEMT GaN High-Electron-Mobility Transistor
  • GaN power device may have an unwanted current collapse phenomenon resulting in increase in dynamic on-resistance which can cause device degradation and failure. Therefore, dynamic on-resistance measurement is important for performance evaluation and circuit diagnosis of GaN power devices and to ensure reliability of system operation. Besides, it is challenging to evaluate drift of on-resistance during design stage.
  • One objective of the present invention is to provide a cost-effective approach to realize wafer-level monitoring of on-resistance of power devices such that development cycle of the power devices can be greatly reduced. Moreover, through integrating capability of monitoring drain-to-source voltage into integrated circuit (IC) chips, protection circuits can be provided to the IC such that the IC can be more reliable.
  • IC integrated circuit
  • a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability comprises a control terminal, a first conduction terminal, a second conduction terminal and a voltage-sensing terminal.
  • the nitride-based electronic device further comprises a power switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the power switching element being electrically connected to the control terminal, the first conduction electrode of the power switching element being electrically connected to the first conduction terminal and the second conduction electrode of the power switching element electrically connected to the second conduction terminal; a sense switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the sense switching element being electrically connected to the control terminal, the first conduction electrode of the sense switching element being electrically connected to the first conduction terminal; a first clamping element having a positive electrode electrically connected to the voltage-sensing terminal and a negative electrode electrically connected to the second conduction terminal; and a second clamping element having a positive electrode electrically connected to the second conduction terminal and a negative electrode electrically connected to voltage-sensing terminal.
  • FIG. 1 shows a simplified circuit diagram for a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability according to some embodiments of the present invention
  • FIG. 2 shows a simplified isometric view of a nitride-based semiconductor IC chip according to various embodiments of the present invention
  • FIG. 3 shows a simplified cross-sectional view of a nitride-based semiconductor IC chip according to various embodiments of the present invention
  • FIG. 4A –4C show different stages of a simplified process flow for manufacturing a nitride-based semiconductor IC chip according to various embodiments of the present invention.
  • FIG. 1 is a simplified circuit diagram for a nitride-based electronic device with dynamic on-resistance monitoring capability according to some embodiments of the present invention.
  • the device 10 may comprise a control terminal Ctrl, a first conduction terminal Cdct1, a second conduction terminal Cdct2 and a voltage-sensing terminal VS.
  • the device 10 may further comprise a power switching element Q1 having a control electrode Q1_Ctrl, a first conduction electrode Q1_Cdct1 and a second conduction electrode Q1_Cdct2; the control electrode being electrically connected to the control terminal Ctrl, the first conduction electrode being electrically connected to the first conduction terminal Cdct1 and the second conduction electrode electrically connected to the second conduction terminal Cdct2.
  • the device 10 may further comprise a sense switching element Q2 having a control electrode Q2_Ctrl, a first conduction electrode Q2_Cdct1 and a second conduction electrode Q2_Cdct2; the control electrode being electrically connected to the control terminal Ctrl, the first conduction electrode being electrically connected to the first conduction terminal Cdct1.
  • the device 10 may further comprise a first clamping element D1 having a positive electrode D1_P electrically connected to the voltage-sensing terminal VS and a negative electrode D1_N electrically connected to the second conduction terminal Cdct2.
  • the device 10 may further comprise a second clamping element D2 having a positive electrode D2_P electrically connected to the second conduction terminal Cdct2 and a negative electrode D2_N electrically connected to voltage-sensing terminal VS.
  • a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element Q1 is generated at the voltage-sensing terminal VS.
  • the sense switching element Q2 has an on-resistance greater than an on-resistance of the power switching element Q1.
  • the sense switching element Q2 may have on-resistance approximately 250 times of on-resistance of the power switching element Q1.
  • the power switching element Q1 is a first nitride-based transistor having a gate G acting as the control electrode Q1_Ctrl of the power switching element, a drain D acting as the first conduction electrode Q1_Cdct1 of the power switching element and a source S acting as the second conduction electrode Q1_Cdct2 of the power switching element.
  • the first nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  • the sense switching element Q2 is a second nitride-based transistor having a gate G acting as the control electrode Q1_Ctrl of the sense switching element, a drain D acting as the first conduction electrode Q2_Cdct1 of the sense switching element and a source S acting as the second conduction electrode Q2_Cdct2 of the sense switching element.
  • the second nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  • the first clamping element D1 is a third nitride-based transistor having a gate G and a source S being electrically connected together to act as the positive electrode D1_P of the first clamping element D1 and a drain D configured to act as the negative electrode D1_N of the first clamping element D1.
  • the second clamping element D2 is a fourth nitride-based transistor having a gate G and a source S being electrically connected together to act as the positive electrode D2_P of the second clamping element D2 and a drain D configured to act as the negative electrode D2_N of the second clamping element D2.
  • the power switching element Q1, the sense switching element Q2, the first clamping element D1 and the second clamping element D2 are integrated into a nitride-based integrated circuit (IC) chip so as to realize wafer-level monitoring of on-resistance of the power switching element Q1.
  • FIGS. 2 and 3 depict a simplified isometric view and a simplified cross-sectional view of a nitride-based semiconductor IC chip 100 according to various embodiments of the present invention respectively.
  • the semiconductor chip 100 may include power switching element Q1, sense switching element Q2, first clamping element D1 and second clamping element D2.
  • Each of the power switching element Q1, sense switching element Q2, first clamping element D1 and second clamping element D2 may be made of a transistor formed on a stacked semiconductor structure including at least a substrate 102; a first nitride-based semiconductor layer 104 disposed above the substrate 102; and a second nitride-based semiconductor layer 106 disposed above the first nitride-based semiconductor layer 104.
  • the exemplary materials of the nitride-based semiconductor layers 104 and 106 are selected such that the nitride-based semiconductor layer 106 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 104, which causes electron affinities thereof different from each other and forms a heterojunction therebetween.
  • the nitride-based semiconductor layer 104 is an undoped GaN layer having a bandgap of approximately 3.4 eV
  • the nitride-based semiconductor layer 106 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.
  • the nitride-based semiconductor layers 104 and 106 can serve as a channel layer and a barrier layer, respectively.
  • a triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
  • the multi-channel switching device is available to include one or more GaN-based high-electron-mobility transistors (HEMT) .
  • HEMT high-electron-mobility transistors
  • the substrate 102 may be a semiconductor substrate.
  • the exemplary materials of the substrate 102 can include, for example but are not limited to, Si, p-doped Si, n-doped Si, SiC, GaN, Sapphire, or other suitable semiconductor materials.
  • the exemplary materials of the nitride-based semiconductor layer 104 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the exemplary structures of the nitride-based semiconductor layer 104 can include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.
  • the exemplary materials of the nitride-based semiconductor layer 106 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl y Ga (1–x–y) N where x+y ⁇ 1, Al y Ga (1–y) N where y ⁇ 1.
  • the semiconductor chip 100 may further include a buffer layer (not illustrated) and a nucleation layer 108, or a combination thereof.
  • the buffer layer and the nucleation layer 108 may be disposed between the substrate 102 and the nitride-based semiconductor layer 104.
  • the buffer layer and nucleation layer 108 can be configured to reduce lattice and thermal mismatches between the substrate 102 and the nitride-based semiconductor layer 104, thereby curing defects due to the mismatches/difference.
  • the buffer layer may include a III-V compound.
  • the III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof.
  • the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.
  • the exemplary material of the nucleation layer 108 can include, for example but is not limited to AlN or any of its alloys.
  • Each of the transistors Q1, Q2, D1 and D2 may further include a plurality of gate structures 110 and a plurality of source/drain (S/D) electrodes 116 disposed on/over/above the stacked semiconductor structure.
  • S/D electrodes 116 can serve as a source electrode or a drain electrode, depending on the device design.
  • the S/D electrodes 116 can be located at two opposite sides of the corresponding gate structure 110 although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device.
  • Each of the gate structure 110 can be arranged such that each of the gate structure 110 is located between at least two of the S/D electrodes 116.
  • the adjacent S/D electrodes 116 are symmetrical about the gate structure 110 therebetween.
  • the adjacent S/D electrodes 116 can be optionally asymmetrical about the gate structure 110 therebetween. That is, one of the S/D electrodes 116 may be closer to the gate structure 110 than another one of the S/D electrodes 116.
  • each of the gate structures 110 may include an optional gate semiconductor layer and a gate metal layer.
  • the gate semiconductor layer and the gate metal layer are stacked on the nitride-based semiconductor layer 106.
  • the gate semiconductor layer is between the nitride-based semiconductor layer 106 and the gate metal layer.
  • the gate semiconductor layer and the gate metal layer may form a Schottky barrier.
  • each of the transistors Q1, Q2, D1 and D2 may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layer and the gate metal layer.
  • the gate semiconductor layer may be a p-type doped III-V compound semiconductor layer.
  • the p-type doped III-V compound semiconductor layer may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure 110 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the transistors Q1, Q2, D1 and D2 may have a normally-off characteristic for forming enhancement mode devices, which are in a normally-off state when their gate electrodes are at approximately zero bias.
  • a threshold voltage i.e., a minimum voltage required to form an inversion layer below the gate structures 110
  • the zone of the 2DEG region below the gate structures 110 is kept blocked, and thus no current flows therethrough.
  • gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.
  • the p-type doped III-V compound semiconductor layers can be omitted, such that each of the transistors Q1, Q2, D1 and D2 is a depletion-mode device, which means each of the transistors Q1, Q2, D1 and D2 is in a normally-on state at zero gate-source voltage.
  • the exemplary materials of the p-type doped III-V compound semiconductor layers can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.
  • the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
  • the gate electrodes may include metals or metal compounds.
  • the gate electrodes may be formed as a single layer, or plural layers of the same or different compositions.
  • the exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds.
  • the exemplary materials of the gate electrodes may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.
  • the optional dielectric layer can be formed by a single layer or more layers of dielectric materials.
  • the exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO x layer, a SiN x layer, a high-k dielectric material (e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc) , or combinations thereof.
  • a high-k dielectric material e.g., HfO 2 , Al 2 O 3 , TiO 2 , HfZrO, Ta 2 O 3 , HfSiO 4 , ZrO 2 , ZrSiO 2 , etc
  • the S/D electrodes 116 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof.
  • the exemplary materials of the S/D electrodes 116 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof.
  • the S/D electrodes 116 may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes 116 may form ohmic contacts with the nitride-based semiconductor layer 106.
  • the ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes 116.
  • each of the S/D electrodes 116 is formed by at least one conformal layer and a conductive filling.
  • the conformal layer can wrap the conductive filling.
  • the exemplary materials of the conformal layer for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof.
  • the exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
  • deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • MOCVD metal organic CVD
  • PECVD plasma enhanced CVD
  • LPCVD low-pressure CVD
  • plasma-assisted vapor deposition epitaxial growth, or other suitable processes.
  • the process for forming the passivation layers serving as a planarization layer generally includes a chemical mechanical polish (CMP) process.
  • CMP chemical mechanical polish
  • the process for forming the conductive vias generally includes forming vias in a passivation layer and filling the vias with conductive materials.
  • the process for forming the conductive traces generally includes photolithography, exposure and development, etching, other suitable processes, or combinations thereof.
  • a substrate 102 (with typical thickness about 0.7 to 1.2 mm) is provided.
  • two nitride-based semiconductor layers 104 and 106 can then be formed on the substrate 102 using the above-mentioned deposition techniques.
  • the nitride-based semiconductor layer 104 serves as a primary current channel and the nitride-based semiconductor layer 106 serves as a barrier layer.
  • a 2DEG region is formed adjacent to a heterojunction interface between the nitride-based semiconductor layer 104 and the nitride-based semiconductor layer 106.
  • Formation of nitride-based semiconductor layers 104 and 106 can include depositing a layer of GaN or InGaN material typically about 0.01 to about 0.5 ⁇ m in thickness to form current conducting region, and depositing a layer of material composed of AlGaN where the Al fraction (which is the content of Al such that Al fraction plus Ga fraction equals 1) is in a range of about 0.1 to about 1.0 and the thickness is in a range between about 0.01 and about 0.03 ⁇ m to form barrier layer.
  • Al fraction which is the content of Al such that Al fraction plus Ga fraction equals 1
  • gate structure 110 can be formed, for example, by depositing p-type GaN material on a surface of nitride-based semiconductor layer 106, etching the gate structure 110 from the p-type GaN material, and forming a refractory metal contact such as tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tungsten (W) , or tungsten silicide (WSi 2 ) over the GaN material. It should be understood that other known methods and materials for providing a gate structure 110 can also be used.
  • S/D electrodes 116 can be formed from any known ohmic contact metals, such as Ti and/or Al, along with a capping metal such as Ni, Au, Ti or TiN.
  • the metal and gate layer are each preferably about 0.01 to about 1.0 ⁇ m in thickness, and then annealed at high temperature, such as 800°C for 60 seconds.
  • passivation layers and routing (conductive) layers may then be deposited and etched to form connections between the gate structures 110 and electrodes 116 with external circuits.
  • a second passivation layer may be disposed on the first passivation layer and covering the S/D electrodes; one or more first conductive vias may be disposed within the second passivation layer; a first conductive layer may be disposed on the second passivation layer and patterned to form one or more first conductive lines; a third passivation layer may be disposed on the first conductive layer and covering the one or more first conductive lines; may be one or more second conductive vias disposed within the third passivation layer; may be a second conductive layer disposed on the third passivation layer and patterned to form one or more second conductive lines; and a protection layer may be disposed above the second conductive layer and having one or more openings to expose one or more conductive pads.

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Abstract

The present disclosure provides a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability which can be integrated into an integrated circuit chip. The nitride-based electronic device comprises: a control terminal, a first conduction terminal, a second conduction terminal, a voltage-sensing terminal, a power switching element, a sense switching element, a first clamping element and a second clamping element. When the power switching element is turned on by a control signal received by the control terminal, a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element is generated at the voltage-sensing terminal. The present invention provides a cost-effective approach to realize wafer-level monitoring of on-resistance of power devices such that development cycle of the power devices can be greatly reduced.

Description

NITRIDE-BASED ELECTRONIC DEVICE WITH WAFER-LEVEL DYNAMIC ON-RESISTANCE MONITORING CAPABILITY Field of the Invention:
The present invention generally relates to electronic device with wafer-level dynamic on-resistance monitoring capability. More specifically, the present invention relates to gallium nitride (GaN) electronic device with dynamic on-resistance monitoring capability.
Background of the Invention:
Group III-V material, such as gallium nitride (GaN) power devices have been widely used for high frequency electrical energy conversion systems because of low power losses and fast switching transition. In comparison with silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) , GaN High-Electron-Mobility Transistor (HEMT) has a much better figure of merit and more promising performance for high-power, high-frequency applications. However, GaN power device may have an unwanted current collapse phenomenon resulting in increase in dynamic on-resistance which can cause device degradation and failure. Therefore, dynamic on-resistance measurement is important for performance evaluation and circuit diagnosis of GaN power devices and to ensure reliability of system operation. Besides, it is challenging to evaluate drift of on-resistance during design stage.
Summary of the Invention:
One objective of the present invention is to provide a cost-effective approach to realize wafer-level monitoring of on-resistance of power devices such that development cycle of the power devices can be greatly reduced. Moreover, through integrating capability of monitoring drain-to-source voltage into integrated circuit (IC) chips, protection circuits can be provided to the IC such that the IC can be more reliable.
According to one aspect of the present invention, a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability is provided. The nitride-based electronic device comprises a control terminal, a first conduction terminal, a second conduction terminal and a voltage-sensing terminal. The nitride-based electronic device further comprises a power switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the power switching element being electrically connected to the control terminal, the first conduction electrode of the power switching element being electrically connected to the first conduction terminal and the second conduction electrode of the power switching element electrically connected to the second conduction terminal; a sense switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the sense switching element being electrically connected to the control terminal, the first conduction electrode of the sense switching element being electrically connected  to the first conduction terminal; a first clamping element having a positive electrode electrically connected to the voltage-sensing terminal and a negative electrode electrically connected to the second conduction terminal; and a second clamping element having a positive electrode electrically connected to the second conduction terminal and a negative electrode electrically connected to voltage-sensing terminal. When the power switching element is turned on by a control signal received by the control terminal, a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element is generated at the voltage-sensing terminal.
Brief Description of the Drawings:
Aspects of the present disclosure may be readily understood from the following detailed description with reference to the accompanying figures. The illustrations may not necessarily be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Common reference numerals may be used throughout the drawings and the detailed description to indicate the same or similar components.
FIG. 1 shows a simplified circuit diagram for a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability according to some embodiments of the present invention;
FIG. 2 shows a simplified isometric view of a nitride-based semiconductor IC chip according to various embodiments of the present invention;
FIG. 3 shows a simplified cross-sectional view of a nitride-based semiconductor IC chip according to various embodiments of the present invention;
FIG. 4A –4C show different stages of a simplified process flow for manufacturing a nitride-based semiconductor IC chip according to various embodiments of the present invention.
Detailed Description:
In the following description, preferred examples of the present disclosure will be set forth as embodiments which are to be regarded as illustrative rather than restrictive. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.
Reference in this specification to "one embodiment" or "an embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one of the embodiments of the invention. The appearances of the phrase "in one embodiment" or “in some embodiments” in various places in the specifications are not necessarily all referring to the same embodiments, nor are separate or alternative embodiments  mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others.
FIG. 1 is a simplified circuit diagram for a nitride-based electronic device with dynamic on-resistance monitoring capability according to some embodiments of the present invention. As shown, the device 10 may comprise a control terminal Ctrl, a first conduction terminal Cdct1, a second conduction terminal Cdct2 and a voltage-sensing terminal VS.
The device 10 may further comprise a power switching element Q1 having a control electrode Q1_Ctrl, a first conduction electrode Q1_Cdct1 and a second conduction electrode Q1_Cdct2; the control electrode being electrically connected to the control terminal Ctrl, the first conduction electrode being electrically connected to the first conduction terminal Cdct1 and the second conduction electrode electrically connected to the second conduction terminal Cdct2.
The device 10 may further comprise a sense switching element Q2 having a control electrode Q2_Ctrl, a first conduction electrode Q2_Cdct1 and a second conduction electrode Q2_Cdct2; the control electrode being electrically connected to the control terminal Ctrl, the first conduction electrode being electrically connected to the first conduction terminal Cdct1.
The device 10 may further comprise a first clamping element D1 having a positive electrode D1_P electrically connected to the voltage-sensing terminal VS and a negative electrode D1_N electrically connected to the second conduction terminal Cdct2.
The device 10 may further comprise a second clamping element D2 having a positive electrode D2_P electrically connected to the second conduction terminal Cdct2 and a negative electrode D2_N electrically connected to voltage-sensing terminal VS.
When the power switching element Q1 is turned on by a control signal received by the control terminal Ctrl, a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element Q1 is generated at the voltage-sensing terminal VS.
Preferably, the sense switching element Q2 has an on-resistance greater than an on-resistance of the power switching element Q1. For example, the sense switching element Q2 may have on-resistance approximately 250 times of on-resistance of the power switching element Q1.
In some embodiments, the power switching element Q1 is a first nitride-based transistor having a gate G acting as the control electrode Q1_Ctrl of the power switching element, a drain D acting as the first conduction electrode Q1_Cdct1 of the power switching element and a source S acting as the second conduction electrode Q1_Cdct2 of the power switching element. Preferably, the first nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
In some embodiments, the sense switching element Q2 is a second nitride-based transistor having a gate G acting as the control electrode Q1_Ctrl of the sense switching element, a drain D acting as the first conduction electrode Q2_Cdct1 of the sense switching element and a source S acting as the second conduction electrode Q2_Cdct2 of the sense switching element. Preferably, the second nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
In some embodiments, the first clamping element D1 is a third nitride-based transistor having a gate G and a source S being electrically connected together to act as the positive electrode D1_P of the first clamping element D1 and a drain D configured to act as the negative electrode D1_N of the first clamping element D1. The second clamping element D2 is a fourth nitride-based transistor having a gate G and a source S being electrically connected together to act as the positive electrode D2_P of the second clamping element D2 and a drain D configured to act as the negative electrode D2_N of the second clamping element D2.
In some embodiments, the power switching element Q1, the sense switching element Q2, the first clamping element D1 and the second clamping element D2 are integrated into a nitride-based integrated circuit (IC) chip so as to realize wafer-level monitoring of on-resistance of the power switching element Q1. FIGS. 2 and 3 depict a simplified isometric view and a simplified cross-sectional view of a nitride-based semiconductor IC chip 100 according to various embodiments of the present invention respectively.
Referring to FIGS. 2 and 3, the semiconductor chip 100 may include power switching element Q1, sense switching element Q2, first clamping element D1 and second clamping element D2. Each of the power switching element Q1, sense switching element Q2, first clamping element D1 and second clamping element D2 may be made of a transistor formed on a stacked semiconductor structure including at least a substrate 102; a first nitride-based semiconductor layer 104 disposed above the substrate 102; and a second nitride-based semiconductor layer 106 disposed above the first nitride-based semiconductor layer 104.
The exemplary materials of the nitride-based  semiconductor layers  104 and 106 are selected such that the nitride-based semiconductor layer 106 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 104, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 104 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 106 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based  semiconductor layers  104 and 106 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons  accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the multi-channel switching device is available to include one or more GaN-based high-electron-mobility transistors (HEMT) .
The substrate 102 may be a semiconductor substrate. The exemplary materials of the substrate 102 can include, for example but are not limited to, Si, p-doped Si, n-doped Si, SiC, GaN, Sapphire, or other suitable semiconductor materials.
The exemplary materials of the nitride-based semiconductor layer 104 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1. The exemplary structures of the nitride-based semiconductor layer 104 can include, for example but are not limited to, multilayered structure, superlattice structure and composition-gradient structures.
The exemplary materials of the nitride-based semiconductor layer 106 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl yGa  (1–x–y) N where x+y ≤ 1, Al yGa  (1–y) N where y ≤ 1.
In some embodiments, the semiconductor chip 100 may further include a buffer layer (not illustrated) and a nucleation layer 108, or a combination thereof. The buffer layer and the nucleation layer 108 may be disposed between the substrate 102 and the nitride-based semiconductor layer 104. The buffer layer and nucleation layer 108 can be configured to reduce lattice and thermal mismatches between the substrate 102 and the nitride-based semiconductor layer 104, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The exemplary material of the nucleation layer 108 can include, for example but is not limited to AlN or any of its alloys.
Each of the transistors Q1, Q2, D1 and D2 may further include a plurality of gate structures 110 and a plurality of source/drain (S/D) electrodes 116 disposed on/over/above the stacked semiconductor structure. Each of the S/D electrodes 116 can serve as a source electrode or a drain electrode, depending on the device design. The S/D electrodes 116 can be located at two opposite sides of the corresponding gate structure 110 although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. Each of the gate structure 110 can be arranged such that each of the gate structure 110 is located between at least two of the S/D electrodes 116.
In the exemplary illustration, for each of the transistors, the adjacent S/D electrodes 116 are symmetrical about the gate structure 110 therebetween. In some embodiments, the adjacent  S/D electrodes 116 can be optionally asymmetrical about the gate structure 110 therebetween. That is, one of the S/D electrodes 116 may be closer to the gate structure 110 than another one of the S/D electrodes 116.
In some embodiments, each of the gate structures 110 may include an optional gate semiconductor layer and a gate metal layer. The gate semiconductor layer and the gate metal layer are stacked on the nitride-based semiconductor layer 106. The gate semiconductor layer is between the nitride-based semiconductor layer 106 and the gate metal layer. The gate semiconductor layer and the gate metal layer may form a Schottky barrier. In some embodiments, each of the transistors Q1, Q2, D1 and D2 may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layer and the gate metal layer.
Specifically, the gate semiconductor layer may be a p-type doped III-V compound semiconductor layer. The p-type doped III-V compound semiconductor layer may create at least one p-n junction with the nitride-based semiconductor layer 106 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure 110 has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the transistors Q1, Q2, D1 and D2 may have a normally-off characteristic for forming enhancement mode devices, which are in a normally-off state when their gate electrodes are at approximately zero bias. In other words, when no voltage is applied to the gate electrodes or a voltage applied to the gate electrodes is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate structures 110) , the zone of the 2DEG region below the gate structures 110 is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layers, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.
In some embodiments, the p-type doped III-V compound semiconductor layers can be omitted, such that each of the transistors Q1, Q2, D1 and D2 is a depletion-mode device, which means each of the transistors Q1, Q2, D1 and D2 is in a normally-on state at zero gate-source voltage.
The exemplary materials of the p-type doped III-V compound semiconductor layers can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg.
In some embodiments, the gate electrodes may include metals or metal compounds. The gate electrodes may be formed as a single layer, or plural layers of the same or different  compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.
In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO x layer, a SiN x layer, a high-k dielectric material (e.g., HfO 2, Al 2O 3, TiO 2, HfZrO, Ta 2O 3, HfSiO 4, ZrO 2, ZrSiO 2, etc) , or combinations thereof.
In some embodiments, the S/D electrodes 116 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes 116 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The S/D electrodes 116 may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes 116 may form ohmic contacts with the nitride-based semiconductor layer 106. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes 116. In some embodiments, each of the S/D electrodes 116 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.
Different stages of a method for manufacturing a semiconductor chip according to the present invention are shown in FIGS. 4A-4C and described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes. The process for forming the passivation layers serving as a planarization layer generally includes a chemical mechanical polish (CMP) process. The process for forming the conductive vias generally includes forming vias in a passivation layer and filling the vias with conductive materials. The process for forming the conductive traces generally includes photolithography, exposure and development, etching, other suitable processes, or combinations thereof.
Referring to FIG. 4A, a substrate 102 (with typical thickness about 0.7 to 1.2 mm) is provided.
Referring to FIG. 4B, two nitride-based semiconductor layers 104 and 106 can then be formed on the substrate 102 using the above-mentioned deposition techniques. The nitride-based semiconductor layer 104 serves as a primary current channel and the nitride-based semiconductor layer 106 serves as a barrier layer. As a result, A 2DEG region is formed adjacent to a heterojunction interface between the nitride-based semiconductor layer 104 and the nitride-based semiconductor layer 106. Formation of nitride-based semiconductor layers 104 and 106 can include depositing a layer of GaN or InGaN material typically about 0.01 to about 0.5 μm in thickness to form current conducting region, and depositing a layer of material composed of AlGaN where the Al fraction (which is the content of Al such that Al fraction plus Ga fraction equals 1) is in a range of about 0.1 to about 1.0 and the thickness is in a range between about 0.01 and about 0.03 μm to form barrier layer.
Referring to FIG. 4C, one or more gate structure 110, S/D electrodes 116 are then formed over the nitride-based semiconductor layer 106. Gate structure 110 can be formed, for example, by depositing p-type GaN material on a surface of nitride-based semiconductor layer 106, etching the gate structure 110 from the p-type GaN material, and forming a refractory metal contact such as tantalum (Ta) , titanium (Ti) , titanium nitride (TiN) , tungsten (W) , or tungsten silicide (WSi 2) over the GaN material. It should be understood that other known methods and materials for providing a gate structure 110 can also be used. S/D electrodes 116 can be formed from any known ohmic contact metals, such as Ti and/or Al, along with a capping metal such as Ni, Au, Ti or TiN. The metal and gate layer are each preferably about 0.01 to about 1.0 μm in thickness, and then annealed at high temperature, such as 800℃ for 60 seconds.
It should be understood that passivation layers and routing (conductive) layers (not illustrated) may then be deposited and etched to form connections between the gate structures 110 and electrodes 116 with external circuits. In some embodiments, a second passivation layer may be disposed on the first passivation layer and covering the S/D electrodes; one or more first conductive vias may be disposed within the second passivation layer; a first conductive layer may be disposed on the second passivation layer and patterned to form one or more first conductive lines; a third passivation layer may be disposed on the first conductive layer and covering the one or more first conductive lines; may be one or more second conductive vias disposed within the third passivation layer; may be a second conductive layer disposed on the third passivation layer and patterned to form one or more second conductive lines; and a protection layer may be disposed above the second conductive layer and having one or more openings to expose one or more conductive pads.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations. While the apparatuses disclosed herein have been described with reference to particular structures, shapes, materials, composition of matter and relationships…etc., these descriptions and illustrations are not limiting. Modifications may be made to adapt a particular situation to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto.

Claims (25)

  1. A nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability, comprising:
    a control terminal, a first conduction terminal, a second conduction terminal and a voltage-sensing terminal;
    a power switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the power switching element being electrically connected to the control terminal, the first conduction electrode of the power switching element being electrically connected to the first conduction terminal and the second conduction electrode of the power switching element electrically connected to the second conduction terminal; and
    a sense switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the sense switching element being electrically connected to the control terminal, the first conduction electrode of the sense switching element being electrically connected to the first conduction terminal; and
    wherein when the power switching element is turned on by a control signal received by the control terminal, a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element is generated at the voltage-sensing terminal.
  2. The nitride-based electronic device according to claim 1, further comprising a first clamping element having a positive electrode electrically connected to the voltage-sensing terminal and a negative electrode electrically connected to the second conduction terminal.
  3. The nitride-based electronic device according to claim 2, further comprising a second clamping element having a positive electrode electrically connected to the second conduction terminal and a negative electrode electrically connected to voltage-sensing terminal.
  4. The nitride-based electronic device according to any one of claims 1 to 3, wherein the sense switching element has an on-resistance greater than an on-resistance of the power switching element.
  5. The nitride-based electronic device according to any one of claims 1 to 4, wherein the power switching element is a first nitride-based transistor having a gate acting as the control electrode of the power switching element, a drain acting as the first conduction electrode of the  power switching element and a source acting as the second conduction electrode of the power switching element.
  6. The nitride-based electronic device according to claim 5, wherein the first nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  7. The nitride-based electronic device according to any one of claims 1 to 6, wherein the sense switching element is a second nitride-based transistor having a gate acting as the control electrode of the sense switching element, a drain acting as the first conduction electrode of the sense switching element and a source acting as the second conduction electrode of the sense switching element.
  8. The nitride-based electronic device according to claim 7, wherein the second nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  9. The nitride-based electronic device according to any one of claims 1 to 8, wherein the first clamping element is a third nitride-based transistor having a gate and a source being electrically connected together to act as the positive electrode of the first clamping element and a drain configured to act as the negative electrode of the first clamping element.
  10. The nitride-based electronic device according to claim 9, wherein the third nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  11. The nitride-based electronic device according to any one of claims 1 to 10, wherein the second clamping element is a fourth nitride-based transistor having a gate and a source being electrically connected together to act as the positive electrode of the second clamping element and a drain configured to act as the negative electrode of the second clamping element.
  12. The nitride-based electronic device according to claim 11, wherein the third nitride-based transistor is a AlGaN/GaN enhancement-mode (E-mode) high-electron-mobility transistor (HEMT) .
  13. The nitride-based electronic device according to any one of claims 1 to 12, wherein the power switching element, the sense switching element, the first clamping element and the second clamping element are integrated into a nitride-based integrated circuit (IC) chip.
  14. The nitride-based electronic device according to claim 13, wherein the nitride-based IC chip comprises:
    a first nitride-based semiconductor layer disposed above a substrate;
    a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    one or more gate structures formed by patterning a gate semiconductor layer disposed on the second nitride-based semiconductor layer and patterning a gate metal layer disposed on the gate semiconductor layer;
    a first passivation layer disposed on the second nitride-based semiconductor layer and covering the gate structures;
    one or more source/drain (S/D) electrodes formed by patterning a S/D electrode layer disposed on the first passivation layer and penetrating through the first passivation layer to be in contact with the second nitride-based semiconductor layer; .
  15. The nitride-based electronic device according to claim 14, wherein the nitride-based IC chip further comprises:
    a second passivation layer disposed on the first passivation layer and covering the S/D electrodes;
    one or more first conductive vias disposed within the second passivation layer;
    a first conductive layer disposed on the second passivation layer and patterned to form one or more first conductive lines;
  16. The nitride-based electronic device according to claim 15, wherein the nitride-based IC chip further comprises:
    a third passivation layer disposed on the first conductive layer and covering the one or more first conductive lines;
    one or more second conductive vias disposed within the third passivation layer;
    a second conductive layer disposed on the third passivation layer and patterned to form one or more second conductive lines; and
  17. The nitride-based electronic device according to claim 16, further comprising a protection layer disposed above the second conductive layer and having one or more openings to expose one or more conductive pads.
  18. A method for manufacturing a nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability, the nitride-based electronic device comprising a control terminal, a first conduction terminal, a second conduction terminal and a voltage-sensing terminal, the method comprising:
    forming a power switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the power switching element being electrically connected to the control terminal, the first conduction electrode of the power switching element being electrically connected to the first conduction terminal and the second conduction electrode of the power switching element being electrically connected to the second conduction terminal; and
    forming a sense switching element having a control electrode, a first conduction electrode and a second conduction electrode; the control electrode of the sense switching element being electrically connected to the control terminal, and the first conduction electrode of the sense switching element being electrically connected to the first conduction terminal; and
    wherein when the power switching element is turned on by a control signal received through the control terminal, a voltage-sensing signal indicative of an on-state voltage across the first and second conduction terminals of the power switching element is generated at the voltage-sensing terminal.
  19. The method according to claim 18, further comprising forming a first clamping element having a positive electrode electrically connected to the voltage-sensing terminal and a negative electrode electrically connected to the second conduction terminal.
  20. The method according to claim 19 further comprising forming a second clamping element having a positive electrode electrically connected to the second conduction terminal and a negative electrode electrically connected to voltage-sensing terminal.
  21. The method according to any one of claims 18 to 20, wherein the sense switching element has an on-resistance greater than an on-resistance of the power switching element.
  22. The method according to any one of claims 18 to 21, wherein the power switching element is formed by forming a first nitride-based transistor having a gate acting as the control electrode of  the power switching element, a drain acting as the first conduction electrode of the power switching element and a source acting as the second conduction electrode of the power switching element.
  23. The method according to any one of claims 18 to 22, wherein the sense switching element is formed by forming a second nitride-based transistor having a gate acting as the control electrode of the sense switching element, a drain acting as the first conduction electrode of the sense switching element and a source acting as the second conduction electrode of the sense switching element.
  24. The method according to any one of claims 18 to 23, wherein:
    the first clamping element is formed by forming a third nitride-based transistor having a gate and a source being electrically connected together to act as the positive electrode of the first clamping element and a drain configured to act as the negative electrode of the first clamping element; and
    the second clamping element is formed by forming a fourth nitride-based transistor having a gate and a source being electrically connected together to act as the positive electrode of the second clamping element and a drain configured to act as the negative electrode of the second clamping element.
  25. The method according to claim 10, further comprising integrating the power switching element, the sense switching element, the first clamping element and the second clamping element into an integrated circuit (IC) chip by:
    disposing a first nitride-based semiconductor layer over a substrate;
    disposing a second nitride-based semiconductor layer on the first nitride-based semiconductor layer, the second nitride-based semiconductor layer having a bandgap greater than a bandgap of the first nitride-based semiconductor layer;
    disposing a gate semiconductor layer on the second nitride-based semiconductor layer and a gate metal layer on the gate semiconductor layer and patterning the gate semiconductor layer and the gate metal layer to form one or more gate structures;
    disposing a first passivation layer on the second nitride-based semiconductor layer to cover the gate structures and patterning the first passivation layer to form one or more source/drain (S/D) regions;
    disposing a S/D electrode layer to cover the first passivation layer and the one or more S/D regions and patterning the S/D electrode layer to form one or more S/D electrodes penetrating  through the first passivation layer to be in contact with the second nitride-based semiconductor layer;
    disposing a second passivation layer on the first passivation layer to cover the S/D electrodes;
    disposing a first conductive layer on the second passivation layer and patterning the first conductive layer to form one or more first conductive lines;
    disposing a third passivation layer on the first conductive layer to cover the one or more first conductive lines;
    disposing a second conductive layer on the third passivation layer and patterning the second conductive layer to form one or more second conductive lines;
    disposing a protection layer above the second conductive layer and patterning the protection layer to form one or more openings to expose one or more conductive pads to act as the first control terminal, the second control terminal, the first conduction terminal and second conduction terminal respectively.
PCT/CN2022/114810 2022-08-25 2022-08-25 Nitride-based electronic device with wafer-level dynamic on-resistance monitoring capability WO2024040516A1 (en)

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