JP2013041969A - Semiconductor device, method for manufacturing the same, and testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a gate leakage current is reduced and current collapse is suppressed.SOLUTION: In a first embodiment, the semiconductor device is provided comprising: a semiconductor layer 110 formed of a nitride-based semiconductor; a first insulating film 120 which is provided to have an opening on the semiconductor layer and contains a tantalum oxynitride; a second insulating film 130 laminated on the semiconductor layer in the opening of the first insulating film; and a gate electrode 140 provided on the second insulating film. The second insulating film is constituted of an insulating film having higher insulating properties than the first insulating film.

Description

  The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a test apparatus.

Conventionally, in a heterojunction semiconductor device using a GaN (gallium nitride) -based semiconductor (particularly, a high electron mobility transistor: HEMT: High Electron Mobility Transistor), a gate leakage current has been a problem. Therefore, it is known that Ta (tantalum) oxide or the like is interposed between the gate electrode and the semiconductor layer to reduce the gate leakage current of the HEMT having a metal-insulator-semiconductor (MIS) structure (for example, patents). Reference 1).
Japanese Patent Application Laid-Open No. 2006-245317

  However, the MIS HEMT having such a MIS structure has a problem called “current collapse” in which the current decreases due to the influence of the trap on the semiconductor surface while the gate leakage current can be suppressed. For example, if Vds (drain-source voltage) is given in several tens of volts in advance and negative stress voltage is also given in advance to Vgs (gate-source voltage), Id is reduced in the Id (drain current) -Vds characteristic. Resulting in. In particular, when the time after applying the stress voltage is as short as several μs, Id is significantly reduced. That is, it has been difficult to realize a device in which the influence of current collapse is reduced while suppressing gate leakage current.

  In the first aspect of the present invention, a semiconductor layer formed of a nitride-based semiconductor, a first insulating film provided with an opening on the semiconductor layer and containing tantalum oxynitride, and a first insulating film A semiconductor device comprising: a second insulating film stacked on the semiconductor layer in the opening; and a gate electrode provided on the second insulating film.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 shows a configuration example of a longitudinal section of a semiconductor device 100 according to the present embodiment. 2 shows a manufacturing flow of the semiconductor device 100 according to the present embodiment. A configuration example at the stage where the semiconductor layer 110 of the semiconductor device 100 according to the present embodiment is formed is shown. A configuration example at the stage where the source electrode 160 and the drain electrode 170 are formed on the semiconductor layer 110 according to the present embodiment is shown. A configuration example at the stage where the first insulating film 120 is formed on the semiconductor layer 110 according to the present embodiment is shown. A configuration example at a stage where an opening is formed in the first insulating film 120 according to the present embodiment is shown. A configuration example at the stage where the second insulating film 130 is formed on the first insulating film 120 and the opening according to the present embodiment is shown. A configuration example at the stage where the gate electrode 140 is formed on the second insulating film 130 according to the present embodiment is shown. A configuration example at the stage where the protective film 150 is formed on the gate electrode 140 according to the present embodiment is shown. An example of the Ig-Vds characteristic of the conventional semiconductor device is shown. An example of the pulse characteristic of the conventional semiconductor device is shown. An example of Ig-Vds characteristic of the semiconductor device 100 concerning this embodiment is shown. An example of pulse characteristics of the semiconductor device 100 according to the present embodiment is shown. The modification of the semiconductor device 100 which concerns on this embodiment is shown. A configuration example of a test apparatus 410 according to this embodiment is shown together with a device under test 400.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration example of a longitudinal section of a semiconductor device 100 according to the present embodiment. The semiconductor device 100 has a small gate leakage current and reduces the influence of current collapse. The semiconductor device 100 may be a FET. The semiconductor device 100 may be a HEMT. The semiconductor device 100 includes a substrate 10, a semiconductor layer 110, a first insulating film 120, a second insulating film 130, a gate electrode 140, a protective film 150, a source electrode 160, and a drain electrode 170.

  The substrate 10 forms a semiconductor layer 110 on the surface. The substrate 10 may be a crystal having a lattice constant substantially the same as the lattice constant of the semiconductor layer 110 so as to be formed while maintaining the crystallinity of the semiconductor layer 110. The substrate 10 may be a single crystal such as sapphire, SiC (silicon carbide), GaN, GaAs, or Si.

  The semiconductor layer 110 is formed of a nitride semiconductor. The semiconductor layer 110 may have a heterojunction in which two or more kinds of semiconductors having different band gaps are joined with crystallinity. In this embodiment, the semiconductor layer 110 is a GaN-based semiconductor layer. The semiconductor layer 110 includes an electron transit layer 112, a spacer layer 114, an electron supply layer 116, and a protective layer 118.

  The electron transit layer 112 is formed on the surface of the substrate 10. In the electron transit layer 112, a layer called binary electron gas capable of flowing electrons at high speed is formed. The electron transit layer 112 may be an undoped i-type GaN layer to which no impurities are artificially added.

  The spacer layer 114 is formed on the electron transit layer 112. The spacer layer 114 is formed of a different kind of semiconductor material having a band gap different from that of the electron transit layer 112. Since the electron transit layer 112 and the spacer layer 114 form a heterojunction, the electron transit layer 112 can form a binary electron gas in a region of about 10 nm near the interface with the spacer layer 114. The spacer layer 114 may be an undoped i-type AlGaN layer.

  The electron supply layer 116 is formed on the spacer layer 114. The electron supply layer 116 supplies electrons to the electron transit layer 112 through the spacer layer 114. The electron supply layer 116 may be an n-type AlGaN layer doped with impurities.

  The protective layer 118 is formed on the electron supply layer 116. For example, the protective layer 118 prevents and protects the oxidation of Al or the like in the electron supply layer 116. The protective layer 118 may be an n-type GaN layer doped with impurities. Note that the protective layer 118 may be omitted when the influence of oxidation of Al or the like in the electron supply layer 116 is small.

The first insulating film 120 is provided with an opening on the semiconductor layer 110 and includes Ta (tantalum) oxynitride (TaON). The first insulating film 120 has an opening on the semiconductor layer 110 below the gate electrode 140 and covers the surface of the semiconductor layer 110 other than the opening. The first insulating film 120 may be an insulating film having a higher dielectric constant than SiO ₂ (silicon dioxide). Insulating film of Ta oxynitride as a first insulation layer 120, Ta oxide and less trap levels as compared to SiO ₂ or the like, at the interface between the semiconductor layer 110, as compared with the Ta oxide and SiO _2, etc. It has a feature that a good interface with few defects is formed.

  The second insulating film 130 is stacked on the semiconductor layer 110 in the opening of the first insulating film 120. The second insulating film 130 is provided from the opening of the first insulating film 120 to the upper part of the first insulating film 120 in the vicinity of the opening. That is, the second insulating film 130 is in contact with the protective layer 118 in the opening of the first insulating film 120. The second insulating film 130 is stacked on the first insulating film 120 in portions other than the openings. Therefore, the second insulating film 130 in a portion other than the opening is a layer farther from the protective layer 118 than in the opening of the first insulating film 120. Accordingly, the upper surface of the second insulating film 130 has a depression at a portion corresponding to the opening.

  The second insulating film 130 may be more insulative than the first insulating film 120. The second insulating film 130 may be formed of a high dielectric constant material that reduces leakage current caused by a tunnel effect or the like.

  The second insulating film 130 includes an insulating film having a dielectric constant higher than that of SiN. The second insulating film 130 is at least one of Ta, Al (aluminum), Hf (hafnium), HfAl (hafnium aluminum), La (lanthanum), Y (yttrium), LaSi (lanthanum silicon), and HfLa (hafnium lanthanum). Including one. For example, the second insulating film 130 is made of Ta oxide, Hf (hafnium) oxide, HfAl (hafnium aluminum) oxide, La (lanthanum) oxide, HfLa (hafnium lanthanum), Y (yttrium) oxide, or the like. Insulating material is included.

  As an example, the second insulating film 130 includes Ta oxide (TaOx) as an insulating material. The second insulating film 130 may be formed by stacking a plurality of insulating films, and at least one of the plurality of insulating films may include Ta oxide as an insulating material.

  The gate electrode 140 is provided on the second insulating film 130. The gate electrode 140 is formed as an electrode having an insulated gate structure that applies a gate voltage to the semiconductor layer 110 through the second insulating film 130. The gate electrode may include Ni (nickel), Pt (platinum), Au (gold), Mo (molybdenum), Ti (titanium), or the like. The gate electrode 140 may have a wiring connection portion. The wiring connection portion may be electrically connected to an external circuit that supplies a gate voltage by gold plating or wire bonding.

  The gate electrode 140 is integrated with the first surface of the second insulating film 130 stacked in the opening of the first insulating film 120 and the second surface of the second insulating film 130 stacked on the first insulating film 120. It is provided. The gate electrode 140 is stacked closer to the protective layer 118 in the recess portion formed on the upper surface of the second insulating film 130, and the protective layer 118 is compared to the inside of the recess at the edge located around the recess. Laminated further away from. That is, the gate electrode 140 has a two-stage structure formed on two different surfaces of the second insulating film 130.

  The protective film 150 is an insulating film provided on the gate electrode 140 and the second insulating film 130. The protective film 150 may include a different type of insulating material from the second insulating film 130. As an example, the protective film 150 includes SiN (silicon nitride) as an insulating material. As a result, the semiconductor device 100 can reinforce the protective film on the surface and reduce trap levels and the like near the surface of the second insulating film 130.

  The source electrode 160 and the drain electrode 170 are provided on the semiconductor layer 110. The source electrode 160 and the drain electrode 170 are preferably formed so as to be in contact with the electron supply layer 116. The source electrode 160 and the drain electrode 170 are in ohmic contact with the semiconductor layer 110. The source electrode 160 and the drain electrode 170 may include Ni (nickel), Pt (platinum), Au (gold), Mo (molybdenum), Al (aluminum), Ti (titanium), or the like.

  Each of the source electrode 160 and the drain electrode 170 may have a wiring connection portion. Each wiring connection portion may be electrically connected to an external circuit to be connected to the source electrode 160 or the drain electrode 170 by gold plating or wire bonding.

  Here, the first insulating film 120 and the second insulating film 130 may be provided between the source electrode 160 and the drain electrode 170. The first insulating film 120 and the second insulating film 130 may be provided so as to further cover at least a part of the source electrode 160 and the drain electrode 170. In this case, the first insulating film 120 may be provided so as to cover the surface of the source electrode 160 and the drain electrode 170 other than the wiring connection portion.

  FIG. 2 shows a manufacturing flow of the semiconductor device 100 according to the present embodiment. 3 to 9 show configuration examples of the semiconductor device 100 formed at each stage of the manufacturing flow.

  First, the semiconductor layer 110 is formed on the substrate 10 (S200). The semiconductor layer 110 may be formed by a MOVPE method (Metal Organic Vapor Phase Epitaxy), an MBE method (Molecular Beam Epitaxy), or the like. FIG. 3 shows a configuration example at the stage where the semiconductor layer 110 of the semiconductor device 100 according to the present embodiment is formed.

  Next, the source electrode 160 and the drain electrode 170 are formed (S210). The source electrode 160 and the drain electrode 170 may be formed in a region where the electron supply layer 116 is exposed by removing the protective layer 118 by etching. Here, the region where the electrode is formed may be removed from the protective layer 118 by dry etching using a reactive gas, ions, radicals, or the like. Alternatively, the region where the electrode is formed may be removed by wet etching using a liquid chemical.

  For example, the source electrode 160 and the drain electrode 170 are formed by a vapor deposition method in which a material is heated and vaporized or sublimated to adhere to the surface of the substrate. Instead, the source electrode 160 and the drain electrode 170 may be formed by sputtering. In addition, as an example, the source electrode 160 and the drain electrode 170 are formed by forming a reverse pattern of a pattern to be formed on a substrate with a photoresist or the like, depositing a thin film to be formed, and then removing unnecessary portions other than the pattern together with the photoresist. It is formed by the evaporation lift-off method to be removed.

  The source electrode 160 and the drain electrode 170 formed on the electron supply layer 116 are annealed at a temperature of about 500 ° C. or higher to form an ohmic junction. FIG. 4 shows a configuration example at the stage where the source electrode 160 and the drain electrode 170 are formed on the semiconductor layer 110 according to the present embodiment.

Next, the first insulating film 120 is formed on the semiconductor layer 110 (S220). The first insulating film 120 may be formed by sputtering. For example, the first insulating film 120 is formed by RF sputtering in which a high-frequency voltage is applied to an insulating target to perform sputtering. Here, a Ta ₂ O ₅ (tantalum pentoxide) target is sputtered using a mixed gas of Ar (argon) and N ₂ (nitrogen) as an atmospheric gas, thereby forming Ta oxynitride as the first insulating film 120. May be membrane.

  Instead, the first insulating film 120 may be formed by a CVD (Chemical Vapor Deposition) method, an ALD (Atomic Layer Deposition) method, a sputtering method, or the like. The first insulating film 120 may have a thickness of about 10 to 100 nm. More preferably, it may have a film thickness of 20 to 50 nm. FIG. 5 shows a configuration example when the first insulating film 120 is formed on the semiconductor layer 110 according to the present embodiment.

  Next, an opening is formed in the first insulating film 120 (S230). The opening may be formed by removing the first insulating film 120 by etching and exposing a part of the surface of the semiconductor layer 110. FIG. 6 shows a configuration example at a stage where an opening is formed in the first insulating film 120 according to the present embodiment.

Next, the second insulating film 130 is formed on the first insulating film 120 and the opening (S240). Similar to the first insulating film 120, the second insulating film 130 may be formed by RF sputtering. Here, as the second insulating film 130, Ta oxide (TaOx) is formed by sputtering a Ta ₂ O ₅ target using a mixed gas of Ar (argon) and O ₂ (oxygen) as an atmospheric gas. Good. Thus, the first insulating film 120 and the second insulating film 130 can be formed by controlling the atmospheric gas without changing the target of the insulating material.

  Instead, the second insulating film 130 may be formed by a CVD method, an ALD method, or the like. The second insulating film 130 may have a thickness of about 10 to 100 nm. More preferably, it may have a film thickness of 20 to 50 nm.

  The second insulating film 130 is formed in contact with the exposed surface of the semiconductor layer 110 in the opening and covers the first insulating film 120. Since the second insulating film 130 is formed on the first insulating film 120 and the opening with substantially the same thickness, a step having substantially the same shape as the opening is also formed on the surface of the second insulating film 130. FIG. 7 shows a configuration example at a stage where the first insulating film 120 according to the present embodiment and the second insulating film 130 are formed on the opening.

  Next, the gate electrode 140 is formed on the second insulating film 130 (S250). For example, the gate electrode 140 is formed by an evaporation method. For example, the gate electrode 140 is formed by a vapor deposition lift-off method. The gate electrode 140 may be formed by evaporating a plurality of electrode materials. Alternatively, the gate electrode 140 may be formed by a sputtering method.

  Since the gate electrode 140 is formed to cover the step formed on the surface of the second insulating film 130, the gate electrode 140 is formed to have a two-step structure corresponding to the opening. FIG. 8 shows a configuration example at the stage where the gate electrode 140 is formed on the second insulating film 130 according to the present embodiment.

  Next, the protective film 150 is formed on the gate electrode 140 (S260). The protective film 150 may include a different type of insulating material from the first insulating film 120 and the second insulating film 130. The protective film 150 may be formed by a CVD method, an ALD method, a sputtering method, or the like. As an example, the protective film 150 is formed of SiN. In this case, the protective film 150 may be formed with a film thickness of about 50 to 300 nm. FIG. 9 shows a configuration example at a stage where the protective film 150 is formed on the gate electrode 140 according to the present embodiment.

  The semiconductor device 100 which is GaN HEMT is manufactured by the above Example. The semiconductor device 100 is a HEMT having a GaN MIS structure having high breakdown voltage, high output, and high frequency characteristics.

  FIG. 10 shows an example of Ig (gate current) -Vds characteristics of a conventional semiconductor device. FIG. 11 shows an example of pulse characteristics of a conventional semiconductor device. Here, the conventional semiconductor device is a semiconductor device using a GaN MIS structure HEMT in which the first insulating film 120 having an opening is not formed. In the case of this semiconductor device, the second insulating film 130 is formed on the semiconductor layer 110, and the gate electrode 140 and the protective film 150 are formed on the second insulating film 130 in this order. In this example, Ta oxide is used as the second insulating film 130.

  Note that the pulse characteristics are determined in advance by applying predetermined Vds and Vgs different from the initial state in a pulsed manner from a state in which predetermined Vds and Vgs are applied to the semiconductor device (starting state). Is to measure Id after a lapse of time, and obtain Id according to applied Vds and Vgs. When voltage stress is applied in the initial state, response characteristics after stress application can be evaluated from the pulse characteristics. In addition, the measurement result in a present Example has measured Id about 5 microseconds after applying Vds and Vgs like a pulse.

In FIG. 10, the horizontal axis represents the gate-source voltage Vgs of the semiconductor device, and the vertical axis represents the gate current Ig. This gate current Ig corresponds to the gate leakage current. From the figure, it can be seen that the reverse gate leakage current when negative Vgs is applied is reduced to 10 ⁻¹⁰ A / mm or less.

  The horizontal axis in FIG. 11 represents the drain-source voltage Vds of the semiconductor device, and the vertical axis represents the current Id flowing between the drain and source. The current-voltage characteristics plotted by the black circles are Vds = 0V and Vgs = 0V as the initial state, that is, pulse characteristics in the initial state without voltage stress, and when Vgs = 2, −2, −4, and −6V, respectively. Id-Vds relationship is shown.

  In this case, since no voltage is applied to Vds and Vgs as a starting state in the semiconductor device, even if a trap level is formed in the vicinity of the gate electrode, it is considered that carriers are hardly trapped newly. It is done. Accordingly, the current-voltage characteristics are observed to have substantially the same shape as the static characteristics when a voltage is statically applied to Vds and Vgs.

  The current-voltage characteristics plotted with white squares are the pulse characteristics when Vds = 25 V and Vgs = −10 V are applied as the initial state, and Id− in the case of Vgs = 2, 0, −2 and −4V. The relationship of Vds is shown. That is, a white square current-voltage characteristic indicates a pulse characteristic acquired in the presence of voltage stress, while a current-voltage characteristic plotted with a black circle indicates a pulse characteristic acquired in the absence of voltage stress. Thus, it is observed that the current-voltage characteristics change significantly depending on the presence or absence of voltage stress in the initial state.

  This is because when a voltage stress is applied to Vds and Vgs as a starting state, a depletion layer region extends according to Vds and Vgs, and electrons that are carriers are trapped in trap levels existing in the vicinity of the gate electrode 140, It is believed that Id has decreased as a result of the formation of a virtual gate. Thus, it is considered that current collapse is caused by the influence of traps existing in the vicinity of the gate electrode 140 and the like.

  Here, in the vicinity of the gate electrode 140, two main regions for forming such trap levels are considered between the gate electrode 140 and the second insulating film 130 and between the second insulating film 130 and the semiconductor layer 110. It is done. Between the gate electrode 140 and the second insulating film 130, the second insulating film 130 and the protective film 150 exist particularly at the gate end where the electric field concentrates when a gate voltage is applied to the gate electrode 140. It is considered that a trap level is formed at the heterogeneous interface between the second insulating film 130 and the protective film 150 to generate current collapse.

As described above, even if a highly insulating material is formed as the second insulating film 130, if the second insulating film 130 does not form a good interface with few defects on the semiconductor layer 110, a trap that generates current collapse is generated. A level is formed, and the influence of current collapse becomes a problem. That is, the conventional semiconductor device includes an insulating film having a high insulating property that reduces the gate leakage current between the gate electrode 140 and the semiconductor layer 110, and between the gate electrode 140 and the second insulating film 130, and the second insulating film 130. -It has been difficult to reduce the influence of current collapse by reducing trap levels formed in two regions between the semiconductor layers 110. For example, as shown in the example in the figure, a MIS structure GaN-based HEMT having a pulse characteristic with a small influence of current collapse while realizing high insulation with a gate leakage current of 10 ⁻⁹ A / mm or less is realized. It was difficult to do.

FIG. 12 shows an example of Ig-Vds characteristics of the semiconductor device 100 according to the present embodiment. Here, the second insulating film 130 is Ta oxide. In FIG. 12, the horizontal axis indicates the gate-source voltage Vgs of the semiconductor device, and the vertical axis indicates the gate current Ig. As in FIG. 10, it can be seen that the reverse gate leakage current is reduced to 10 ⁻¹⁰ A / mm or less.

  FIG. 13 shows an example of pulse characteristics of the semiconductor device 100 according to the present embodiment. The horizontal axis in FIG. 13 indicates Vds as in FIG. 11, and the vertical axis indicates Id. The current-voltage characteristics plotted with black circles are the pulse characteristics in the initial state with no voltage stress, and show the relationship of Id-Vds when Vgs = 2, 0, -2, and -4V. The current-voltage characteristics plotted with open squares are the pulse characteristics in the initial state with voltage stress, and show the relationship of Id-Vds when Vgs = 2, 0, -2, and -4V.

  It can be seen that the semiconductor device 100 according to the present example shows substantially the same current-voltage characteristic tendency regardless of the presence or absence of voltage stress. That is, it is considered that the semiconductor device 100 suppresses the current collapse by preventing the formation of the interface state that changes the current-voltage characteristics, and it has been difficult to reduce the gate leakage current and the current collapse. It can be seen that the reduction of the effect is compatible.

  In the semiconductor device 100, the second insulating film 130 is formed in a region immediately below the gate electrode 140 on the surface of the semiconductor layer 110, and the first insulating film 120 is formed in other regions. This insulating film containing Ta oxynitride, which is the first insulating film 120, has fewer trap levels than Ta oxide, and a good interface with few defects at the interface between the first insulating film 120 and the semiconductor layer 110. Form.

  Therefore, the first insulating film 120 covers the surface of the semiconductor layer 110 other than the region where the gate electrode 140 is formed, and the formation of trap levels at the heterogeneous interface between the semiconductor layer 110 and the insulating film can be reduced. . In addition, since the second insulating film 130 having a higher insulating property than the first insulating film 120 is formed in the region immediately below the gate electrode 140, leakage current from the gate electrode 140 to the semiconductor layer 110 can be reduced. That is, the semiconductor device 100 can reduce the leakage current while reducing the formation of trap levels on the surface of the semiconductor layer 110 between the insulating film and the semiconductor layer 110.

  In addition, since the gate electrode 140 is formed on the second insulating film 130 to have a two-step structure corresponding to the opening, the gate electrode 140 faces the semiconductor layer 110 and faces the semiconductor layer 110, the gate end, and the semiconductor layer 110. The second insulating film 130 covers the oppositely spaced surfaces. That is, since the gate end portion is formed so that only the second insulating film 130 wraps around the gate end portion, there is no heterogeneous interface with the protective film 150 and the like. Therefore, the trap level caused by the heterogeneous interface is not formed at the gate end, and the influence of current collapse can be prevented.

  As described above, the semiconductor device 100 reduces the formation of trap levels in the two regions between the gate electrode 140 and the second insulating film 130 in the vicinity of the gate electrode 140 and between the insulating film and the semiconductor layer 110, thereby reducing the current collapse. Can be prevented. Further, since the gate electrode 140 has a two-stage structure, it is possible to obtain a field plate effect that alleviates the concentration of the electric field at the gate end. Therefore, the semiconductor device 100 of the present embodiment can reduce the influence of current collapse while suppressing the gate leakage current.

  FIG. 14 shows a modification of the semiconductor device 100 according to the present embodiment. In the semiconductor device 100 of the present modification, the same reference numerals are given to substantially the same operations as those of the semiconductor device 100 according to the present embodiment shown in FIG. The semiconductor device 100 of this modification further includes a gate boundary film 180.

  The gate boundary film 180 is provided on the second insulating film 130 and is in contact with the gate electrode 140 at least at a part of the end of the gate electrode 140 on the second insulating film 130. Here, the gate boundary film 180 may cover a region from at least a part of the region where the gate electrode 140 is not provided on the second insulating film 130 to at least a part of the gate electrode 140. The gate boundary film 180 may be provided so as to cover the surface of the gate electrode 140 other than the wiring connection portion.

  The gate boundary film 180 may include an insulating material such as Ta oxide, Hf oxide, HfAl oxide, La oxide, or Y oxide. As an example, the gate boundary film 180 includes Ta oxide.

  Here, the gate boundary film 180 and the second insulating film 130 in contact with the gate boundary film 180 may include the same type of insulating material. For example, the gate boundary film 180 and the second insulating film 130 are formed of substantially the same insulating material. Instead, the gate boundary film 180 and the second insulating film 130 may have substantially the same main elements or main components. Instead, the gate boundary film 180 and the second insulating film 130 may have substantially the same type or composition of elements contained in the main component of the insulating material.

  Accordingly, since the semiconductor device 100 does not form a different material between the gate boundary film 180 and the second insulating film 130, it is possible to prevent the formation of a different interface. Therefore, since the gate electrode 140 does not contact the heterogeneous interface at the electrode end portion, it is possible to prevent electrons from being trapped in a trap level or the like formed at the heterogeneous interface. As described above, since the heterogeneous interface is not formed at the electrode end portion of the gate electrode 140, the gate electrode 140 may not have a two-stage structure.

  In the semiconductor device 100 of this embodiment described above, the second insulating film 130 has been described as an example in which a single-layer insulating film is formed. Instead, the second insulating film 130 may be a multilayer film in which a plurality of layers formed of different materials are stacked. In this case, at least one of the plurality of insulating films includes an insulating material having a higher insulating property than the first insulating film 120.

  For example, the semiconductor device 100 is provided on and in contact with the semiconductor layer 110, and is provided on the first layer of the Ta oxynitride film that forms a good interface with the semiconductor layer 110 with few defects, and on the first layer. A second insulating film 130 having a second layer of Ta oxide film that has higher insulating properties than nitride films and reduces leakage current may be provided. In addition, the semiconductor device 100 may include a second insulating film 130 that is provided in contact with the gate electrode 140 and has a third layer of Ta oxynitride film that forms a good interface with the gate electrode 140 with few defects.

  The second insulating film 130 formed of such a multilayer film has a gate leakage while suppressing the formation of defects at the interface with the semiconductor layer 110 and / or the gate electrode 140 even in the region directly under the gate. The current can be reduced. Since the semiconductor device 100 according to this embodiment is a MIS HEMT formed of GaN, it can have high breakdown voltage, high output, and high frequency characteristics.

  FIG. 15 shows a configuration example of the test apparatus 410 according to this embodiment together with the device under test 400. The test apparatus 410 tests at least one device under test 400 such as an analog circuit, a digital circuit, an analog / digital mixed circuit, a memory, and a system on chip (SOC). The test apparatus 410 inputs a test signal based on a test pattern for testing the device under test 400 to the device under test 400, and the device under test based on an output signal output from the device under test 400 according to the test signal. The quality of 400 is judged.

  The test apparatus 410 includes a test unit 420, a signal input / output unit 430, and a control device 440. The test unit 420 tests the device under test 400 by exchanging electrical signals with the device under test 400. The test unit 420 includes a test signal generation unit 423 and an expected value comparison unit 426.

  The test signal generator 423 is connected to one or a plurality of devices under test 400 via the signal input / output unit 430 and generates a plurality of test signals to be supplied to the device under test 400. The test signal generator 423 may generate an expected value of the response signal output from the device under test 400 according to the test signal.

  The expected value comparison unit 426 compares the data value included in the response signal of the device under test 400 received from the signal input / output unit 430 with the expected value generated by the test signal generation unit 423. The expected value comparison unit 426 determines pass / fail of the device under test 400 based on the comparison result.

  The signal input / output unit 430 electrically connects the device under test 400 to be tested and the test unit 420, and transmits the test signal generated by the test signal generation unit 423 to the device under test 400. The signal input / output unit 430 receives a response signal output from the device under test 400 in accordance with the test signal. The signal input / output unit 430 transmits the received response signal of the device under test 400 to the expected value comparison unit 426. The signal input / output unit 430 may be a performance board on which a plurality of devices under test 400 are mounted. The signal input / output unit 430 includes the semiconductor device 100.

  The semiconductor device 100 is provided between the test unit 420 and the device under test 400 and electrically connects or disconnects between the test unit 420 and the device under test 400. The test apparatus 410 may perform electrical connection or disconnection by the semiconductor device 100 according to the present embodiment.

  In this example, the example in which the signal input / output unit 430 is connected to one device under test 400 and one semiconductor device 100 is provided for each of the input signal line and the output signal line of one device under test 400 has been described. Instead, the signal input / output unit 430 may be connected to a plurality of devices under test 400, and one semiconductor device 100 may be provided for each of the input signal lines and the output signal lines of the plurality of devices under test 400. Further, when there is one signal input / output line connected from the signal input / output unit 430 to one device under test 400, one semiconductor device 100 may be provided in one input / output line.

  The control device 440 transmits a control signal to the test unit 420 and the signal input / output unit 430 in order to execute the test of the test device 410. The control device 440 transmits a control signal that causes the test unit 420 to generate a test signal or compare a test result with an expected value in accordance with a test program. Further, the control device 440 instructs connection of the semiconductor device 100 provided in the signal input / output line to be connected and disconnection of the semiconductor device 100 provided in the signal input / output line to be disconnected according to the test program. An instruction or the like is transmitted to the signal input / output unit 430.

  The above-described test apparatus 410 in the present embodiment has a high breakdown voltage, high output, and high frequency characteristics, and is a semiconductor device that improves high frequency characteristics when a pulse is applied to the gate electrode while reducing gate leakage current. 100 can be used to perform the test.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 substrate, 100 semiconductor device, 110 semiconductor layer, 112 electron transit layer, 114 spacer layer, 116 electron supply layer, 118 protective layer, 120 first insulating film, 130 second insulating film, 140 gate electrode, 150 protective film, 160 Source electrode, 170 Drain electrode, 180 Gate boundary film, 400 Device under test, 410 Test device, 420 Test unit, 423 Test signal generation unit, 426 Expected value comparison unit, 430 Signal input / output unit, 440 Control device

Claims (14)

A semiconductor layer formed of a nitride-based semiconductor;
A first insulating film provided on the semiconductor layer with an opening and containing tantalum oxynitride;
A second insulating film stacked on the semiconductor layer in the opening of the first insulating film;
A gate electrode provided on the second insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first insulating film has the opening on the semiconductor layer below the gate electrode. The second insulating film is provided over the first insulating film in the vicinity of the opening from within the opening of the first insulating film,
The gate electrode is integrally provided on a first surface of the second insulating film stacked in the opening and a second surface of the second insulating film stacked on the first insulating film. The semiconductor device according to claim 1.   4. The semiconductor device according to claim 1, wherein the second insulating film has a higher insulating property than the first insulating film. 5.   The semiconductor device according to claim 1, wherein the second insulating film includes an insulating film having a dielectric constant higher than that of SiN.   The semiconductor device according to claim 5, wherein the second insulating film includes at least one of tantalum, aluminum, hafnium, hafnium aluminum, lanthanum, yttrium, lanthanum silicon, and hafnium lanthanum.   The semiconductor device according to claim 6, wherein the second insulating film includes tantalum oxide as an insulating material.   8. The second insulating film according to claim 1, wherein the second insulating film is formed by stacking a plurality of insulating films, and at least one of the plurality of insulating films includes tantalum oxide as an insulating material. Semiconductor device.   The semiconductor device according to claim 1, further comprising an insulating protective film provided on the gate electrode and the second insulating film.   The semiconductor device according to claim 9, wherein the protective film includes silicon nitride as an insulating material. A source electrode and a drain electrode provided on the semiconductor layer;
The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are provided between the source electrode and the drain electrode.   The semiconductor device according to claim 1, wherein the semiconductor device is a HEMT having a MIS structure. A semiconductor layer forming step of forming a semiconductor layer with a nitride-based semiconductor;
A first insulating film forming step of forming a first insulating film provided with an opening on the semiconductor layer and including tantalum oxynitride;
A second insulating film forming step of forming a second insulating film on the semiconductor layer in the opening of the first insulating film;
Forming a gate electrode on the second insulating film; and
A method for manufacturing a semiconductor device comprising: A test apparatus for testing a device under test,
A test section for transmitting an electrical signal to and from the device under test to test the device under test;
13. The device according to claim 1, wherein the device is provided in a transmission path between the device under test and the test unit, and switches between the device under test and the test unit being electrically connected or disconnected. A semiconductor device according to the description;
A test apparatus comprising:

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