JP2010147349A - Semiconductor device, method of manufacturing the same, and switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a leakage current of a transistor. <P>SOLUTION: A semiconductor device includes: a plurality of electric elements disposed adjacent to each other along the front face of a semiconductor material; a lower-layer protection insulation film containing no silicon, which covers the plurality of electric elements; and an upper-layer protection insulation film containing silicon, which is disposed on the lower-layer protection insulation film. In the semiconductor device, at least one of the plurality of electric elements could contain a metal that is to be silicided and the lower-layer protection insulation film could serve to prevent a contact between the metal contained in the electric element and the silicon contained in the upper-layer protection insulation film. The lower-layer protection insulation film could have a high-dielectric-constant layer having a relative permittivity of ≥10. The upper-layer protection insulation film could contain silicon and nitride. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and a switch circuit.

  Japanese Patent Laid-Open No. 2002-324813 discloses a heterostructure field effect transistor. The heterostructure field effect transistor includes a buffer layer, a channel layer, a spacer layer, a carrier supply layer, an etching stopper layer, and a cap layer that are epitaxially grown on a semiconductor substrate. The source electrode and drain electrode formed on the surface are electrically connected to a two-dimensional electron gas formed in the channel layer. An insulating layer having a high dielectric material is deposited on the opening from which the cap layer has been removed, and a gate electrode is further formed.

Japanese Patent Laying-Open No. 2006-245317 discloses a semiconductor device and a manufacturing method thereof. The semiconductor device is a semiconductor device made of a group 3-5 nitride semiconductor, a semiconductor layer made of a group 3-5 nitride semiconductor, a gate insulating film formed on the surface of the semiconductor layer, and a gate insulating film And a formed gate electrode. It is disclosed that the gate insulating film is made of Ta (tantalum) oxide, Hf (hafnium) oxide, HfAl (hafnium aluminum) oxide, La (lanthanum) oxide, or Y (yttrium) oxide.
JP 2002-324813 A JP 2006-245317 A

  In the field effect transistor disclosed in Patent Document 1 or Patent Document 2, a high dielectric material is applied as the gate insulating layer. As a result, the gate leakage current of the field effect transistor can be suppressed to some extent. However, semiconductor devices suitable for high-speed response such as gallium nitride-based field effect transistors are expected to have high-functional switching characteristics, and further reduction of leakage current is desired. In this case, a certain low on-resistance is also required.

  In order to solve the above problems, in the first aspect of the present invention, a plurality of electrical element elements adjacent to each other along the surface of the semiconductor material, and a lower layer protective insulation not containing silicon covering the plurality of electrical element elements A semiconductor device is provided that includes a film and an upper protective insulating film that is disposed on the lower protective insulating film and includes silicon.

  In the semiconductor device, at least one of the plurality of electric element elements can contain a metal to be silicided, and the lower protective insulating film includes a metal contained in the electric element element and silicon contained in the upper protective insulating film. Can be blocked. The lower protective insulating film may have a high dielectric layer having a relative dielectric constant of 10 or more. The upper protective insulating film can contain silicon and nitrogen. The upper protective insulating film may be a silicon nitride film formed as a thin film at a temperature of 260 ° C. or lower, and is preferably a silicon nitride film formed as a thin film at a temperature of 100 ° C. or lower.

  In the semiconductor device, at least one of the plurality of electric element elements is an electrode or a terminal constituting an active element or a passive element formed on a surface of a semiconductor material, or a lead portion connected to the active element or the passive element. Good. The plurality of electric element elements may include a gate electrode, a source electrode, and a drain electrode of a MIS field effect transistor. The plurality of electrical element elements may further include a gate extension, a source extension, and a drain extension extending from the gate electrode, the source electrode, and the drain electrode.

  The semiconductor device may further include an inter-element insulating film having a high dielectric layer having a relative dielectric constant of 10 or more, disposed between the semiconductor material and at least one of the electric element elements. The inter-element insulating film is also disposed on the surface of the semiconductor material included between the plurality of electrical element elements, and can prevent impurities that become donors or acceptors from contacting the semiconductor material. At least one of the electric element elements may be a gate electrode of a MIS type field effect transistor, and the inter-element insulating film may be a gate insulating film of the MIS type field effect transistor.

  The leakage current when the gate width of the MIS field effect transistor is 1 mm may be 500 pA or less, and the on-resistance of the MIS field effect transistor may be 2 Ωmm or less.

  In the second aspect of the present invention, a step of forming a plurality of electric element elements so as to be adjacent to each other along the surface of the semiconductor material, and a lower protective insulating film not containing silicon covering the plurality of electric element elements And a step of forming an upper protective insulating film containing silicon on the lower protective insulating film. A method for manufacturing a semiconductor device is provided.

  According to a third aspect of the present invention, there is provided a switch circuit including a semiconductor device that operates as a switch element, the semiconductor device including a plurality of electrical element elements adjacent to each other along a surface of a semiconductor material, and a plurality of electrical elements. A switch circuit is provided that includes a lower protective insulating film that does not include silicon and covers an element element, and an upper protective insulating film that is disposed on the lower protective insulating film and includes silicon.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 schematically shows a cross-sectional example of a semiconductor device 10 according to the present embodiment. The semiconductor device 10 includes a semiconductor substrate 12, an electrical element element 14, a lower protective insulating film 16, and an upper protective insulating film 18.

  The semiconductor substrate 12 is an example of a semiconductor material. The semiconductor substrate 12 may be a group 3-5 semiconductor. Examples of the semiconductor substrate 12 include a GaN semiconductor, an AlGaN semiconductor, a GaAs semiconductor, an InGaAs semiconductor, and an AlGaAs semiconductor.

  The plurality of electrical element elements 14 are arranged adjacent to each other along the surface of the semiconductor substrate 12. At least one of the plurality of electrical element elements 14 may contain a metal to be silicided. Examples of the metal to be silicided include Na, Mg, K, Ca, V, Cr, Mn, Fe, Co, Ni, Cu, Rb, Zr, Ru, Pd, Cs, W, Pt, Au, and Ti.

  The electric element element 14 may be an electrode or a terminal constituting an active element or a passive element formed on the surface of the semiconductor substrate 12, or a lead portion connected to the active element or the passive element. Examples of the active element include a transistor and a diode. Examples of passive elements include capacitors, coils, and resistors. An example of the resistance material is nickel chromium. Examples of electrodes or terminals include a gate, a source, a drain, a base, an emitter, a collector, an anode, and a cathode. The lead portion includes a wiring and a contact pad.

  The lower protective insulating film 16 may be an insulating film that does not contain silicon and covers the plurality of electric element elements 14. As the insulating film not including silicon, a metal oxide film can be exemplified. The lower protective insulating film 16 can inhibit contact between the metal contained in the electrical element element 14 and the silicon contained in the upper protective insulating film 18. Silicon may act as a semiconductor donor impurity by entering the semiconductor substrate 12. In such a case, the lower protective insulating film 16 can inhibit the penetration of silicon into the semiconductor substrate 12 and maintain high electrical insulation between the electrical element elements 14.

  The lower protective insulating film 16 can prevent the electric element element 14 from being silicided by silicon contained in the upper protective insulating film 18. By preventing silicidation, it is possible to suppress adverse effects caused by silicidation, for example, generation of leakage current between the plurality of electric element elements 14.

  The lower protective insulating film 16 may have a high dielectric layer having a relative dielectric constant of 10 or more. Examples of high dielectrics include tantalum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, yttrium oxide, titanium oxide, barium strontium titanium oxide (BST), strontium titanium oxide (STO), zirconate titanate (PZT), strontium Examples thereof include bismuth tantalum oxide (SBT). By using the lower protective insulating film 16 as a high dielectric, the electric field generated between the plurality of electric element elements 14 can be reduced, and the leakage current between the plurality of electric element elements 14 can be suppressed. .

  The upper protective insulating film 18 is disposed on the lower protective insulating film 16. The upper protective insulating film 18 may contain silicon. The upper protective insulating film 18 may contain silicon and nitrogen, and may be, for example, silicon nitride or silicon nitride oxide. The upper protective insulating film 18 may be a silicon nitride film formed as a thin film at a temperature of 260 ° C. or lower, and is preferably a silicon nitride film formed as a thin film at a temperature of 100 ° C. or lower. Silicon nitride can protect the electric element element 14 from moisture, impurities, etc. in addition to the insulating effect due to its denseness.

  The semiconductor device 10 can be manufactured by the following process. That is, the plurality of electric element elements 14 are formed so as to be adjacent to each other along the surface of the semiconductor substrate 12 which is an example of the semiconductor material. Thereafter, a lower protective insulating film 16 that does not contain silicon and covers the plurality of electric element elements 14 is formed. Further, an upper protective insulating film 18 containing silicon is formed on the lower protective insulating film 16. According to the semiconductor device 10, the leakage current between the plurality of electric element elements 14 can be reduced.

  FIG. 2 shows an example of the upper surface of a semiconductor device 100 including a high electron mobility transistor and a capacitor, which is a specific example of the semiconductor device 10 of FIG. FIG. 3 shows an example of a cross section of the semiconductor device 100 shown in FIG. 3 is a cross-sectional example along the line AA in FIG. 2, and the b part in FIG. 3 is a cross-sectional example along the line BB in FIG. Part a and part b in FIG. 3 indicate high electron mobility transistors included in the semiconductor device 100. In FIG. 3b, the source wiring is not shown. Part c of FIG. 3 is a cross-sectional example of the capacitor. In FIG. 2, the illustration of the capacitor is omitted.

  In this embodiment, a high electron mobility transistor is exemplified as the active element, but a MOS field effect transistor or a bipolar transistor may be applied. Although a capacitor is illustrated as a passive element, a resistor and a coil may be applied.

  The semiconductor device 100 includes a source electrode 102, a drain electrode 104, a gate electrode 106, a gate extension 107, a source extraction wiring 108, a drain extraction wiring 110, a gate pad 112, a source wiring 114, and a drain wiring. 116, gate wiring 118, support substrate 122, buffer layer 124, channel layer 126, spacer layer 128, carrier supply layer 130, cap layer 132, insulating layer 134, and lower protective insulating film 136 , An upper protective insulating film 138, an element isolation region 140, a capacitor lower electrode 142, a capacitor insulating layer 144, and a capacitor upper electrode 146.

  The source electrode 102 and the drain electrode 104 may be an example of an electric element element. The source electrode 102 and the drain electrode 104 are disposed in contact with the carrier supply layer 130 and constitute input / output electrodes of the high electron mobility transistor. Examples of the material composing the source electrode 102 and the drain electrode 104 include Ni, Au, Ti, W, and Al transition metals. The material of the source electrode 102 and the drain electrode 104 may be a single element of the metal or an alloy of the metal. The source electrode 102 and the drain electrode 104 may have a stacked structure of a single element or an alloy of the metal.

  The gate electrode 106 may be an example of an electric element element. The gate electrode 106 is disposed in contact with the insulating layer 134. Examples of the material for forming the gate electrode 106 include Au, Ni, Pt, and W. The material of the gate electrode 106 may be the above metal alone or an alloy of the above metal. The gate electrode 106 may have a stacked structure of the above metals.

  The gate extension 107 may be an example of an electric element element. The gate extension 107 is an extension of the gate electrode and connects the gate electrode 106 to the gate pad 112 together with the gate wiring 118. The gate extension 107 is disposed on the element isolation region 140.

  The source lead wiring 108 may be an example of an electric element element. The source lead wiring 108 is connected to the source electrode 102 through the source wiring 114. The source lead wiring 108 is a terminal that connects the source electrode 102 to the outside of the semiconductor device 100. The source lead wiring 108 may have the same material as the source electrode 102.

  The drain lead wiring 110 may be an example of an electric element element. The drain lead wiring 110 is connected to the drain electrode 104 through the drain wiring 116. The drain lead wiring 110 is a terminal that connects the drain electrode 104 to the outside of the semiconductor device 100. The drain lead wiring 110 may have the same material as the drain electrode 104.

  The gate pad 112 may be an example of an electric element element. The gate pad 112 is connected to the gate electrode 106 through the gate wiring 118 and the gate extension 107. The gate pad 112 is a terminal that connects the gate electrode 106 to the outside of the semiconductor device 100. The gate pad 112 may have the same material as the gate electrode 106.

  The source wiring 114 may be an example of an electric element element. The source wiring 114 connects the plurality of source electrodes 102 to the source lead wiring 108. The source wiring 114 may have the same material as the source electrode 102.

  The drain wiring 116 may be an example of an electric element element. The drain wiring 116 connects the plurality of drain electrodes 104 to the drain lead wiring 110. The drain wiring 116 may have the same material as the drain electrode 104.

  The gate wiring 118 may be an example of an electric element element. The gate wiring 118 connects the plurality of gate electrodes 106 to the gate pad 112. The gate wiring 118 may have the same material as the gate electrode 106.

  The support substrate 122 may be an example of a semiconductor material and supports a thin film. Examples of the support substrate 122 include single crystal alumina, SiC, and Si wafer.

  The buffer layer 124 may be an example of a semiconductor material. The buffer layer 124 ensures the crystal quality of the channel layer 126 and prevents the deterioration of the characteristics of the semiconductor device 100 due to impurities remaining on the surface of the support substrate 122. The buffer layer 124 serves to suppress leakage current from the channel layer 126. The buffer layer 124 also functions as a buffer layer that matches the interstitial distance between the channel layer 126 formed in the upper layer and the support substrate 122. Examples of the material of the buffer layer 124 include GaN and AlGaN.

  The channel layer 126 may be an example of a semiconductor material. The channel layer 126 forms a two-dimensional electron gas at the interface with the spacer layer 128 to form a current channel between the source electrode and the drain electrode. An example of the material of the channel layer 126 is i-type GaN.

  The spacer layer 128 may be an example of a semiconductor material. The spacer layer 128 is formed between the channel layer 126 and the carrier supply layer 130 and acts to form a secondary electron gas at a position away from the carrier supply layer 130. An example of the material of the spacer layer 128 is i-type AlGaN.

  The carrier supply layer 130 may be an example of a semiconductor material. The carrier supply layer 130 supplies carriers to the channel layer 126. An example of the material of the carrier supply layer 130 is n-type AlGaN.

  The cap layer 132 may be an example of a semiconductor material. The cap layer 132 has a function of adjusting stress of a layer formed below the cap layer 132, particularly a function of stabilizing the carrier supply layer 130. An example of the material of the cap layer 132 is n-type GaN.

  The insulating layer 134 may be an example of an inter-element insulating film. In FIG. 3A, the insulating layer 134 is disposed between the cap layer 132, which is a semiconductor material, and the gate electrode 106, and constitutes a gate insulating film of the MIS field effect transistor. The insulating layer 134 may include a high dielectric layer having a relative dielectric constant of 10 or more. As the insulating layer 134, for example, tantalum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, yttrium oxide, titanium oxide, barium strontium titanium oxide (BST), strontium titanium oxide (STO), zirconate titanate (PZT), strontium Examples thereof include bismuth tantalum oxide (SBT). By adopting a high dielectric layer having a relative dielectric constant of 10 or more for the insulating layer 134, gate leakage current can be reduced.

  The insulating layer 134 is also disposed on the surface of the cap layer 132 between the source electrode 102 and the gate electrode 106 and between the gate electrode 106 and the drain electrode 104. The insulating layer 134 can prevent impurities that become donors or acceptors from contacting the cap layer 132 with respect to the cap layer 132 of a semiconductor material. As a result, it is possible to prevent the occurrence of a leak current due to impurity penetration.

  As shown in part b of FIG. 3, the insulating layer 134 is disposed between the gate extension 107 and the element isolation region 140. The insulating layer 134 is also disposed on the surface of the element isolation region 140 between the source electrode 102 and the gate extension portion 107 and between the gate extension portion 107 and the drain electrode 104. With the above arrangement, the insulating layer 134 can prevent impurities that serve as donors or acceptors for the semiconductor material from coming into contact with the element isolation region 140.

  Insulating layer 134 may also be disposed between the semiconductor material and other electrical element elements. Insulating layer 134 may also be disposed on the surface of the semiconductor material between the plurality of electrical element elements. With such an arrangement, the insulating layer 134 can prevent impurities that serve as donors or acceptors for the semiconductor material from coming into contact with the semiconductor material, and can prevent the occurrence of leakage current due to the intrusion of impurities.

  The lower protective insulating film 136 may be an example of the lower protective insulating film 16 in FIG. The lower protective insulating film 136 may include a high dielectric layer having a relative dielectric constant of 10 or more. Examples of high dielectrics include tantalum oxide, zirconium oxide, hafnium oxide, lanthanum oxide, yttrium oxide, titanium oxide, barium strontium titanium oxide (BST), strontium titanium oxide (STO), zirconate titanate (PZT), strontium Examples thereof include bismuth tantalum oxide (SBT).

  The lower protective insulating film 136 can inhibit the contact between the metal contained in the electric element such as the source electrode 102, the drain electrode 104, and the gate electrode 106 and the silicon contained in the upper protective insulating film 138. The lower protective insulating film 136 can prevent the electric element element from being silicided by silicon contained in the upper protective insulating film 138. By preventing silicidation, it is possible to suppress adverse effects caused by silicidation, for example, generation of leakage current between a plurality of electric element elements. The lower protective insulating film 136 can also prevent silicon contained in the upper protective insulating film 138 from entering the cap layer 132 and the like.

  FIG. 3B shows an example in which the insulating layer 134 is formed between the gate extension 107 and the element isolation region 140, but the insulating layer 134 may not be provided. Even in such a case, the lower protective insulating film 136 can prevent the upper protective insulating film 138 containing silicon from coming into direct contact with the surface of the element isolation region 140. The lower protective insulating film 136 can prevent an increase in leakage current due to silicon entering the element isolation region 140.

  The upper protective insulating film 138 may be an example of the upper protective insulating film 18 in FIG. The upper protective insulating film 138 is disposed on the lower protective insulating film 136. The upper protective insulating film 138 may contain silicon. The upper protective insulating film 138 may contain silicon and nitrogen, and may be, for example, silicon nitride or silicon nitride oxide. Silicon nitride can protect the electric element element from moisture, impurities, etc., in addition to the insulating effect, due to its denseness.

  The element isolation region 140 is a region formed by element isolation processing in a semiconductor material such as the support substrate 122, the buffer layer 124, the channel layer 126, the spacer layer 128, the carrier supply layer 130, and the cap layer 132. The element isolation region 140 can be formed by destroying the crystal structure by implanting ions into the semiconductor material.

  The capacitor lower electrode 142 may be an example of an electric element element. The capacitor lower electrode 142 may contain a metal to be silicided. Examples of the metal to be silicided include Ni, Au, Ti, and W.

  The capacitor insulating layer 144 insulates the capacitor lower electrode 142 and the capacitor upper electrode 146. Examples of the material of the capacitor insulating layer 144 include tantalum oxide, zirconium oxide, hafnium oxide, and the like.

  The capacitor upper electrode 146 may be an example of an electric element element. The capacitor upper electrode 146 may contain a metal to be silicided. Examples of the metal to be silicided include Ni, Au, Ti, and W.

  As shown in FIG. 1, the plurality of source electrodes 102, the plurality of drain electrodes 104, and the plurality of gate electrodes 106 may be disposed adjacent to each other. The plurality of source electrodes 102 are connected to the source lead wiring 108 by the source wiring 114. The plurality of drain electrodes 104 are connected to the drain lead wiring 110 by the drain wiring 116. The plurality of gate electrodes 106 are connected to the gate pad 112 by the gate extension 107 and the gate wiring 118.

  Part a of FIG. 3 shows the structure of a high electron mobility transistor as an active element. In the high electron mobility transistor, the leakage current when the gate width is 1 mm may be 500 pA or less, and the on-resistance may be 2 Ωmm or less. Here, the “leakage current” may include a gate leakage current between the gate and another electric element element or the semiconductor substrate and an off-leakage current between the source and the drain generated when the transistor is off.

  4 to 10 schematically show cross-sectional examples in the manufacturing process of the semiconductor device 100. FIG. Hereinafter, a method for manufacturing the semiconductor device 100 will be described with reference to the drawings.

  As shown in FIG. 4, a semiconductor material substrate including a support substrate 122, a buffer layer 124, a channel layer 126, a spacer layer 128, a carrier supply layer 130, and a cap layer 132 is prepared. The semiconductor material substrate only needs to have a semiconductor layer capable of forming an electric element element. For example, the semiconductor material substrate may be constituted by the support substrate 122, the channel layer 126, and the carrier supply layer 130.

  The semiconductor material substrate can be formed by epitaxially growing the buffer layer 124, the channel layer 126, the spacer layer 128, the carrier supply layer 130, and the cap layer 132 in this order on the support substrate 122. Examples of the epitaxial growth method include a metal organic chemical vapor deposition method (MOCVD method) and a molecular beam epitaxy method (MBE method).

  As shown in FIG. 5, the insulating layer 134 is formed on the cap layer 132. The insulating layer 134 can be formed by sputtering, chemical vapor deposition (CVD), MOCVD, or the like.

As shown in FIG. 6, the source electrode 102, the drain electrode 104, and the capacitor | condenser lower electrode 142 are formed. In forming the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142, first, a photoresist film having openings at the portions where the source electrode 102 and the drain electrode 104 are formed is formed on the surface of the insulating layer 134. By etching using the photoresist film as a mask, the insulating layer 134 and the cap layer 132 at the site where the source electrode 102 and the drain electrode 104 are formed are removed. Thereafter, a conductive film to be the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142 is deposited, and then the photoresist film is lifted off to form the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142. As a method for etching the insulating layer 134, dry etching using an F-based mixed gas can be exemplified. Examples of the method for etching the cap layer 132 include dry etching using chlorine gas or chlorine-based gas. After forming the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142, the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142 may be annealed for the purpose of sintering and the like. An example of the annealing process is a heat treatment at 750 ° C. for 3 minutes in an N ₂ atmosphere.

  6 is a cross-sectional example of the AA portion of FIG. 2, and schematically shows a cross section in a manufacturing process of a portion corresponding to the a portion of FIG. Part b of FIG. 6 is a cross-sectional example of the part BB of FIG. 2, and schematically shows a cross section in the manufacturing process of a part corresponding to part b of FIG. 3. Part c of FIG. 6 schematically shows a cross section in the manufacturing process of forming a capacitor corresponding to part c of FIG. The same applies to each of the parts a, b, and c in FIGS.

  As shown in FIG. 7, an element isolation region 140 is formed. The element isolation region 140 can be formed by, for example, photolithography using a photoresist film having an opening in a region where the element isolation region 140 is to be formed, and using the photoresist film as a mask, for example, by boron ion implantation. It can also be formed by argon ion implantation.

  In the description of FIG. 5, the example in which the insulating layer 134 is formed after the cap layer 132 is epitaxially grown is shown, but the insulating layer 134 may be formed after the element isolation region 140 is formed. In this case, the insulating layer 134 covers the source electrode 102 and the drain electrode 104, silicidation between the source electrode 102 and the drain electrode 104 can be suppressed, and leakage current can be reduced.

As shown in FIG. 8, a capacitor insulating layer 144 is formed by sputtering, for example, and as shown in FIG. 9, a gate electrode 106 and a gate extending portion 107 are formed on the surface of the insulating layer 134. At the same time, a capacitor upper electrode 146 is formed on the surface of the capacitor insulating layer 144. For example, the gate electrode 106, the gate extension 107, and the capacitor upper electrode 146 are formed by forming a photoresist film having an opening in a region where the gate electrode 106, the gate extension 107 and the capacitor upper electrode 146 are to be formed, and then depositing a conductive film. The photoresist film can be lifted off. After forming the gate electrode 106 and the like, an annealing treatment may be performed for the purpose of sintering and the like. As a method for the annealing treatment, for example, a treatment for 60 minutes at 360 ° C. in an N ₂ atmosphere can be exemplified.

  Note that ion implantation may be performed again in the element isolation region 140 for the purpose of improving the insulation of the element isolation region 140. Leakage current can be effectively suppressed by ion implantation again.

  As shown in FIG. 10, a lower protective insulating film 136 is formed to cover the source electrode 102, the drain electrode 104, the capacitor lower electrode 142, the gate electrode 106, the gate extension 107, and the capacitor upper electrode 146, which is an example of an electric element element. To do. The lower protective insulating film 136 can be formed using a sputtering method, a CVD method, or the like.

  Then, by forming the upper protective insulating film 138 on the lower protective insulating film 136, the semiconductor device 100 shown in FIG. 3 can be manufactured. The upper protective insulating film 138 can be formed using a CVD method, a sputtering method, or the like. Thereafter, contact holes connected to any one of the source electrode 102, the drain electrode 104, the capacitor lower electrode 142, the gate electrode 106, the gate extension 107, and the capacitor upper electrode 146 are formed in the upper protective insulating film 138 and the lower protective insulating film 136. The electrode wiring can be formed through the formed contact hole. Furthermore, a final product can be obtained by forming a final protective film.

  In the above embodiment, the insulating layer 134 is disposed on the surface of the cap layer 132 or the surface of the element isolation region 140 other than between the gate electrode 106 and the cap layer 132. However, even if there is a portion that is not covered by the insulating layer 134 on the surface of the cap layer 132 or the element isolation region 140, the cap layer 132 or the element isolation region 140 is formed by the passivation of the two-layer protective insulating film of this embodiment. On the other hand, impurities that become donors or acceptors can be prevented from contacting the cap layer 132 or the element isolation region 140. Thereby, generation | occurrence | production of leak current can be suppressed.

  FIG. 11 schematically shows a cross-sectional example of a semiconductor device 200 according to another embodiment. A schematic top view of the semiconductor device 200 is the same as FIG.

  The a part, b part, and c part of FIG. 11 show the same cross-sectional examples as FIG. In the semiconductor device 100 shown in part a and part b of FIG. 3, the surface of the cap layer 132 or the surface of the element isolation region 140 is all covered with the insulating layer 134. On the other hand, the semiconductor device 200 shown in FIGS. 11A and 11B is different in that the surface of the cap layer 132 or the surface of the element isolation region 140 is not covered by the gate insulating layer 234.

  When an impurity that becomes a donor or an acceptor with respect to the cap layer 132 of a semiconductor material is in contact with the cap layer 132, for example, when the upper protective insulating film 138 having silicon nitride is in direct contact with the cap layer 132, the silicon is the cap layer. It becomes a donor or an acceptor for 132 and may form a leak path at the contact interface. However, since the semiconductor device 200 includes the lower protective insulating film 136, diffusion of donor impurities and the like into the cap layer 132 can be prevented.

  12 to 17 schematically show cross sections in the manufacturing process of the semiconductor device 200 shown in FIG. However, description of the same contents as in FIGS. 4 to 10 may be omitted.

  As shown in FIG. 4, a semiconductor material substrate including a support substrate 122, a buffer layer 124, a channel layer 126, a spacer layer 128, a carrier supply layer 130, and a cap layer 132 is prepared. The semiconductor material substrate only needs to have a semiconductor layer capable of forming an electric element element. For example, the semiconductor material substrate may be constituted by the support substrate 122, the channel layer 126, and the carrier supply layer 130.

  As shown in FIG. 12, the source electrode 102, the drain electrode 104, and the capacitor | condenser lower electrode 142 are formed. In forming the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142, first, a photoresist film having openings at the formation site of the source electrode 102 and the drain electrode 104 is formed on the surface of the cap layer 132. By etching using the photoresist film as a mask, the cap layer 132 at the site where the source electrode 102 and the drain electrode 104 are formed is removed.

Thereafter, a conductive film to be the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142 is deposited, and then the photoresist film is lifted off to form the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142. Examples of the method for etching the cap layer 132 include dry etching using chlorine gas or chlorine-based gas. After forming the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142, the source electrode 102, the drain electrode 104, and the capacitor lower electrode 142 may be annealed for the purpose of sintering and the like. An example of the annealing process is a heat treatment at 750 ° C. for 3 minutes in an N ₂ atmosphere.

  As shown in FIG. 13, an element isolation region 140 is formed. The element isolation region 140 can be formed by, for example, photolithography using a photoresist film having an opening in a region where the element isolation region 140 is to be formed, and using the photoresist film as a mask, for example, by boron ion implantation. It can also be formed by argon ion implantation.

  As shown in FIG. 14, the gate insulating layer 234 is formed by sputtering, for example. In this embodiment, since the capacitor insulating layer 144 can be formed simultaneously with the gate insulating layer 234, the process can be simplified.

  As shown in FIG. 15, the gate electrode 106 and the gate extension portion 107 are formed on the surface of the gate insulating layer 234. At the same time, a capacitor upper electrode 146 is formed on the surface of the capacitor insulating layer 144. For example, the gate electrode 106, the gate extension 107, and the capacitor upper electrode 146 are formed by forming a photoresist film having an opening in a region where the gate electrode 106, the gate extension 107 and the capacitor upper electrode 146 are to be formed, and then depositing a conductive film. The photoresist film can be lifted off.

As shown in FIG. 16, the gate insulating layer 234 in the region other than the portion covered with the electrode or the like is removed by using, for example, an etching method. As a method for etching the gate insulating layer 234, dry etching using an F-based mixed gas can be exemplified. Thereafter, annealing may be performed. By this annealing treatment, damage due to dry etching can be reduced and the on-resistance of the transistor can be lowered. As a method for the annealing treatment, for example, a treatment at 360 ° C. for 60 minutes in an N ₂ atmosphere can be exemplified.

  Note that ion implantation may be performed again in the element isolation region 140 for the purpose of improving the insulation of the element isolation region 140. Leakage current can be effectively suppressed by ion implantation again.

  In part a of FIG. 16, the gate insulating layer 234 is not disposed on the surface of the cap layer 132 between the source electrode 102 and the gate electrode 106 and between the gate electrode 106 and the drain electrode 104. Therefore, when an impurity that becomes a donor or an acceptor with respect to the cap layer 132 is in contact with the cap layer 132, a leak path may be formed and a leak current may be generated. Also in part b of FIG. 16, the gate insulating layer 234 is not disposed on the surface of the element isolation region 140 between the source electrode 102 and the gate extension 107 and between the gate extension 107 and the drain electrode 104. There is a possibility that a leak current similarly occurs on such a surface. However, in this example, since the lower protective insulating film 136 is formed, it is possible to suppress the impurities that become donors or acceptors from entering the cap layer 132 or the element isolation region 140.

  As shown in FIG. 17, a lower protective insulating film 136 is formed to cover the source electrode 102, the drain electrode 104, the capacitor lower electrode 142, the gate electrode 106, the gate extension 107, and the capacitor upper electrode 146, which is an example of an electric element element. To do. The lower protective insulating film 136 can be formed using a sputtering method, a CVD method, or the like.

  Then, by forming the upper protective insulating film 138 on the lower protective insulating film 136, the semiconductor device 200 shown in FIG. 11 can be manufactured. The upper protective insulating film 138 can be formed using a CVD method, a sputtering method, or the like.

  In this embodiment, an impurity which becomes a donor or an acceptor for the cap layer 132 or the element isolation region 140 by the two-layer passivation that forms the upper protective insulating film 138 on the high dielectric lower protective insulating film 136 that does not contain silicon. Can be prevented from contacting the cap layer 132 or the element isolation region 140. Further, by adopting the above configuration, silicidation of the metal contained in the electronic element element and Si contained in the upper protective insulating film can be suppressed. As a result, generation of leakage current can be suppressed.

Example 1
A high electron mobility transistor having the structure shown in part a and part b of FIG. 3 was manufactured. As the support substrate 122, a SiC wafer was used. On the SiC wafer, a GaN buffer layer 124, an i-type GaN channel layer 126, an i-type AlGaN spacer layer 128, an n-type AlGaN carrier supply layer 130, and an n-type GaN cap layer 132 are formed by MOCVD. A semiconductor material substrate was prepared by sequentially forming by epitaxial growth.

An insulating layer 134 made of tantalum oxide having a thickness of 20 nm was formed on the cap layer 132 by sputtering. The insulating layer 134 at the site where the source electrode 102 and the drain electrode 104 were formed was removed by photolithography and dry etching using an F-based mixed gas. Further, the cap layer 132 was removed using a dry etching method using chlorine gas or chlorine-based gas. After forming a laminated film made of titanium, aluminum, nickel, and gold, unnecessary laminated films were removed by lift-off, and the source electrode 102 and the drain electrode 104 were formed. Thereafter, annealing was performed at 750 ° C. for 3 minutes in an N ₂ atmosphere.

  An element isolation region 140 was formed. The element isolation region 140 was formed by ion implantation of boron using a photoresist film having an opening in a region where the element isolation region 140 is to be formed by photolithography, and using the photoresist film as a mask.

A photoresist film having an opening at the site where the gate electrode 106 was formed was formed by photolithography, a nickel film was deposited, and then the unnecessary nickel film was removed by lift-off to form a nickel gate electrode 106. Thereafter, annealing was performed at 360 ° C. for 60 minutes in an N ₂ atmosphere. Boron ions were implanted again into the element isolation region 140 for the purpose of improving the insulation of the element isolation region 140.

  A 5 nm-thick tantalum oxide lower protective insulating film 136 was formed by sputtering, and a 200 nm-thick silicon nitride upper protective insulating film 138 was formed thereon by CVD. Furthermore, by forming wirings and the like, the high electron mobility transistor used in this example was manufactured. In the high electron mobility transistor manufactured in Example 1, the length of the gate electrode is 1 μm and the width of the gate electrode is 100 μm. The source electrode and the drain electrode have a width in the gate electrode length direction of 15 μm and a width in the gate electrode width direction of 100 μm. The distance between the source electrode and the drain electrode is 3 μm.

  FIG. 18 shows the results of measuring the gate leakage current of the manufactured high electron mobility transistor. The horizontal axis represents the gate voltage, and the vertical axis represents the gate current. When a voltage of −30 V was applied to the gate electrode, a very low leakage current of 30 pA / mm was observed. In a conventional high electron mobility transistor that does not use the lower protective insulating film 136, the leakage current cannot be suppressed to 1 nA or less, but as shown in FIG. 18, by passivation of the two-layer protective insulating film having the lower protective insulating film 136, The gate leakage current can be greatly reduced.

(Example 2)
FIG. 19 schematically shows an example of the configuration of the switch circuit. The switch circuit 300 may be a DC / RF switch. The switch circuit 300 includes a transistor 302, a transistor 304, a transistor 306, an input terminal 308, an output terminal 310, a DC terminal 312, a DC terminal 314, a control terminal 322, a control terminal 324, and a control terminal 326. With.

  The switch circuit 300 switches input signals input from the input terminal 308, the DC terminal 312, and the DC terminal 314, and outputs any one signal from the output terminal 310. The switch circuit 300 receives a high-frequency signal (hereinafter sometimes referred to as an RF signal) from the input terminal 308, and receives a DC signal from the DC terminal 312 and the DC terminal 314.

  The transistor 302, the transistor 304, and the transistor 306 are turned on and off in accordance with a control signal input to the control terminal 322, the control terminal 324, or the control terminal 326, respectively. As a result, the switch circuit can output any one of the input signals input from the input terminal 308, the DC terminal 312 and the DC terminal 314.

  The transistor 302, the transistor 304, and the transistor 306 may be high electron mobility transistors having the structure described in Embodiment 1. Thereby, a switch circuit with little insertion loss can be obtained even in a high frequency band.

  The on-resistance value of the high electron mobility transistor having the structure shown in Example 1 was 2 Ωmm or less. In order to investigate the characteristics of the switch circuit 300, the insertion loss of the switch circuit was measured.

  FIG. 20 shows the relationship between the frequency of the RF signal input from the input terminal 308 and the insertion loss of the switch circuit 300. In FIG. 19, the vertical axis represents insertion loss [dB], and the horizontal axis represents the frequency [GHz] of the RF signal. As shown in FIG. 20, the switch circuit 300 had an insertion loss of −3 dB even when the frequency of the input signal was 30 GHz. Thus, as described above, a switch circuit having excellent insertion loss characteristics was obtained by applying the semiconductor device adopting the above configuration to the switch circuit.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

The cross section of the semiconductor device 10 which is this embodiment is shown schematically. The upper surface of the semiconductor device 100 which is other embodiment is shown schematically. The cross section of the semiconductor device 100 shown in FIG. 2 is shown schematically. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. 1 schematically shows a cross section of the semiconductor device 100 in the manufacturing process. The cross section of the semiconductor device 200 which is other embodiment is shown schematically. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. 1 schematically shows a cross-section in the process of manufacturing a semiconductor device 200. The measurement result of gate leakage current is shown. 1 schematically shows a switch circuit according to an embodiment. The result of having measured the insertion loss of the circuit of FIG. 19 is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Semiconductor substrate 14 Electric element 16 Lower layer protective insulating film 18 Upper layer protective insulating film 100 Semiconductor device 102 Source electrode 104 Drain electrode 106 Gate electrode 107 Gate extension part 108 Source extraction wiring 110 Drain extraction wiring 112 Gate pad 114 Source wiring 116 Drain wiring 118 Gate wiring 122 Support substrate 124 Buffer layer 126 Channel layer 128 Spacer layer 130 Carrier supply layer 132 Cap layer 134 Insulating layer 136 Lower layer protective insulating film 138 Upper layer protective insulating film 140 Element isolation region 142 Capacitor lower electrode 144 Capacitor insulating layer 146 Capacitor upper electrode 200 Semiconductor device 234 Gate insulating layer 300 Switch circuit 302 Transistor 304 Transistor 306 Transistor 308 Input terminal 310 Output Force terminal 312 DC terminal 314 DC terminal 322 Control terminal 324 Control terminal 326 Control terminal

Claims (15)

A plurality of electrical element elements adjacent to each other along the surface of the semiconductor material;
A lower protective insulating film that does not contain silicon and covers the plurality of electrical element elements;
An upper protective insulating film that is disposed on the lower protective insulating film and contains silicon;
A semiconductor device comprising: At least one of the plurality of electrical element elements contains a metal to be silicided;
The lower protective insulating film inhibits contact between the metal contained in the electrical element element and silicon contained in the upper protective insulating film;
The semiconductor device according to claim 1. The lower protective insulating film has a high dielectric layer having a relative dielectric constant of 10 or more.
The semiconductor device according to claim 1 or 2. The upper protective insulating film contains silicon and nitrogen;
The semiconductor device according to claim 1. The upper protective insulating film is a silicon nitride film formed as a thin film at a temperature of 260 ° C. or lower.
The semiconductor device according to claim 4. The upper protective insulating film is a silicon nitride film formed as a thin film at a temperature of 100 ° C. or lower.
The semiconductor device according to claim 4. At least one of the plurality of electrical element elements is:
An electrode or a terminal constituting an active element or a passive element formed on the surface of the semiconductor material, or a lead portion connected to the active element or the passive element;
The semiconductor device according to any one of claims 1 to 6, wherein: The plurality of electric element elements include a gate electrode, a source electrode, and a drain electrode of a MIS field effect transistor,
The semiconductor device according to claim 7. The plurality of electrical element elements further include a gate extension, a source extension, and a drain extension extending from the gate electrode, the source electrode, and the drain electrode.
The semiconductor device according to claim 8. An inter-element insulating film having a high dielectric layer having a relative dielectric constant of 10 or more, disposed between the semiconductor material and at least one of the electric element elements;
The semiconductor device according to claim 1. The inter-element insulating film is also disposed on the surface of the semiconductor material between the plurality of electric element elements,
Impeding impurities that become donors or acceptors for the semiconductor material from contacting the semiconductor material;
The semiconductor device according to claim 10. At least one of the electric element elements is a gate electrode of a MIS field effect transistor,
The inter-element insulating film is a gate insulating film of the MIS field effect transistor.
12. The semiconductor device according to claim 10 or claim 11. The leakage current at the gate width of 1 mm of the MIS field effect transistor is 500 pA or less,
The on-resistance of the MIS field effect transistor is 2 Ωmm or less.
The semiconductor device according to claim 8, claim 9 or claim 12. Forming a plurality of electrical element elements such that they are adjacent to each other along the surface of the semiconductor material;
Forming a lower protective insulating film not containing silicon and covering the plurality of electrical element elements;
Forming an upper protective insulating film containing silicon on the lower protective insulating film;
A method for manufacturing a semiconductor device comprising: A switch circuit including a semiconductor device that operates as a switch element,
The semiconductor device includes:
A plurality of electrical element elements adjacent to each other along the surface of the semiconductor material;
A lower protective insulating film that does not contain silicon and covers the plurality of electrical element elements;
An upper protective insulating film disposed on the lower protective insulating film and containing silicon;
A switch circuit comprising:

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