JP2019012827A - Gallium nitride semiconductor device and manufacturing method therefor - Google Patents

Abstract

To provide a semiconductor device using a gallium nitride semiconductor having excellent interface characteristics between a semiconductor layer and an insulator layer.SOLUTION: A semiconductor device 100 includes a semiconductor layer 101 containing gallium nitride, a gate electrode 105, and an insulator layer 102 provided between the semiconductor layer 101 and the gate electrode 105, and the gallium nitride is a single crystal, and the insulator layer 102 has at least a first insulating film 103 containing a crystal of gallium oxide in a portion adjacent to the semiconductor layer 101, and in the crystal of gallium oxide, the crystal lattice of gallium nitride matches an in-plane lattice constant a.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a gallium nitride-based semiconductor device having excellent interface characteristics between a semiconductor layer and an insulator layer, and a method for manufacturing the same.

Gallium nitride semiconductors are attracting attention not only as short-wavelength optical devices such as blue semiconductor lasers but also as high-frequency power devices due to their high breakdown field strength, high thermal conductivity, and high electron saturation speed. Yes. For example, in the case of a GaN semiconductor, the band gap is 3.4 eV, and the saturation electron velocity (V _sat ) is more than twice that of Si and GaAs, about 10 times that of Si, and about 7.5 times that of GaAs. Having a dielectric breakdown electric field strength (E _c ) of When compared with the Johnson index represented by V _sat · E _c / 2π, which is often used as an index for comparing the performance of high-frequency and high-power amplifiers using semiconductors, GaN is about 27 times as much as Si and GaAs In comparison, the size is about 15 times, and from these, GaN is recognized as a semiconductor having an overwhelming advantage.

  However, semiconductor devices such as MISFETs (Metal Insulator Semiconductor Field Transistors) using gallium nitride semiconductors and MOSFETs (Metal Oxide Field Transistors) are disclosed in non-patent literature such as non-patent literature. A gate leakage current may be generated between the gate and the drain due to a reaction between the oxide on the surface of the semiconductor and the deposited metal.

In order to suppress the generation of the gate leakage current, there is an aspect in which an insulating film such as a SiN film (silicon nitride film) or a SiO ₂ film (silicon oxide film) is deposited on the surface of a gallium nitride based semiconductor. The presence of an oxide on the surface of the semiconductor of the system causes an interface state to be generated at the interface between the semiconductor surface and the insulating film, and trap sites are easily introduced. Therefore, in such a MISFET or MOSFET, there is a problem that the characteristics depending on the frequency are likely to change.

In order to avoid such a problem, in Patent Document 1, gallium nitride represented by (In _x Al _1-x ) _y Ga _1-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) A thermally oxidized gallium oxide (Ga ₂ O ₃ ) thermal oxide film is formed on the surface of the semiconductor, and an insulating film such as SiO ₂ by plasma CVD is formed on the formed thermal oxide film. It has a structure in which a gate electrode is formed thereon.

JP 2003-258258 A

Surf. Sci. Pp.532-535, pp.759-763 (2003)

  The present invention eliminates the problems of the gate leakage current and the deterioration of frequency characteristics in gallium nitride semiconductor devices, particularly MISFETs and MOSFETs using gallium nitride semiconductors. It is an object of the present invention to provide a gallium nitride semiconductor device having excellent interface characteristics and a method for manufacturing the same.

  According to one aspect of the present invention, a semiconductor device includes a semiconductor layer containing gallium nitride, a gate electrode, and an insulator layer provided between the semiconductor layer and the gate electrode. And the insulator layer has at least a first insulating film containing a gallium oxide crystal in a portion adjacent to the semiconductor layer, and the gallium oxide crystal has a crystal lattice of gallium nitride and an in-plane lattice constant a. Consistent.

  According to an embodiment of the present invention, in a semiconductor device, gallium nitride is a wurtzite single crystal, and the gallium oxide crystal is a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. It is a crystal.

  According to one embodiment of the present invention, in a semiconductor device, gallium nitride is a single crystal having a wurtzite structure, and the gallium oxide crystal is a cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. It is a crystal.

  According to one embodiment of the present invention, in a semiconductor device, gallium nitride is a wurtzite single crystal, and the gallium oxide crystal has a hexagonal crystal with an a-axis lattice constant of 0.28 nm to 0.34 nm. It is a cubic crystal.

  According to an embodiment of the present invention, in the semiconductor device, the gallium oxide crystal is selected from the group consisting of ε-structure gallium oxide, γ-structure gallium oxide, and combinations thereof.

  According to one embodiment of the present invention, in the semiconductor device, the crystal plane of the gallium oxide crystal is aligned with the crystal plane of the semiconductor layer.

  According to one embodiment of the present invention, in the semiconductor device, the thickness of the first insulating film is not less than the thickness of the monoatomic layer of the gallium oxide crystal and not more than 10 nm.

  According to one embodiment of the present invention, in the semiconductor device, the thickness of the first insulating film is 5 nm or less.

  According to one embodiment of the present invention, in the semiconductor device, the first insulating film is a gallium oxide crystal in which the in-plane lattice constant a is matched with the crystal lattice of gallium nitride, or the lattice constant of the a axis is 0. In the case of having a gallium oxide crystal that is at least one of hexagonal crystal and cubic crystal of 28 nm or more and 0.34 nm or less, the volume ratio occupied by the gallium oxide crystal in the first insulating film is 95% or more It is.

  According to one embodiment of the present invention, in the semiconductor device, the first insulating film has a combination of ε-structure gallium oxide and γ-structure gallium oxide, and the ε-structure oxidation is performed in the first insulating film. The volume ratio occupied by the gallium crystal is 70% or more and 90% or less, and the γ-structure gallium oxide crystal occupies the remaining portion of the first insulating film.

  According to one embodiment of the present invention, in the first insulating film of the semiconductor device, the volume ratio occupied by the gallium oxide crystal of ε structure is 80%, and the ratio of the gallium oxide crystal of γ structure is 20%.

  According to one embodiment of the present invention, in the semiconductor device, the first insulating film has a combination of ε-structure gallium oxide and γ-structure gallium oxide, and the ε-structure oxidation is performed in the first insulating film. The volume ratio occupied by gallium oxide and gallium oxide having a γ structure is 95% or more.

  According to one embodiment of the present invention, in the semiconductor device, the insulator layer includes a second insulating film provided between the gate electrode and the first insulating film, and the second insulating film is made of aluminum. (Al), silicon (Si), hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti), gallium (Ga), yttrium (Y), scandium (Sc), elements of rare earth elements Having an oxide, nitride, or oxynitride of at least one element selected from the group.

  According to one embodiment of the present invention, in a semiconductor device, the gate electrode is formed of aluminum (Al), titanium (Ti), tungsten (W), platinum (Pt), gold (Au), silver (Ag), ruthenium ( And at least one selected from the group consisting of Ru), rhodium (Rh), palladium (Pd), nickel (Ni), tin (Sn), zinc (Zn), and poly-Si.

  According to one embodiment of the present invention, the above-described method for manufacturing a semiconductor device includes a semiconductor layer preparation step for preparing a semiconductor layer, an insulator layer formation step for forming an insulator layer, and a gate electrode formation for forming a gate electrode. At least a process.

  According to one embodiment of the present invention, in the method for manufacturing a semiconductor device, the insulator layer forming step includes the step of forming the semiconductor layer into sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, hydroxylation. Forming a first insulating film by performing a surface treatment using at least one selected from the group consisting of potassium;

  According to an embodiment of the present invention, in the method for manufacturing a semiconductor device, the insulator layer forming step includes performing a plasma oxidation process and / or an ozone oxidation process on the semiconductor layer at a temperature of 500 ° C. or lower, thereby providing a first insulation. Forming a film.

  According to an embodiment of the present invention, in the semiconductor device manufacturing method, the insulator layer forming step is performed at 870 ° C. using an electron beam evaporation method and / or MBE method at 700 ° C. or lower on the semiconductor layer. First insulation using CVD method below, using HVPE method below 700 ° C., using ALD method below 500 ° C. and / or using sputtering method below 500 ° C. Laminating a film.

  According to one embodiment of the present invention, in the method for manufacturing a semiconductor device, the insulator layer forming step includes forming a gallium oxide crystal on the semiconductor layer by a heat treatment of 500 ° C. or more and 870 ° C. or less, and then performing etching. And forming a first insulating film by reducing the thickness of the gallium oxide crystal to 10 nm or less.

  According to the present invention, a gallium nitride semiconductor device having good electrical characteristics and a method for manufacturing the same are provided by reducing trap sites due to interface states between the semiconductor layer and the insulator layer. Here, a gallium nitride semiconductor device refers to a semiconductor device having a semiconductor layer containing gallium nitride.

  Other objects, features and advantages of the present invention will become apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a semiconductor device as a first embodiment of the present invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device of the 2nd Embodiment of this invention. It is a section schematic diagram showing a manufacturing process of a semiconductor device of a 3rd embodiment of the present invention. It is a section schematic diagram showing a manufacturing process of a semiconductor device of a 3rd embodiment of the present invention. It is a section schematic diagram showing a manufacturing process of a semiconductor device of a 3rd embodiment of the present invention. It is a schematic sectional drawing of the MIS capacitor as an Example of this invention. It is a characteristic view which shows the XPS Ga _3d spectrum after the surface treatment in the manufacturing process of the MIS capacitor of FIG. FIG. 10 is a partially enlarged cross-sectional view of the MIS capacitor of FIG. 7 on a Miller index [1-100] plane by TEM (Transmission Electron Microscope). It is a partially expanded sectional view in the Miller index [11-20] plane by TEM of the MIS capacitor of FIG. It is a characteristic view which shows the CV (capacitance-voltage) characteristic of the MIS capacitor of FIG. FIG. 3 is a structural diagram of a cubic crystal of gallium oxide viewed from the (100) plane. FIG. 3 is a structural diagram of a cubic crystal of gallium oxide viewed from a (111) plane. FIG. 3 is a structural diagram showing the arrangement of oxygen atoms at the cut surface when cubic gallium oxide is sliced along a (111) plane. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device of the 4th Embodiment of this invention. It is a cross-sectional schematic diagram which shows the manufacturing process of the semiconductor device of the 4th Embodiment of this invention. It is the cross-sectional TEM observation image and FFT figure which show the structure of the insulating film of this invention.

  Examples of the present invention will be described below with reference to the drawings, but the present invention is not limited to these examples.

<Embodiment 1>
In the first embodiment, a gallium nitride semiconductor device 100 which is a lateral MISFET will be described with reference to FIG.
The semiconductor device 100 includes a semiconductor layer (channel layer) 101 containing gallium nitride formed on a gallium nitride free-standing substrate 111, a gate electrode 105, and an insulator provided between the semiconductor layer 101 and the gate electrode 105. A layer (gate insulating film) 102.
The gallium nitride of the semiconductor layer 101 is preferably a single crystal, and the gallium nitride is more preferably a wurtzite single crystal. The semiconductor layer 101 is more preferably made of single crystal gallium nitride.

The insulator layer 102 includes a first insulating film 103 in a portion adjacent to the semiconductor layer 101. The insulator layer 102 may include a second insulating film 104 provided between the gate electrode 105 and the first insulating film 103. Here, the second insulating film 104 may be a single-layer film or a stacked film including a plurality of films.
Further, the semiconductor device 100 may include a source region 107 and a drain region 108 by injecting impurities into the semiconductor layer 101 in order to configure a MISFET. For example, when the semiconductor layer 101 is n-type gallium nitride, the source region 107 and the drain region 108 are formed by implanting p-type impurities into the semiconductor layer 101.
The semiconductor device 100 includes a source electrode 109 and a drain electrode 110 on the source region 107 and the drain region 108, respectively.

The first insulating film 103 includes a gallium oxide crystal whose in-plane lattice constant a is matched with the gallium nitride crystal lattice forming the semiconductor layer 101.
Here, that the in-plane lattice constant a is matched means that the difference in crystal lattice constant a between gallium nitride and gallium oxide is within ± 15%. When the difference in crystal lattice constant a between gallium nitride and gallium oxide is within ± 15%, the generation of trap sites in the insulator layer 102 can be suppressed.

  As a single crystal of gallium nitride constituting the semiconductor layer 101, a single crystal having a wurtzite structure can be cited from the viewpoint of crystal stability. When a wurtzite single crystal is used as the gallium nitride constituting the semiconductor layer 101, the gallium oxide crystal constituting the first insulating film 103 has an a-axis lattice constant of 0.28 nm to 0.34 nm. It is preferably at least one of hexagonal crystals and cubic crystals.

  Here, the a-axis lattice constant in the present invention refers to a normal a-axis lattice constant in the case of a hexagonal crystal, and in the case of a cubic crystal, the crystal lattice at the cut surface when sliced by the (111) plane. The lattice constant of

FIG. 11 is a view of cubic gallium oxide, for example, γ-Ga ₂ O ₃ crystal, viewed from the (100) plane. In FIG. 11, 1 represents oxygen atoms (O) and 2 represents gallium atoms (Ga). Represent. In the plane (in-plane) sliced by the (100) plane, hexagonal oxygen atom arrangement is not recognized, and lattice matching with the GaN semiconductor in contact with this plane does not occur.

FIG. 12 is a view of cubic gallium oxide, for example, γ-Ga ₂ O ₃ crystal, viewed from the (111) plane. Here, 1 in FIG. 12 represents an oxygen atom (O) and 2 represents a gallium atom (Ga) as in the case of FIG. Then, when this crystal is sliced at a location having the (111) plane and the oxygen atom 1, the arrangement of atoms located at the cut end is shown in FIG. As can be seen from FIG. 13, the oxygen atom 1 (in this in-plane) at this cut has the same crystal arrangement (crystal lattice 11) as the hexagonal crystal.
In the present invention, a ₁ shown in 21 of FIG. 13, a ₂ shown in 22 in FIG. 13, and a ₃ shown in 23 in this in-plane are set to a lattice constant of the a axis. The values of ₁ , a _2, and a ₃ are almost equal and can be expressed by a lattice constant a.

  The crystal structure of wurtzite gallium nitride is a hexagonal crystal with an a-axis lattice constant of 0.319 nm. The inventor has found that when gallium oxide has a hexagonal crystal structure with an a-axis lattice constant of 0.28 nm to 0.34 nm, the lattice is matched and generation of trap sites is sufficiently suppressed. In addition, when the gallium oxide is a (111) -plane cubic crystal, the inventor has sufficient gallium nitride and lattice of a wurtzite structure that is a hexagonal structure when the lattice constant of the a axis is 0.28 nm or more and 0.34 nm or less. It was found that the generation of trap sites was sufficiently suppressed. Furthermore, the inventor has found that when the gallium oxide is composed of hexagonal gallium oxide having a lattice constant of a-axis of 0.28 nm or more and 0.34 nm or less and cubic gallium oxide, the lattice is matched and the trap site. It has been found that the occurrence of is sufficiently suppressed.

The first insulating film 103 may be composed of ε-structure gallium oxide or γ-structure gallium oxide, or a combination of ε-structure gallium oxide and γ-structure gallium oxide.
Here, ε-structure gallium oxide has a hexagonal crystal structure, and its a-axis crystal lattice constant is 0.290 nm. Further, gallium oxide having a γ structure has a cubic crystal structure, and the crystal lattice constant of the a axis in the (111) plane is 0.291 nm.
Incidentally, the thermally oxidized gallium oxide disclosed in Patent Document 1 is β-Ga ₂ O ₃ because it is formed in a 900 ° C. dry oxygen atmosphere. β-Ga ₂ O ₃ is monoclinic and has lattice constants of a = 1.214 nm, b = 0.30371 nm, and c = 0.57981 nm. Further, α = γ = 90 °, β = 108.83 °, and β-Ga ₂ O ₃ is not lattice-matched with gallium nitride having a wurtzite structure.

  The crystal plane of gallium oxide constituting the first insulating film 103 is preferably aligned with the crystal plane of the semiconductor layer 101. For example, the first insulating film 103 may be formed so as to align the crystal plane of gallium oxide that is a hexagonal single crystal on the crystal plane of the Miller index [0001] of gallium nitride of the semiconductor layer 101.

  The thickness of the first insulating film 103 is preferably 10 nm or less. This is because if the thickness is larger than 10 nm, lattice mismatch tends to occur in the formed gallium oxide crystal, and trap sites increase. Furthermore, the thickness of the first insulating film 103 is more preferably 5 nm or less. Thus, it is preferable to reduce the thickness of the first insulating film 103 as much as possible. On the other hand, the thickness of the first insulating film 103 needs to be greater than or equal to the thickness of the monolayer of gallium oxide in order to ensure that gallium oxide is formed over the semiconductor layer 101. Further, when the thickness of the first insulating film 103 is equal to or greater than the thickness of the gallium oxide diatomic layer, there is an effect that generation of defects is reduced.

  When the first insulating film 103 has a gallium oxide crystal in which the in-plane lattice constant a is lattice-matched with gallium nitride, the gallium oxide in the first insulating film 103 in which the in-plane lattice constant a is matched The volume ratio occupied by the crystal is preferably 95% or more. In the case where the first insulating film 103 includes at least one of hexagonal and cubic gallium oxide crystals having an a-axis lattice constant of 0.28 nm to 0.34 nm, the first insulating film 103 The ratio of the volume occupied by at least one of hexagonal and cubic crystals of gallium oxide having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less is preferably 95% or more. With this configuration, generation of trap sites in the gate insulating film 102 formed between the gallium nitride based semiconductor layer 101 and the gate electrode 105 is sufficiently suppressed.

  When the first insulating film 103 is composed of a combination of ε-structure gallium oxide and γ-structure gallium oxide, the proportion of the ε-structure gallium oxide in the volume of the first insulating film 103 is 70% or more. 90% or less, and the proportion of γ structure gallium oxide is 10% or more and 30% or less, and the total proportion of ε structure gallium oxide and γ structure gallium oxide is 95% or more and 100% or less. It is preferable that For example, the ε-structure gallium oxide accounts for 80% of the volume of the first insulating film 103, and the γ-structure gallium oxide occupies the remaining 20% of the first insulating film 103. Also good. Further, in the volume of the first insulating film 103, the proportion of gallium oxide having an ε structure is 78% and the proportion of gallium oxide having a γ structure is 18%. The proportion of the total of ε-structure gallium oxide and γ-structure gallium oxide may be 96%, so that the proportion other than gallium oxide is 4%. With this configuration, generation of trap sites in the gate insulating film 102 formed between the gallium nitride based semiconductor layer 101 and the gate electrode 105 is sufficiently suppressed.

The second insulating film 104 of the insulator layer 102 is provided over the first insulating film 103 and is made of aluminum (Al), silicon (Si), hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium. (Ti), gallium (Ga), yttrium (Y), scandium (Sc), formed of an oxide, nitride, or oxynitride of at least one element selected from the group of elements consisting of rare earth elements . Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si _{2 3} N ₄ , SiON and the like can be mentioned.
The thickness of the second insulating film is preferably 3 nm to 100 nm, and more preferably 5 nm to 50 nm. When the thickness is 3 nm or less, a tunnel current is likely to be generated, or a gate breakdown voltage failure is likely to occur. Above 100 nm, FET characteristics such as current drive capability (Gm) tend to be insufficient.

  The gate electrode 105 is provided on the second insulating film 104 and is made of aluminum (Al), titanium (Ti), tungsten (W), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru). , Rhodium (Rh), palladium (Pd), nickel (Ni), tin (Sn), zinc (Zn), and poly-Si (polysilicon). In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, carbonitride including at least one selected from these groups may be used. In view of the work function, resistivity, heat resistance in the manufacturing process, contamination, and workability as the gate electrode of the MISFET, an optimum material is selected from these materials.

Next, a manufacturing process of the gallium nitride based semiconductor device 101 according to the first embodiment will be described with reference to FIG.
In this specification, n or p means that electrons or holes are majority carriers, respectively. In addition, regarding + or − described on the right shoulder of n or p, + means that the carrier concentration is higher than that in which it is not described, and − means that the carrier concentration is lower than that in which it is not described. To do.

Hereinafter, in order to make the description easy to understand, a case where an n ⁺ -type GaN single crystal substrate is used as the self-standing substrate 111 will be described. When a p-type substrate is used, n may be replaced with p and p with n. In this specification, “upper” and “upper” mean a first direction that is a direction from the freestanding substrate 111 to the semiconductor layer 101.

First, the semiconductor layer 101 is formed on the free-standing substrate 111 (FIG. 2A). For example, an n ⁺ -type GaN single crystal substrate is used as the free-standing substrate 111, and a p-type GaN layer is epitaxially formed as a semiconductor layer 101 with a thickness of about 2 μm in the first direction as the semiconductor layer 101. An example of a p-type impurity for GaN is Mg (magnesium).

Next, the screen layer 151 is formed on the entire main surface in direct contact with the main surface of the semiconductor layer 101 (FIG. 2B). Examples of the screen layer 151 include SiO ₂ having a thickness of about 20 nm in the first direction. The screen layer 151 has a function of preventing channeling that occurs in the semiconductor layer 101 during ion implantation.

Thereafter, impurities are implanted into the semiconductor layer 101 through the screen layer 151 to form the source region 107 and the drain region 108 (FIG. 2C). This implantation can be performed using the photoresist layer 161 as a mask, but ions can also be drawn and implanted without a mask. Examples of the impurity (n-type) to be implanted include Si, but are not limited to Si, and O (oxygen) or the like may be used. In the case of implanting Si, for example, 5 × 10 ¹⁵ cm ^{−2 is} implanted at 45 keV. Note that the photoresist layer 161 is sufficiently thick to shield Si, and Si is not implanted into the channel formation region. Note that a hard mask such as SiO ₂ may be used instead of the photoresist layer 161.

  Thereafter, the photoresist layer 161 is removed (FIG. 2D), and then the insulating layer 152 is formed on the screen layer 151 (FIG. 2E). Thereby, the cap layer 153 composed of the screen layer 151 and the insulating layer 152 is formed on the entire main surface.

  If the screen layer 151 is removed once immediately after the impurity implantation step for forming the source region 107 and the drain region 108, the surfaces of the amorphous source region 107 and the drain region 108 are exposed. This state is active and immediately combines with oxygen to form gallium oxide. Therefore, as in this example, the insulating layer 152 is increased without removing the screen layer 151.

  On the other hand, the insulating layer 152 may be provided in contact with the main surface after the screen layer 151 is removed. In this case, only the insulating layer 152 becomes the cap layer 153. Thereby, impurities mixed in the screen layer 151 during ion implantation can be removed together with the screen layer 151.

Examples of the insulating layer 152 include SiO ₂ having a thickness of about 480 nm in the first direction. In this case, the cap layer 153 has a thickness of about 500 nm by further stacking the insulating layer 152 on the screen layer 151. As the cap layer 153, Al ₂ O ₃ , SiN, and AlN can be used.
When the impurity in the semiconductor layer 101 is Mg, Al ₂ O ₃ , SiN and AlN are less likely to absorb Mg in the semiconductor layer 101 than SiO ₂ . In this case, it is desirable to use SiO ₂ as the cap layer 153 for the purpose of allowing the cap layer 153 to absorb Mg in the vicinity of the main surface of the semiconductor layer 101.

Thereafter, annealing is performed. An example of the annealing temperature is 1050 ° C. or higher and 1200 ° C. or lower. Examples of the atmospheric gas include Ar (argon) and / or N ₂ (nitrogen), but are not limited to this gas.

The cap layer 20 can absorb impurities (for example, Mg) in the semiconductor layer 101 in this annealing step. When the semiconductor layer 101 is a p-type GaN layer containing Mg as an impurity, the p-type impurity concentration in the semiconductor layer 101 is substantially reduced, so that the n-type source region 16 and the drain region 18 have a low resistance. can do. In the case of using the SiO ₂ cap layer 153, because it contains Si, the cap layer 153 does not absorb Si.

  Thereafter, the cap layer 153 is removed (FIG. 2F). By performing the annealing, the source region 107 and the drain region 108 are recrystallized. If the cap layer 153 is removed before annealing, the source region 107 and the drain region 108 may be peeled off together with the cap layer 153. When the cap layer 153 is removed after annealing, peeling of the source region 107 and the drain region 108 can be prevented.

Next, the first insulating film 103 and the second insulating film 104 are sequentially formed on the main surface, and the insulator layer 102 composed of the insulating film 103 and the second insulating film 104 is formed (FIG. 2G). ).
Here, the first insulating film 103 is an insulating film having a gallium oxide crystal in which the above-described gallium nitride and the in-plane lattice constant a are matched. Alternatively, the first insulating film 103 is an insulating film including at least one of hexagonal and cubic gallium oxide crystals having an a-axis lattice constant of 0.28 nm to 0.34 nm.

Alternatively, the first insulating film 103 is an insulating film containing a gallium oxide crystal, and includes, for example, the above-described ε-structure gallium oxide and / or γ-structure gallium oxide.
In general, a gallium oxide crystal has a stable β structure, and an ε structure or a γ structure has a metastable structure, but the first insulating film 103 is a gallium oxide crystal having an ε structure or a γ structure. Thus, the insulating film 103 having a favorable interface state with few trap sites, which is suitable as a gate insulating film, can be formed.

In the first method of forming the first insulating film 103, the surface of the semiconductor layer 101 containing gallium nitride is made of sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, or potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
As this oxidation method, SC1 (Standard Cleaning solution 1) (NH ₄ OH (ammonia water) -H ₂ O ₂ (hydrogen peroxide) -H ₂ O (water)), SC2 (Standard Cleaning solution 2) (HCl ( _{hydrochloride) -H 2 O 2 -H 2 O} ), SPM (sulfuric acid hydrogen Peroxide Mixture) (H 2 SO 4 ( sulfuric _{acid) -H 2 O 2 -H 2 O} ), buffered hydrofluoric acid solution (buffered Hydrogen fluoride: BHF) and the like are usually used as cleaning methods. A buffered hydrofluoric acid solution is generally known as a method for removing an oxide film. However, an oxide film having a gallium oxide crystal in which in-plane lattice constant a is matched with gallium nitride formed along with the removal, or an ε structure An oxide film containing gallium oxide and / or gallium oxide having a γ structure is a film suitable as the first insulating film 103.

  According to the first method, the crystal plane (gallium oxide crystal plane) of the first insulating film 103 is aligned with the crystal plane of the surface of the semiconductor layer 101. Therefore, the first method is particularly preferable in forming the high-quality insulating film 102 with few traps.

In addition, in this 1st method, you may use light irradiation together (Photo-Ectrochemical Oxidation). For example, the semiconductor layer 101 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or far-sighted external light having a wavelength of 190 nm or more and less than 280 nm (on the surface of the semiconductor layer 101 ( The first insulating film 103 may be formed by oxidizing the surface of the semiconductor layer 101 by irradiation with DUV.
In addition, the first method is characterized in that the heat load is less than that in the thermal oxidation treatment because it is a treatment at 280 ° C. or less even at room temperature or even when heat treatment is applied. When a large heat load is applied, problems such as changes in the profile of the implanted impurity and generation of stress tend to occur.

  The second method of forming the first insulating film 103 is to oxidize the surface of the semiconductor layer 101 by plasma oxidation in an atmosphere of 500 ° C. or lower, and oxidize in which the in-plane lattice constant a is matched with gallium nitride. An oxide film having a gallium crystal, an oxide film having at least one gallium oxide crystal of hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or ε-structure gallium oxide, and This is a method for forming gallium oxide having a γ structure. In addition, the surface of the semiconductor layer 101 is oxidized by ozone oxidation in an atmosphere of 500 ° C. or lower, and an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with the gallium nitride, an a-axis lattice Even if an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide having a constant of 0.28 nm or more and 0.34 nm or less, or an ε-structure gallium oxide and / or a γ-structure gallium oxide is formed. Good.

  A third method for forming the first insulating film 103 is to form gallium nitride on the surface of the semiconductor layer 101 by an electron beam evaporation method and / or a molecular beam epitaxy (MBE) method in an atmosphere of 700 ° C. or lower. And an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched, a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, and a cubic gallium oxide crystal of at least one of cubic crystals. Or an ε-structure gallium oxide and / or a γ-structure gallium oxide. Further, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by a chemical vapor deposition (CVD) method in an atmosphere of 870 ° C. or lower on the surface of the semiconductor layer 101. , An oxide film having at least one hexagonal crystal or cubic crystal of gallium oxide having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. May be deposited. Further, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by a hydride vapor phase epitaxy (HVPE) method in an atmosphere of 700 ° C. or lower on the surface of the semiconductor layer 101. , An oxide film having at least one hexagonal crystal or cubic crystal of gallium oxide having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. May be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and in-plane lattice constant a are matched by an atomic layer deposition (ALD) method in an atmosphere of 500 ° C. or lower in an atmosphere of 500 ° C. or lower, a Deposit an oxide film having at least one hexagonal crystal or cubic crystal of gallium oxide having an axial lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. You may let them. Further, gallium oxide is deposited on the surface of the semiconductor layer 101 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to have an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride , An oxide film having at least one hexagonal crystal or cubic crystal of gallium oxide having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. May be deposited.

  Note that when the first insulating film is formed under oxygen-rich conditions, ε-structure gallium oxide and / or γ-structure gallium oxide is formed.

  A fourth method for forming the first insulating film 103 is to form gallium oxide on the surface of the semiconductor layer 101 by heat treatment at 500 ° C. or higher, and then perform etching to reduce the thickness of the gallium oxide to 10 nm or less. Thus, the first insulating film is formed.

The second insulating film 104 is formed of an oxide, nitride, or acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and a rare earth element. Nitride is formed by sputtering, CVD, ALD, or the like. Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si _{2 3} N ₄ , SiON, and the like can be given. For example, when Al ₂ O ₃ is formed as the second insulating film by a sputtering method, Al can be used as a target, and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. Alternatively, it can be formed by an ALD method using trimethylaluminum.

Thereafter, a gate electrode 105 is formed on the insulator layer 102 (FIG. 2H).
The gate electrode 105 is formed by depositing a gate material constituting the gate electrode on the entire surface of the insulator layer 102, forming a photoresist layer having a desired pattern by lithography, and etching the gate material using the photoresist layer as an etching mask. To form. The gate electrode material is formed of at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, carbonitride including at least one selected from these groups may be used. As a deposition method of the gate electrode material, there are a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, a CVD method, and the like. This method is characterized by high gate electrode processing accuracy.
Further, after forming a photoresist layer for lift-off, a gate material is deposited by an evaporation method using an electron beam, a heating evaporation method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to remove the gate electrode 105. May be formed. This method is characterized in that the semiconductor device is not damaged by etching.
In addition, an interlayer film having an opening where the gate electrode is to be formed is formed on the insulator layer 102, a gate electrode material is deposited, and then gate insulation is performed by a CMP (Chemical Mechanical Polishing) method, an etch back method, or the like. The gate electrode 105 may be formed by embedding a material in the opening of the interlayer film. This method is characterized in that even when an electrode material that is difficult to etch is used, processing with sufficiently high accuracy is possible and damage to the semiconductor device due to etching is difficult to occur.

Thereafter, the source electrode 109 and the drain electrode 110 are formed (FIG. 2 (i)). At this time, openings are opened in advance in the insulator layer 102 of the source electrode 109 and the drain electrode 110 so that the source electrode 109 and the source region 107 and the drain electrode 110 and the drain region 108 are in electrical contact with each other. Keep it. In this electrical contact, ohmic contact is preferable. The source electrode 109 and the drain electrode 110 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited thereto. As the source electrode 109 and the drain electrode 110, in addition to Al and Ti, at least one selected from the group consisting of W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si is used. It may be formed. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, and carbonitride including at least one selected from these groups may be used.
The MISFET 100 is manufactured through the above steps.

  The MISFET 100 according to the manufacturing method of the first embodiment has a feature that a predetermined heat characteristic can be easily obtained because a desired heat treatment can be performed on the impurity and the profile of the semiconductor layer 101 before the gate electrode 105 is formed.

<Embodiment 2>
The semiconductor device of the second embodiment is a gallium nitride-based semiconductor device 100 that is a lateral MISFET as in the first embodiment, but its manufacturing method is different from that of the first embodiment. The manufacturing method will be described with reference to FIG.

First, the semiconductor layer 101 is formed on the free-standing substrate 111 (FIG. 3A).
Next, a first insulating film 103 and a second insulating film 104 are sequentially formed over the main surface of the semiconductor layer 101, and an insulator layer 102 including the insulating film 103 and the second insulating film 104 is formed (FIG. 3 (b)).
Here, the first insulating film 103 is an insulating film containing a gallium oxide crystal, for example, an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched with gallium nitride, and an a-axis lattice constant. An oxide film having a hexagonal crystal or cubic crystal gallium oxide crystal of 0.28 nm or more and 0.34 nm or less, or an insulating film having ε-structure gallium oxide and / or γ-structure gallium oxide. It is.
The first insulating film 103 is an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride, a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, and a cubic crystal. By using any one oxide film having a gallium oxide crystal or gallium oxide having an ε structure or a γ structure, the insulating film 103 having a favorable interface state with few trap sites suitable as a gate insulating film can be formed. it can.

In the first method of forming the first insulating film 103, the surface of the semiconductor layer 101 containing gallium nitride is made of sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, or potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
Examples of this oxidation method include SC1, SC2, SPM, buffered hydrofluoric acid solution and the like which are usually used for cleaning.
According to the first method, the crystal plane of the first insulating film 103 is aligned with the crystal plane of the surface of the semiconductor layer 101. Therefore, the first method is particularly preferable in forming the high-quality insulating film 102 with few traps.

In the first method, light irradiation may be used in combination. For example, the semiconductor layer 101 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or far-sighted external light having a wavelength of 190 nm or more and less than 280 nm (on the surface of the semiconductor layer 101 ( The first insulating film 103 may be formed by oxidizing the surface of the semiconductor layer 101 by irradiation with DUV.
In addition, the first method is characterized in that the heat load is less than that in the thermal oxidation treatment because it is a treatment at 280 ° C. or less even at room temperature or even when heat treatment is applied. When a large heat load is applied, problems such as changes in the profile of the implanted impurity and generation of stress tend to occur.

  The second method of forming the first insulating film 103 is to oxidize the surface of the semiconductor layer 101 by plasma oxidation in an atmosphere of 500 ° C. or lower, and oxidize in which the in-plane lattice constant a is matched with gallium nitride. An oxide film having a gallium crystal, an oxide film having at least one gallium oxide crystal of hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or ε-structure gallium oxide, and This is a method for forming gallium oxide having a γ structure. In addition, the surface of the semiconductor layer 101 is oxidized by ozone oxidation in an atmosphere of 500 ° C. or lower, and an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with the gallium nitride, an a-axis lattice Even if an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide having a constant of 0.28 nm or more and 0.34 nm or less, or an ε-structure gallium oxide and / or a γ-structure gallium oxide is formed. Good.

  In the third method of forming the first insulating film 103, gallium nitride and in-plane lattice constant a are matched on the surface of the semiconductor layer 101 by an electron beam evaporation method and / or MBE method in an atmosphere of 700 ° C. or lower. An oxide film having a gallium oxide crystal, an oxide film having at least one of hexagonal crystal and cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an oxide having an ε structure In this method, gallium oxide having a gallium and / or γ structure is deposited. In addition, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by a CVD method in an atmosphere of 870 ° C. or less on the surface of the semiconductor layer 101, and the a-axis lattice constant is 0.28 nm or more. An oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide having a size of 0.34 nm or less, or ε-structure gallium oxide and / or γ-structure gallium oxide may be deposited. In addition, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by an HVPE method in an atmosphere of 700 ° C. or lower on the surface of the semiconductor layer 101, and the a-axis lattice constant is 0.28 nm or more. An oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide having a size of 0.34 nm or less, or ε-structure gallium oxide and / or γ-structure gallium oxide may be deposited. In addition, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by an ALD method in an atmosphere of 500 ° C. or lower on the surface of the semiconductor layer 101, and the a-axis lattice constant is 0.28 nm or more. An oxide film having at least one of hexagonal crystal and cubic crystal of 0.34 nm or less, or an gallium oxide having an ε structure and / or a gallium oxide having a γ structure may be deposited. Further, gallium oxide is deposited on the surface of the semiconductor layer 101 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to have an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride , An oxide film having at least one hexagonal crystal or cubic crystal of gallium oxide having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. May be deposited.

  A fourth method for forming the first insulating film 103 is to form gallium oxide on the surface of the semiconductor layer 101 by heat treatment at 500 ° C. to 870 ° C., and then perform etching to reduce the thickness of the gallium oxide. In this method, the first insulating film is formed to 10 nm or less.

The second insulating film 104 is formed of an oxide, nitride, or acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and a rare earth element. Nitride is formed by sputtering, CVD, ALD, or the like. Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si _{2 3} N ₄ , SiON, and the like can be given. For example, when Al ₂ O ₃ is formed as the second insulating film by a sputtering method, Al can be used as a target, and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. Alternatively, it can be formed by an ALD method using trimethylaluminum.

Thereafter, a gate electrode 105 is formed on the insulator layer 102 (FIG. 3C).
The gate electrode 105 is formed by depositing a gate material constituting the gate electrode on the entire surface of the insulator layer 102, forming a photoresist layer having a desired pattern by lithography, and etching the gate material using the photoresist layer as an etching mask. To form. The gate electrode material is formed of at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, carbonitride including at least one selected from these groups may be used. As a deposition method of the gate electrode material, there are a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, a CVD method, and the like. This method is characterized by high gate electrode processing accuracy.
Further, after forming a photoresist layer for lift-off, a gate material is deposited by an evaporation method using an electron beam, a heating evaporation method, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to remove the gate electrode 105. May be formed. This method is characterized in that the semiconductor device is not damaged by etching.
Further, after forming an interlayer film on the insulator layer 102 with the location where the gate electrode is formed as an opening and depositing the gate electrode material, the gate insulating material is deposited on the interlayer film by a CMP method, an etch back method, or the like. The gate electrode 105 may be formed so as to be embedded in the opening. This method is characterized in that even when an electrode material that is difficult to etch is used, processing with sufficiently high accuracy is possible and damage to the semiconductor device due to etching is difficult to occur.

  Thereafter, impurities are implanted into the semiconductor layer 101 using the gate electrode as a mask to form a source region 107 and a drain region 108 (FIG. 3D). Impurities to be implanted are the same as those in the first embodiment.

Thereafter, the source electrode 109 and the drain electrode 110 are formed (FIG. 3E). At this time, openings are opened in advance in the insulator layer 102 of the source electrode 109 and the drain electrode 110 so that the source electrode 109 and the source region 107 and the drain electrode 110 and the drain region 108 are in electrical contact with each other. Keep it. In this electrical contact, ohmic contact is preferable. The source electrode 109 and the drain electrode 110 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited thereto. As the source electrode 109 and the drain electrode 110, in addition to Al and Ti, at least one selected from the group consisting of W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si is used. It may be formed. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, and carbonitride including at least one selected from these groups may be used.
The MISFET 100 is manufactured through the above steps.

  In the MISFET 100 according to the manufacturing method of the second embodiment, the source region 107, the drain region 108, and the channel region are formed by self-alignment using the gate electrode 105 as a mask. There is a feature that it is easy to get accuracy. For this reason, the manufacturing method of the second embodiment is a suitable method for achieving high integration.

<Embodiment 3>
In the third embodiment, a vertical MISFET 300 will be described with reference to FIGS.

In this specification, the surface of the n-type semiconductor substrate 350 on the side where the gate electrode 340 is provided is referred to as a front surface for the sake of convenience, and the surface of the n-type semiconductor substrate 350 on the side of which the drain electrode 346 is provided is referred to as a back surface for convenience. . A direction from the back surface to the front surface is referred to as a front surface direction, and a direction from the front surface to the back surface is referred to as a back surface direction. The surface in the surface direction side of the layer or film is referred to as the front surface side, and the surface in the back surface direction is referred to as the back surface side.
In the present specification, n or p means that electrons or holes are majority carriers, respectively. In addition, regarding + or − described on the right shoulder of n or p, + means that the carrier concentration is higher than that in which it is not described, and − means that the carrier concentration is lower than that in which it is not described. To do.
In the present specification, the first conductivity type is p-type or p ⁺ type, and the second conductivity type is n-type or n ⁺ -type. However, in another example, the first conductivity type may be n-type or n ⁺ type, and the second conductivity type may be p-type or p ⁺ -type.

  The vertical MISFET 300 is provided on the n-type semiconductor substrate 350 (see FIG. 6C). A source electrode 344 is provided on part of the surface of the n-type semiconductor substrate 350. In addition, an insulator layer 342 serving as a gate insulating film is provided on another part of the surface of the n-type semiconductor substrate 350. A gate electrode 340 is provided on the surface side of the gate insulating film (insulator layer) 342. The source electrode 344 may be provided so as to sandwich or surround the gate insulating film 342 and the gate electrode 340.

  The gate insulating film 342 is a stacked film of a first insulating film 351 and a second insulating film 352, and the first insulating film 351 is provided on the n-type semiconductor substrate 350 side.

  The first insulating film 351 is an insulating film containing a gallium oxide crystal. In particular, the first insulating film 351 has an gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride, and the a-axis lattice constant is 0. An oxide film having at least one of hexagonal crystal and cubic crystal of 28 nm or more and 0.34 nm or less, or ε-structure gallium oxide or γ-structure gallium oxide, or ε-structure gallium oxide, and A film made of a combination of γ-structure gallium oxide is preferable.

  The crystal plane of the first insulating film 351 is aligned with the crystal plane of the n-type semiconductor substrate 350. For example, the first insulating film 351 may be formed so that the crystal plane of gallium oxide that is a hexagonal single crystal is aligned on the crystal plane of the Miller index [0001] of gallium nitride of the n-type semiconductor substrate 350.

  The thickness of the first insulating film 351 is preferably 10 nm or less. This is because when the thickness is larger than 10 nm, lattice mismatch tends to occur in the formed gallium oxide, and trap sites increase. Furthermore, the thickness of the first insulating film 351 is more preferably 5 nm or less. Thus, it is preferable to reduce the thickness of the first insulating film 351 as much as possible. On the other hand, the thickness of the first insulating film 351 needs to be greater than or equal to a monoatomic layer of gallium oxide in order to ensure that a gallium oxide crystal is formed on the n-type semiconductor substrate 350. is there. In addition, when the thickness of the first insulating film 351 is set to be equal to or greater than that of the gallium oxide diatomic layer, there is an effect that the generation of defect portions is not reduced.

  When the first insulating film 351 has a gallium oxide crystal in which the gallium nitride and the in-plane lattice constant a are matched, the gallium oxide crystal in which the gallium nitride in the first insulating film 351 and the in-plane lattice constant a are matched is used. The volume ratio occupied by is preferably 95% or more. In the case where the first insulating film 351 includes a hexagonal crystal or a cubic gallium oxide crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, the first insulating film 351. The ratio of the volume occupied by at least one of hexagonal and cubic crystals of gallium oxide having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less is preferably 95% or more. With this structure, generation of trap sites in the gate insulating film 342 formed between the n-type semiconductor substrate 350 that is a gallium nitride based semiconductor layer and the gate electrode 105 is sufficiently suppressed.

  In the case where the first insulating film 351 includes a combination of ε-structure gallium oxide and γ-structure gallium oxide, the ratio of the ε-structure gallium oxide to the volume of the first insulating film 351 is 70. The ratio of γ structure gallium oxide is 10% to 30%, and the total ratio of ε structure gallium oxide and γ structure gallium oxide is 95% to 100%. The following is preferable. For example, the ε-structure gallium oxide accounts for 80% of the volume of the first insulating film 103, and the γ-structure gallium oxide occupies the remaining 20% of the first insulating film 351. Also good. In the volume of the first insulating film 351, the proportion of gallium oxide having an ε structure is 78%, and the proportion of gallium oxide having a γ structure is 18%. The proportion of the total of ε-structure gallium oxide and γ-structure gallium oxide may be 96%, so that the proportion other than gallium oxide is 4%. With this structure, generation of trap sites in the gate insulating film 342 formed between the n-type semiconductor substrate 350 that is a gallium nitride based semiconductor layer and the gate electrode 105 is sufficiently suppressed.

The second insulating film 352 of the gate insulating film 342 is provided on the first insulating film 351 and is made of an element group including Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and a rare earth element. It is formed from an oxide, nitride, or oxynitride of at least one selected element. Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si _{2 3} N ₄ , SiON and the like can be mentioned.
The thickness of the second insulating film is preferably 3 nm to 100 nm, and more preferably 5 nm to 50 nm. When the thickness is 3 nm or less, a tunnel current is likely to be generated, or a gate breakdown voltage failure is likely to occur. Above 100 nm, FET characteristics such as current drive capability (Gm) tend to be insufficient.

A drain electrode 346 is provided on the back surface of the n-type semiconductor substrate 350. An n ⁺ type semiconductor layer 332 is provided on the back surface side of the n type semiconductor substrate 350 and in a region in contact with the drain electrode 346. The n ⁺ type semiconductor layer 332 may have a predetermined thickness. The n ⁺ type semiconductor layer 332 has an impurity concentration higher than the impurity concentration in the n type semiconductor substrate 350 in order to reduce the contact resistance with the drain electrode 346.

  The vertical MISFET 300 includes an n-type drift layer 330 as a second conductivity type drift layer, and a current blocking layer 320 provided on the surface side of the n-type drift layer 330. The n-type semiconductor substrate 350 further includes a p-type semiconductor layer 310 as a first conductivity type semiconductor layer provided on the surface side of the current blocking layer 320. The p-type semiconductor layer 310 is GaN.

The current blocking layer 320 in this example is p-type and has a higher impurity concentration than the p-type semiconductor layer 310. The p-type semiconductor layer 310 in this example is an epitaxial layer provided in contact with the current blocking layer 320. When the current blocking layer 320 is a p ⁺ type semiconductor layer as in this example, the current blocking layer 320 and the p type semiconductor layer 310 are electrically connected.

  The current blocking layer 320 is located between the end on the back surface side of the n-type source side region 312 and the n-type drift layer 330, and extends from the source electrode 344 to the end portion on the back surface side of the n-type source side region 312. The current flowing through the drain electrode 346 is cut off. In another example, the current blocking layer 320 may be an insulating layer. However, when the current blocking layer 320 is not an insulating layer but a semiconductor region, if a large current flows from the drain electrode to the source electrode, the current blocking layer 320 may flow current.

  The p-type semiconductor layer 310 has an n-type source-side region 312 and an n-type drain-side region 314 as a second conductivity type source-side region and drain-side region. The n-type source side region 312 and the n-type drain side region 314 are provided apart from each other on the surface of the p-type semiconductor layer 310.

  The n-type source side region 312 and the n-type drain side region 314 are formed to the same depth in the p-type semiconductor layer 310. In forming the n-type source side region 312 and the n-type drain side region 314, the impurity doping process is performed only once. In the single impurity doping process, the channel length 343 is defined by the distance between the n-type source side region 312 and the n-type drain side region 314. Note that the channel length 343 is a partial region of the p-type semiconductor layer 310 on the back surface side of the gate insulating film.

  On the further back surface side of the current blocking layer 320 on the back surface side of the p-type semiconductor layer 310, the n-type drift layer 330 is in contact with the end portion on the back surface side of the n-type drain side region 314. On the other hand, due to the presence of the current blocking layer 320, the n-type drift layer 330 is not in contact with the back-side end of the n-type source side region 312.

  Depletion layer between the current blocking layer 320 and the n-type drift layer 330 and depletion between the current blocking layer 320 and the n-type drain side region 314 under an off condition in which the drain electrode 346 and the gate electrode 340 are set to a low potential. The layer expands. The depletion layer reaches the entirety between the n-type drift layer 330 and the end portion on the back surface side of the n-type drain side region 314. Thereby, the current from the drain electrode 346 to the source electrode 344 in the off-state is surely cut off.

The vertical MISFET 300 further includes an n ⁺ -type contact layer 318 as a second conductivity type contact layer. The n ⁺ type contact layer 318 is provided to reduce the contact resistance between the n type semiconductor substrate 350 and the source electrode 344. For the same purpose, a p ⁺ -type contact layer 316 is provided on the back side of the source electrode 344.

At least a part of the n ⁺ -type contact layer 318 is formed in the n-type source side region 312. The n ⁺ -type contact layer 318 has a higher impurity concentration than both the n-type drain side region 314 and the n-type source side region 312.

In this example, the distance L2 from the n-type drain side region 314 to the n ⁺ -type contact layer 318 is larger than the distance L1 from the n-type drain side region 314 to the n-type source side region 312. That is, L1 <L2.

The distance L2 may be the shortest distance from the n-type drain side region 314 to the n ⁺ -type contact layer 318 on the surface of the n-type semiconductor substrate 350. Or, the distance L2 is at a depth position of the rear end portion of the ^{n +} -type contact layer 318 may be the shortest distance from the n-type drain-side region 314 to ^{n +} -type contact layer 318.

The distance L1 may be the shortest distance from the n-type drain side region 314 to the n-type source side region 312 on the surface of the n-type semiconductor substrate 350. Alternatively, the distance L1 may be the shortest distance from the n-type drain side region 314 to the n-type source side region 312 in the depth position of the back surface side end of the n ⁺ -type contact layer 318.

In the vertical MISFET 300 of this example, the n ⁺ -type contact layer 318 is not involved in defining the channel length at all. The channel length is defined only by the distance between the n-type source side region 312 and the n-type drain side region 314. Therefore, in the vertical MISFET 300 of this example, the channel length can be precisely controlled. That is, the vertical MISFET 300 of this example is excellent in controllability of the channel length.

In another example, the distance L2 from the n-type drain side region 314 to the n ⁺ -type contact layer 318 may be greater than or equal to the distance L1 from the n-type drain side region 314 to the n-type source side region 312. As is obvious from the above description, in another example, L1 = L2 may be set. Again, the n ⁺ -type contact layer 318 is not involved at all in defining the channel length. Note that the accuracy in manufacturing the n ⁺ -type contact layer 318 is required to be higher when L1 = L2 than when L1 <L2. Therefore, manufacture is easier in the case of L1 <L2.

In yet another example, the n ⁺ -type contact layer 318 may be formed to extend from the n-type source side region 312 in the opposite direction to the n-type drain side region 314. That is, the source electrode 344 may mainly be in contact with the n ⁺ -type contact layer 318 instead of the p ⁺ -type contact layer 316. Note that a contact layer having a higher impurity concentration than the n-type drain side region 314 is not formed on the surface of the n-type drain side region 314.

Next, a method for manufacturing the vertical MISFET 300 will be described.
As described above, the n-type semiconductor substrate 350 is GaN. The p-type impurity may be magnesium (Mg), calcium (Ca) or beryllium (Be), and the n-type impurity may be silicon (Si) or oxygen (O). 4 to 6, an example in which the n-type semiconductor substrate 350 is GaN will be described.

  FIG. 4A is a diagram illustrating a step of forming the current blocking layer 320. First, a patterned photoresist layer 360 is formed on the surface of a GaN n-type semiconductor substrate 350. The photoresist layer 360 may have a linear shape extending in a direction perpendicular to the paper surface, or a rectangular island shape.

  Next, p-type impurities are doped from the surface side of the n-type semiconductor substrate 350 using the photoresist layer 360 as a mask. A region other than the region where the photoresist layer 360 is provided is doped with a p-type impurity. The p-type impurity forms a box profile having a constant impurity concentration within a predetermined range of depth.

The p-type impurity may be Mg. The total dose may be 1 × 10 ¹⁴ or more and 5 × 10 ¹⁵ cm ⁻² or less. The p-type impurity may be doped by a depth of 0.5 μm from the front surface to the back surface of the n-type semiconductor substrate 350. Note that the thickness and impurity concentration of the n-type semiconductor substrate 350 may be appropriately determined according to the withstand voltage.

After doping the p-type impurity, annealing is performed at 1000 ° C. or higher and 1500 ° C. or lower. As a result, the current blocking layer 320 is formed. The current blocking layer 320 is a p ⁺ type semiconductor layer having a higher p type impurity concentration than a p type semiconductor layer 310 described later.

FIG. 4B is a diagram illustrating a step of forming the p-type semiconductor layer 310. After the step of forming the current blocking layer 320, the photoresist layer 360 is removed by ashing or stripping solution, and then the p-type semiconductor layer 310 is formed on the current blocking layer 320. In this example, in the step of forming the p-type semiconductor layer 310, the p-type semiconductor layer 10 is formed on the current blocking layer 320 by epitaxial growth. The epitaxially grown p-type semiconductor layer 310 may have a thickness of not less than 0.5 μm and not more than 2.0 μm, and may include a p-type impurity of 1 × 10 ¹⁷ cm ⁻³ .

  FIG. 4C is a diagram illustrating a step of simultaneously forming the n-type source side region 312 and the n-type drain side region 314. After the step of forming the p-type semiconductor layer 310, the n-type source side region 312 and the n-type drain side region 314 are formed simultaneously. In this example, first, a patterned photoresist layer 362 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layers 362 are provided so as to be separated from each other in a cross-sectional view. Photoresist layer 362 may have a stripe shape, a square cell shape, or a hexagonal cell shape when viewed in plan.

Next, n-type impurities are doped from the surface side of the n-type semiconductor substrate 350 using the photoresist layer 362 as a mask. Regions other than the region where the photoresist layer 362 is provided are doped with n-type impurities. The n-type impurity may constitute a box profile. The n-type impurity may be Si or O. The total dose may be 5 × 10 ¹² or more and 1 × 10 ¹⁴ cm ⁻² or less.

  After doping with n-type impurities, annealing is performed. As a result, the n-type source side region 312 and the n-type drain side region 314 are formed simultaneously. The formed n-type source side region 312 and n-type drain side region 314 are separated from each other on the surface of the p-type semiconductor layer 310. Thereby, the channel length 343 is defined. The channel length 343 may be 0.5 μm or more and 2.0 μm or less.

  The doped n-type impurity diffuses in the p-type semiconductor layer 310 during annealing. After the annealing, the back side edge of the n-type source side region 312 reaches the current blocking layer 320. Further, the back side end of the n-type drain side region 314 reaches the n-type drift layer 330.

FIG. 5A is a diagram illustrating a step of forming the p ⁺ -type contact layer 316. After the step of simultaneously forming the n-type source side region 312 and the n-type drain side region 314, the p ⁺ -type contact layer 316 is formed. First, a patterned photoresist layer 364 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layer 364 of this example is formed so as to completely cover the n-type drain side region 314 and partially cover the n-type source side region 312 in a cross-sectional view. The photoresist layer 364 may have a stripe shape, a square cell shape or a hexagonal cell shape when viewed in plan.

Next, p-type impurities are doped from the surface side of the n-type semiconductor substrate 350 using the photoresist layer 364 as a mask. The p-type impurity doped at this stage has a higher impurity concentration than the p-type semiconductor layer 310. Thereby, the region other than the region where the photoresist layer 364 is provided becomes p ⁺ type. After doping the p-type impurity, annealing is performed. Thereby, a p ⁺ -type contact layer 316 is formed.

FIG. 5B is a diagram illustrating a step of forming the n ⁺ -type contact layer 318. After the step of forming the p ⁺ type contact layer 316, the n ⁺ type contact layer 318 is formed. First, a patterned photoresist layer 366 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layer 366 has an opening at least in the n-type source side region 312. The photoresist layer 366 of this example may have a stripe shape, a square cell shape, or a hexagonal cell shape when seen in a plan view.

  However, the opening end portion 367 on the n-type drain side region 314 side in the opening of the photoresist layer 366 is on the n-type drain side than the surface-side end portion 313 on the n-type drain side region 314 side of the n-type source side region 312. It is not provided on the region 314 side. Of the openings of the photoresist layer 366, the opening end 367 on the n-type drain side region 314 side may coincide with the surface-side end 313 on the n-type drain side region 314 side of the n-type source side region 312.

Next, n-type impurities are doped from the surface side of the n-type semiconductor substrate 350 using the photoresist layer 366 as a mask. Regions other than the region where the photoresist layer 366 is provided are doped with n-type impurities. The n-type impurity may constitute a box profile having a depth of 0.2 μm. The n-type impurity may be Si or O. The total dose may be 5 × 10 ¹⁵ cm ⁻² .

After doping with n-type impurities, annealing is performed. Thus, at least a part of the n ⁺ -type contact layer 318 having a higher impurity concentration than both the n-type drain side region 314 and the n-type source side region 312 is formed in the n-type source side region 312. The distance L2 from the n-type drain side region 314 to the n ⁺ -type contact layer 318 is set to be equal to or longer than the distance L1 from the n-type drain side region 314 to the n-type source side region 312.

As a modification, the annealing at the stage from FIG. 4A to FIG. 5B may be performed collectively when the annealing for forming the n ⁺ -type contact layer 318 in FIG. 5B is performed. . Thereby, manufacturing process time can be shortened.

Next, as shown in FIG. 5C, a first insulating film 351 and a second insulating film 352 are sequentially formed on the surface of the n-type semiconductor substrate 350, and the first insulating film 351 and the second insulating film 352 are formed. A gate insulating film 342 made of the film 352 is formed.
Here, the first insulating film 351 is an insulating film containing a gallium oxide crystal, and in particular, an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched with the above-described gallium nitride, or an ε structure. An insulating film containing gallium oxide and / or gallium oxide having a γ structure is preferable.
The first insulating film 351 is an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride, or a trap site suitable as a gate insulating film by using an ε structure or a γ structure gallium oxide. Thus, the gate insulating film 342 in a favorable interface state with a small amount can be formed.

The first method for forming the first insulating film 351 is to form the surface of the n-type semiconductor substrate 350 from the group consisting of sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. It is a method of oxidizing with at least one selected chemical solution.
Examples of this oxidation method include SC1, SC2, SPM, buffered hydrofluoric acid solution and the like which are usually used for cleaning.
According to the first method, the crystal plane of the first insulating film 351 is aligned with the crystal plane of the n-type semiconductor substrate 350 surface. Therefore, the first method is particularly preferable for forming a high-quality gate insulating film 342 with few traps.

In the first method, light irradiation may be used in combination. For example, the n-type semiconductor substrate 350 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or a wavelength of 190 nm or more and less than 280 nm is formed on the surface of the n-type semiconductor substrate 350. The first insulating film 351 may be formed by oxidizing the surface of the n-type semiconductor substrate 350 by irradiating far-distance external light (DUV).
In addition, the first method is characterized in that the heat load is less than that in the thermal oxidation treatment because it is a treatment at 280 ° C. or less even at room temperature or even when heat treatment is applied. When a large heat load is applied, problems such as changes in the profile of the implanted impurity and generation of stress tend to occur.

  The second method for forming the first insulating film 351 is to oxidize the surface of the n-type semiconductor substrate 350 by plasma oxidation in an atmosphere of 500 ° C. or lower, and the gallium nitride and the in-plane lattice constant a are matched. An oxide film having a gallium oxide crystal, an oxide film having at least one of hexagonal crystal and cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an oxide having an ε structure This is a method for forming gallium oxide having a gallium and / or γ structure. In addition, the surface of the n-type semiconductor substrate 350 is oxidized by ozone oxidation in an atmosphere of 500 ° C. or lower, and an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with the gallium nitride, an a-axis Forming an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide having a lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide. May be.

  A third method for forming the first insulating film 351 is to form gallium nitride and an in-plane lattice constant a on the surface of the n-type semiconductor substrate 350 by an electron beam evaporation method and / or MBE method in an atmosphere of 700 ° C. or lower. Oxide film having aligned gallium oxide crystal, oxide film having at least one of hexagonal crystal and cubic crystal of a-axis lattice constant of 0.28 nm to 0.34 nm, or ε structure The gallium oxide and / or the γ-structure gallium oxide is deposited. Further, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by a CVD method in an atmosphere of 870 ° C. or lower on the surface of the n-type semiconductor substrate 350, and the a-axis lattice constant is 0. Alternatively, an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide of 28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide may be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and in-plane lattice constant a are matched by an HVPE method in an atmosphere of 700 ° C. or lower on the surface of n-type semiconductor substrate 350, and the a-axis lattice constant is 0. Alternatively, an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide of 28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide may be deposited. Further, an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride by an ALD method in an atmosphere of 500 ° C. or lower on the surface of the n-type semiconductor substrate 350, and the lattice constant of the a axis is 0. An oxide film having at least one of hexagonal crystal and cubic crystal of 28 nm or more and 0.34 nm or less, or an ε-structure gallium oxide and / or a γ-structure gallium oxide may be deposited. Further, gallium oxide is deposited on the surface of the n-type semiconductor substrate 350 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to have a gallium oxide crystal in which the gallium nitride and the in-plane lattice constant a are matched. An oxide film, an oxide film having at least one gallium oxide crystal of hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an gallium oxide having an ε structure and / or a γ structure Gallium oxide may be deposited.

  A fourth method of forming the first insulating film 351 is to form a gallium oxide crystal on the surface of the n-type semiconductor substrate 350 by a heat treatment of 500 ° C. or more and 870 ° C. or less, and then etching the gallium oxide. The thickness of the first insulating film is 10 nm or less.

The second insulating film 352 includes an oxide, a nitride, or an acid of at least one element selected from the group consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and a rare earth element. Nitride is formed by sputtering, CVD, ALD, or the like. Specific materials of the second insulating film 352 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si ₃ N ₄ , SiON, and the like can be given. For example, when Al ₂ O ₃ is formed as the second insulating film by a sputtering method, Al can be used as a target, and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. Alternatively, it can be formed by an ALD method using trimethylaluminum.

Next, as illustrated in FIG. 6A, a gate electrode 340 is provided on the surface side of the gate insulating film 342.
The gate electrode 340 is formed by depositing a gate material constituting the gate electrode on the entire surface of the gate insulating film 342, forming a photoresist layer having a desired pattern by lithography, and etching the gate material using the photoresist layer as an etching mask. To form. As a deposition method of the gate electrode material, there are a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, a CVD method, and the like. This method is characterized by high gate electrode processing accuracy.

Next, as illustrated in FIG. 6B, the source electrode 344 is provided in contact with the p ⁺ type contact layer 316 and the n ⁺ type contact layer 318.
Thereafter, as shown in FIG. 6C, an n ⁺ -type semiconductor layer 332 is formed by doping an n-type impurity on the back surface of the n-type semiconductor substrate 350, and then a drain is formed on the back surface of the n ⁺ -type semiconductor layer 332. An electrode 346 is provided. The gate electrode 340, the source electrode 344, and the drain electrode 346 are at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. It may be formed from. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, carbonitride including at least one selected from these groups may be used.
Thus, the vertical MISFET 300 is completed.

  The MISFET 300 according to the manufacturing method of the third embodiment is a vertical MISFET using a gallium nitride based semiconductor as a semiconductor layer, and has a gate insulating film in a favorable interface state with few trap sites. For this reason, the MISFET 300 according to the manufacturing method of the third embodiment is a MISFET having excellent frequency characteristics and less hysteresis.

In the first to third embodiments, the gate insulating film of the MISFET has an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched with the gallium nitride, and the lattice constant of the a axis is 0.28 nm or more. A case where an oxide film having at least one of hexagonal crystal and cubic crystal of gallium oxide of 34 nm or less, or an gallium oxide film having an ε structure and / or a γ structure is shown. And an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched, a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, and a cubic gallium oxide crystal of at least one of cubic crystals. The preferred application of the oxide film or the gallium oxide film having the ε structure and / or the γ structure is not limited to this.
For example, even when used for an insulating film of a MIS capacitor, since there are few trap sites, it is possible to provide a MIS capacitor with less hysteresis and excellent frequency characteristics.
In a high-frequency device using a gallium nitride semiconductor, an oxide film having a crystal in which the in-plane lattice constant a is matched with the gallium nitride as a layer in direct contact with the gallium nitride semiconductor surface; It is also effective to use an oxide film having at least one of hexagonal crystal and cubic crystal of 28 nm or more and 0.34 nm or less, or a passivation film containing ε-structure gallium oxide and / or γ-structure gallium oxide. It is. In this case, there is an effect that current collapse in the high-frequency device can be sufficiently suppressed. Here, the passivation film is an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched with gallium nitride, a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, and a cubic crystal. Alternatively, the structure may be a multilayer film including an oxide film having one gallium oxide crystal or a film having ε-structure gallium oxide and / or γ-structure gallium oxide.

<Embodiment 4>
In the fourth embodiment, a DMOS (Double-Diffused MOSFET) 400 will be described with reference to FIGS. 14 and 15.

  FIG. 14 and FIG. 15 describe the outline of a process for manufacturing a power MOSFET having a planar type DMOS structure using sequential cross-sectional structures. FIG. 15D shows the cross-sectional structure of the manufactured DMOS (400) more specifically. The manufacturing process will be described with reference to FIGS. 14A to 14D and 15A to 15D.

First, an n-type GaN epitaxial layer (n ^- epi layer) 403 is grown on a high-concentration n-type GaN substrate (n ⁺ substrate) 402 using the n ⁺ substrate 402 as a seed crystal (FIG. 14A). reference). Here, the crystal structure of the n ^- epi layer 403 is a wurtzite structure.

  Thereafter, a resist pattern is formed so that a region of a gate electrode to be formed later is masked, and ion implantation is performed on the substrate surface. Then, the implanted p-type impurity is activated by heat-treating the substrate after ion implantation. At that time, a slight diffusion occurs simultaneously with the activation. By this step, a p-type well 404 into which a p-type impurity is implanted is formed in a portion other than the region where the gate is formed (see FIG. 14B).

Next, in order to form the n ⁺ diffusion layer 405 in the p-type well 404, a resist mask is formed, and n-type impurities are implanted in a high concentration and shallow condition in a range limited by the opening. I do. At this time, a resist pattern is formed so that a gate electrode region to be formed later is masked.
After this implantation, heat treatment is performed to activate the implanted n-type impurity. With this heat treatment, slight lateral diffusion occurs. By this step, an n ⁺ diffusion layer 405 is formed (see FIG. 14C).

Next, as shown in FIG. 14D, a gallium oxide layer 406a is formed as a first insulating film on the surface of the sample.
Here, the gallium oxide layer 406a is an insulating film containing a gallium oxide crystal, and in particular, an oxide having a gallium oxide crystal whose in-plane lattice constant a is matched with the above-described n ^- epi layer 403 made of gallium nitride. A film, an insulating film having at least one of hexagonal and cubic crystals having an a-axis lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide It is preferable that the insulating film have.
The gallium oxide layer 406a is an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched with the n ^- epi layer 403, or a hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. By using an insulating film containing at least one of gallium oxide or a gallium oxide having an ε structure or a γ structure, a trap film suitable for a gate insulating film can be used as a laminated film with a second insulating film 407a described later. The gate insulating layer 421a having a small favorable interface state can be formed.

In the first method of forming the gallium oxide layer 406a, the surface including the exposed surface of the n ^- epi layer 403 is made of sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, or potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
Examples of this oxidation method include SC1, SC2, SPM, buffered hydrofluoric acid solution and the like which are usually used for cleaning.
According to this first method, the crystal plane of the gallium oxide layer 406a is aligned with the crystal plane of the n ^- epi layer 403 surface. Therefore, the first method is particularly preferable for forming a high-quality gate insulator layer 421a with few traps.

In the first method, light irradiation may be used in combination. For example, the surface including the n ^- epi layer 403 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or hyperopia with a wavelength of 190 nm or more and less than 280 nm is immersed on the surface. By irradiating light (DUV), the surface including the exposed surface of the n ⁻ epi layer 403 may be oxidized to form the gallium oxide layer 406a.
Here, the first method is characterized in that the thermal load is less than that of the thermal oxidation treatment because it is a treatment at 280 ° C. or less even at room temperature or even when heat treatment is applied. When a large heat load is applied, problems such as changes in the profile of the implanted impurity and generation of stress tend to occur.

A second method of forming a gallium oxide layer 406a is, n ^- the surface including the exposed surface of the epitaxial layer 403, is oxidized by plasma oxidation process in the following atmosphere 500 ° C., n ^- epitaxial layer 403 and an in-plane lattice An oxide film having a crystal of gallium oxide in which the constant a is matched, an insulating film having at least one of hexagonal crystal and cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, or ε This is a method of forming gallium oxide having a structure and / or gallium oxide having a γ structure. Further, the surface of the n ⁻ epi layer 403 including the exposed surface is oxidized by ozone oxidation in an atmosphere of 500 ° C. or lower, and the gallium oxide crystal in which the n ⁻ epi layer 403 and the in-plane lattice constant a are matched. An oxide film having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film containing at least one gallium oxide of cubic crystal, or ε-structure gallium oxide and / or γ-structure Gallium oxide may be formed.

A third method of forming a gallium oxide layer 406a is, n ^- on the surface including the exposed surface of the epitaxial layer 403, n by electron beam evaporation and / or MBE method in the following atmosphere 700 ° C. ^- epi layer 403 and the surface An oxide film having a crystal of gallium oxide in which the inner lattice constant a is matched, an insulating film having at least one of hexagonal crystal and cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, Alternatively, gallium oxide having an ε structure and / or gallium oxide having a γ structure is deposited.
In addition, an oxide film having a gallium oxide crystal whose in-plane lattice constant a is matched with the p ⁻ epi layer 403 by a CVD method in an atmosphere of 870 ° C. or lower on the surface including the exposed surface of the n ⁻ epi layer 403, a An insulating film containing at least one of hexagonal crystal and cubic crystal gallium oxide having an axial lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide is deposited. Also good.
Further, n ^- on the surface including the exposed surface of the epitaxial layer 403, n by the HVPE method in the following atmosphere 700 ° C. ^- oxide film having the gallium oxide epilayer 403 and the in-plane lattice constant a is aligned crystals, a An insulating film containing at least one of hexagonal crystal and cubic crystal gallium oxide having an axial lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide is deposited. Also good.
Further, n ^- on the surface including the exposed surface of the epitaxial layer 403, n by ALD in the following atmosphere 500 ° C. ^- oxide film having a crystal of gallium oxide epilayer 403 and the in-plane lattice constant a are aligned, a An insulating film having at least one of hexagonal crystal and cubic crystal having an axial lattice constant of 0.28 nm to 0.34 nm, or an ε-structure gallium oxide and / or a γ-structure gallium oxide may be deposited. Good.
Further, gallium oxide is deposited on the surface including the exposed surface of the n ⁻ epi layer 403 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to match the n ⁻ epi layer 403 and the in-plane lattice constant a. An oxide film having a crystal of gallium oxide, an insulating film having at least one of hexagonal crystal and cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm, gallium oxide having an ε structure, and Alternatively, gallium oxide having a γ structure may be deposited.

The fourth method for forming the gallium oxide layer 406a is to form a gallium oxide crystal on the surface including the exposed surface of the n ^- epi layer 403 by a heat treatment at 500 ° C. or higher and 870 ° C. or lower, and then perform etching. In this method, the gallium oxide layer 406a is formed with a gallium oxide thickness of 10 nm or less.

  Thereafter, as shown in FIG. 15A, a second insulating film 407a is formed on the gallium oxide layer 406a, and a gate insulator layer 421a including the gallium oxide layer 406a and the second insulating film 407a is formed. .

The second insulating film 407a is formed of an oxide, nitride, or acid of at least one element selected from the group consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and a rare earth element. Nitride is formed by sputtering, CVD, ALD, or the like. Specific materials of the second insulating film 407a include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , Si ₃ N ₄ , SiON and the like can be mentioned. For example, in the case where Al ₂ O ₃ is formed as the second insulating film 407a by a sputtering method, Al can be used as a target and DC sputtering can be performed in an oxygen gas, or Al ₂ O ₃ can be used as a target. RF sputtering can also be performed. Alternatively, it can be formed by an ALD method using trimethylaluminum.

  Next, as shown in FIG. 15B, a metal film 408a is formed on the surface of the second insulating film 407a. Here, examples of the metal film 408a include at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, and Zn. The form may be a single layer film or a laminated film. In addition to these metals, an alloy including at least one selected from these groups, and a compound such as nitride, carbide, and carbonitride including at least one selected from these groups may be used. Further, as the metal film 408a, polysilicon can be used, and a stacked film of polysilicon and the above metal can also be used. Examples of a method for forming the metal film 408a include a sputtering method and a vapor deposition method.

  Next, using the resist as a mask, the metal film 408a, the second insulating film 407a, and the gallium oxide layer 406a are dry-etched to form the first insulating film 406, the second insulating film 407, and the gate electrode 408. A gate shape of the DMOS is formed (see FIG. 15C).

Next, a PSG film (low-temperature oxide film containing 3% to 5% phosphorus atoms) is formed on the entire surface of the substrate by using a low pressure CVD method, and then a metal contact connected to the n ⁺ diffusion layer 405 is formed. An insulating film 411 made of a PSG film having an opening for forming the opening is formed.
Finally, a metal contact made of a metal, for example, an alloy of titanium and aluminum, is formed in the opening to form an emitter electrode 412. On the other hand, a back electrode made of a multilayer film made of nickel, titanium, silver, gold or the like that obtains a low-resistance ohmic contact with the n ⁺ substrate is formed on the back surface of the n ⁺ substrate 402 to form a collector electrode 401 (FIG. 15D )reference).
Through the above steps, the DMOS (400) is manufactured.

  The DMOS (400) according to the manufacturing method of the fourth embodiment is a MOSFET having a DMOS structure using a gallium nitride semiconductor as a semiconductor layer, and has a gate insulating film having a good interface state with few trap sites. Features. For this reason, the DMOS (400) according to the manufacturing method of the fourth embodiment is a power MOSFET having excellent frequency characteristics and switching characteristics.

  In Example 1, the MIS capacitor (MOS capacitor) 200 shown in FIG. 7 was produced, and the electrical characteristics of the MIS capacitor were evaluated.

The MIS capacitor of Example 1 includes a free-standing substrate 201, an n ⁻ GaN epitaxial layer 202 as a semiconductor layer, an insulating layer 203 including a first insulating film 204 and a second insulating film 205, and electrodes 206 and 207.

  The manufacturing method of the MIS capacitor of Example 1 is as follows.

As a semiconductor substrate and a semiconductor layer, a film thickness of 5 μm is formed on a free-standing substrate 201 made of n ^- GaN having a thickness of 270 μm by a metal organic chemical vapor deposition (MOCVD) method. The n ^- GaN epitaxial layer 202 having a carrier concentration of 1 × 10 ¹⁶ cm ⁻³ was prepared. Here, the crystal plane of the surface of the n ⁻ GaN epitaxial layer 202 is (0001).

The surface of the n ^- GaN epitaxial layer 202 was washed with an isopropyl alcohol and acetone solution at room temperature (23 ° C.) and then surface-treated with a dilute hydrofluoric acid solution having a concentration of 3% by volume.
Subsequently, a gallium oxide crystal (Ga ₂ O ₃ ) is generated on the surface of the n ^- GaN epitaxial layer 202 using SPM made of H ₂ SO ₄ —H ₂ O ₂ —H ₂ O as an oxide film forming method. The gallium oxide crystal layer was used as the first insulating film 204. Here, the n ^- GaN epitaxial layer 202 was immersed in an SPM solution and processed at a temperature of self-heating during the production of sulfuric acid / hydrogen peroxide. The volume ratio of H ₂ SO ₄ and H ₂ O ₂ is 2: 1.

The surface state of the n ^- GaN epitaxial layer 202 surface-treated with SPM was measured by XPS (X-ray Photoelectron Spectroscopy) method. FIG. 8 shows an XPS Ga _3d spectrum by the XPS method. The measured data is indicated by □, and the simulation data is indicated by a solid line.
Data by simulation (thin solid line) that combines a Ga-N bond component having a peak at a bond energy of 19.8 eV (thick solid line) and a Ga-O bond component having a peak at a bond energy of 20.3 eV (thick solid line). Is in good agreement with the measured data. Thus, it was confirmed that gallium oxide was generated on the surface of the n ⁻ GaN epitaxial layer 202 by performing surface treatment of the surface of the n ⁻ GaN epitaxial layer 202 with SPM.

Further, a cross-sectional analysis by TEM (Transmission Electron Microscope) was performed, and the structure of the crystal of gallium oxide formed on the surface of the n ^- GaN epitaxial layer 202 was examined. 9A and 9B are a cross-sectional analysis diagram on the Miller index [1-100] plane and a cross-sectional analysis diagram on the Miller index [11-20] plane, respectively. As a result, the film thickness of the produced gallium oxide was 1.7 nm, and it was confirmed that the crystal structure of this gallium oxide was a crystal of ε structure and γ structure.
Further, STEM (Scanning Transmission Electron Microscopy) confirmed that the gallium oxide is composed of crystals having an ε structure of 80% and a γ structure of 20% by volume.
In addition, it was confirmed that the crystal planes of the ε structure and the γ structure are aligned with the crystal plane of the n ⁻ GaN epitaxial layer 202.

Subsequently, on the surface of the first insulating film 204, a 10 nm-thick aluminum oxide (Al ₂ film) is grown at a growth temperature of 300 ° C. by ALD using trimethylaluminum (TMA) as a precursor and water vapor as an oxidizing gas. O ₃ ) was generated to form the second insulating film 205.
Specifically, nitrogen gas (N ₂ gas) is purged, and TMA charging, N ₂ gas purging, 20 ° C. water gas charging, and N ₂ gas purging are performed in one cycle until the film thickness reaches 10 nm. Repeated. Here, TMA and water gas were pulsed.
Then, after forming the Al ₂ O ₃ film, heat treatment was performed at 300 ° C. in a nitrogen atmosphere gas.

Subsequently, a platinum (Pt) film having a thickness of 100 nm was formed on the surface of the second insulating film 205 by an electron beam evaporation method and a photolithography process, so that the electrode 206 was formed.
Finally, a titanium (Ti) film having a thickness of 20 nm and a platinum (Pt) film having a thickness of 100 nm are successively formed on the front surface (rear surface) of the n ^- GaN free-standing substrate 201 to form an ohmic contact electrode 207. Formed.
Through the above steps, the MIS capacitor 200 shown in FIG. 7 was produced.

FIG. 10 shows the CV characteristics of the manufactured MIS capacitor 200.
Measurement data when a forward voltage is applied between the electrodes 206 and 207 is indicated by a circle, and measurement data when a voltage is applied reversely is indicated by a square.
It was confirmed that the hysteresis in the flat band voltage in the forward and reverse cases was negligibly small. This is because there are very few trap sites due to defects in the first insulating film 204 made of gallium oxide having the ε structure and the γ structure and the insulating layer 203 made of the second insulating film 205 made of aluminum oxide. I mean.

Further, an ideal curve indicated by a solid line obtained from the Fermi level of the n ^- GaN epitaxial layer 202, the work function of the electrode 206 by Pt, the thickness of the insulating film 203 and the value of the dielectric constant, and measurements indicated by ◯ and □. The data matched very well.
In Non-Patent Document 1, since the interface between the n ^- GaN epitaxial layer 202 and the insulator layer 203 is not manufactured with particular care, the frequency dispersion of the CV characteristic is reported. Suggests that the condition is not good.

  As described above, the MIS capacitor 200 including the first insulating film 204 made of gallium oxide having the ε structure and the γ structure and the second insulating film 205 made of aluminum oxide as the semiconductor layer is made of gallium nitride. It was confirmed that it has good interfacial properties with few sites.

  As described above, the insulating layer 203 including the first insulating film formed of gallium oxide having the ε structure and the γ structure formed on the gallium nitride semiconductor layer and the second insulating film formed of aluminum oxide has an interface with few trap sites. Although an insulating layer with good characteristics is formed, this is not limited to the MIS capacitor. When the first insulating film made of gallium oxide having the ε structure and the γ structure and the insulating layer 203 made of the second insulating film are used as the gate insulating film of the MISFET (MOSFET), the gate insulating film has interface characteristics with few trap sites. As a result, it is possible to provide a good MISFET (MOSFET) having excellent frequency characteristics and low hysteresis.

A commercially available n ^- GaN substrate having a thickness of 5 μm and a Si-doped carrier concentration of 2 × 10 ¹⁶ cm ⁻³ was obtained as a semiconductor layer on the semiconductor substrate. Here, the crystal plane of the semiconductor substrate surface is (0001).

The surface of the n ^- GaN substrate was washed with an isopropyl alcohol and acetone solution at room temperature (23 ° C.) and then surface-treated with a dilute hydrofluoric acid solution having a concentration of 3% by volume.
Subsequently, using SPM made of H ₂ SO ₄ —H ₂ O ₂ —H ₂ O as an oxide film forming method, gallium oxide is generated on the surface of the n ⁻ GaN substrate, and the gallium oxide layer is formed into the first gallium oxide layer. An insulating film was obtained. That is, the n ^- GaN substrate was immersed in the SPM solution and processed at the temperature of the self-heating during the production of sulfuric acid / hydrogen peroxide. The volume ratio of H ₂ SO ₄ and H ₂ O ₂ is 2: 1.

Thereafter, a second insulating film made of SiO ₂ having a thickness of 100 nm was formed on the first insulating film made of gallium oxide by a plasma CVD method. The second insulating film is an amorphous film. And both insulating films were evaluated by cross-sectional TEM observation.

  FIG. 16 shows a cross-sectional TEM observation result. Here, (a) in FIG. 16 is a bright-field cross-sectional TEM image, (b) is a dark-field cross-sectional TEM image, and (c) is a dark-field cross-sectional TEM image superimposed with a diffraction image by FFT (Fast Fourier Transform) signal analysis. It is a statue. The white line in (c) and the white dot sequence with high luminance indicate the diffraction results.

  As a result, as can be seen from FIG. 16 (c), white dot sequences with high luminance are aligned in a straight line from the GaN crystal region to the first insulating film, and the crystal lattice of the GaN crystal and the first insulating film is It was confirmed that it was consistent. It has been confirmed from low-speed ion scattering spectroscopy that the first insulating film is made of a gallium oxide film.

Thereafter, the thickness of the second insulating film was changed to 10 nm, and a MIS capacitor was produced in the same manner as in Example 1. In addition, an Al ₂ O ₃ film having a thickness of 10 nm shown in Example 1 was formed as the second insulating film, and a MIS capacitor was fabricated in the same manner as in Example 1. As a result, the manufactured MIS capacitor had good interface characteristics with few trap sites.

  While the above description has been made with respect to particular embodiments, it will be apparent to those skilled in the art that the invention is not limited thereto and that various changes and modifications can be made within the scope of the principles of the invention and the appended claims. is there.

1 Oxygen atom (O)
2 Gallium atoms (Ga)
11 Crystal lattice 21 Lattice constant a ₁
22 Lattice constant a ₂
23 Lattice constant a ₃
100 Semiconductor Device 101 Semiconductor Layer 102 Insulator Layer (Gate Insulating Film)
103 First insulating film 104 Second insulating film 105 Gate electrode 107 Source region 108 Drain region 109 Source electrode 110 Drain electrode 111 Free-standing substrate 151 Screen layer 152 Insulating layer 153 Cap layer 161 Photoresist layer 200 MIS capacitor 201 n ⁻ GaN Free standing substrate 202 n ⁻ GaN epitaxial layer 203 Insulator layer 204 First insulating film 205 Second insulating film 206 Electrode 207 Electrode 300 Vertical MISFET
310 p-type semiconductor layer 312 n-type source side region 313 surface side end 314 n-type drain side region 316 p ⁺ -type contact layer 318 n ⁺ -type contact layer 320 current blocking layer 322 p ⁺ -type column 330 drift layer 332 n ⁺ -type Semiconductor layer 340 Gate electrode 342 Gate insulating film (insulator layer)
343 Channel length 344 Source electrode 346 Drain electrode 350 Semiconductor substrate 351 First insulating film 352 Second insulating film 360 Photoresist layer 362 Photoresist layer 364 Photoresist layer 366 Photoresist layer 367 Open end 400 DMOS
401 Collector electrode 402 n-type GaN substrate (n ⁺ substrate)
403 GaN epitaxial layer (n ^- epi layer)
404 p-type well 405 diffusion layer 406 first insulating film 406a gallium oxide layer 407 second insulating film 407a second insulating film 408 gate electrode 408a metal film 411 insulating film (PSG film)
412 Emitter electrode 421a Gate insulator layer

Claims (19)

A semiconductor layer comprising gallium nitride;
A gate electrode;
An insulator layer provided between the semiconductor layer and the gate electrode;
The gallium nitride is a single crystal,
The insulator layer has at least a first insulating film containing a gallium oxide crystal in a portion adjacent to the semiconductor layer;
The gallium oxide crystal is a semiconductor device in which a crystal lattice of the gallium nitride and an in-plane lattice constant a are matched. The gallium nitride is a single crystal of wurtzite structure,
The semiconductor device according to claim 1, wherein the crystal of gallium oxide is a hexagonal crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. The gallium nitride is a single crystal of wurtzite structure,
2. The semiconductor device according to claim 1, wherein the gallium oxide crystal is a cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. The gallium nitride is a single crystal of wurtzite structure,
2. The semiconductor device according to claim 1, wherein the gallium oxide crystal is a hexagonal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm.   2. The semiconductor device according to claim 1, wherein the gallium oxide crystal is selected from the group consisting of an ε-structure gallium oxide, a γ-structure gallium oxide, and a combination thereof.   6. The semiconductor device according to claim 1, wherein a crystal plane of the gallium oxide is aligned with a crystal plane of the semiconductor layer.   7. The semiconductor device according to claim 1, wherein a thickness of the first insulating film is not less than a thickness of a monoatomic layer of the gallium oxide crystal and not more than 10 nm.   The semiconductor device according to claim 7, wherein the film thickness of the first insulating film is 5 nm or less.   The first insulating film is a gallium oxide crystal whose in-plane lattice constant a is matched with the crystal lattice of the gallium nitride, or a hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm to 0.34 nm. 7. The device according to claim 1, wherein the volume ratio of the gallium oxide crystal in the first insulating film is 95% or more. The semiconductor device according to one item.   In the case where the first insulating film has a combination of ε-structure gallium oxide and γ-structure gallium oxide, the volume ratio of the ε-structure gallium oxide crystal in the first insulating film is 70% or more. The semiconductor device according to claim 5, wherein the semiconductor device is 90% or less, and a γ-structure gallium oxide crystal occupies the remaining portion of the first insulating film.   11. The volume ratio of ε-structure gallium oxide crystals in the first insulating film is 80%, and the volume ratio of γ-structure gallium oxide crystals is 20%. Semiconductor device.   The first insulating film has a combination of ε-structure gallium oxide and γ-structure gallium oxide, and the volume ratio of the ε-structure gallium oxide and γ-structure gallium oxide in the first insulating film The semiconductor device according to claim 5, wherein is 95% or more.   The insulator layer includes a second insulating film provided between the gate electrode and the first insulating film, and the second insulating film includes Al, Si, Hf, Zr, Ta, and Ti. 13. The semiconductor according to claim 1, comprising an oxide, a nitride, or an oxynitride of at least one element selected from the group consisting of elements consisting of Ga, Y, Sc, and a rare earth element. apparatus.   The gate electrode has at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, poly-Si. The semiconductor device according to any one of the above. A method for manufacturing a semiconductor device according to any one of claims 1 to 14,
A semiconductor layer preparation step of preparing the semiconductor layer;
An insulator layer forming step of forming the insulator layer;
A manufacturing method comprising at least a gate electrode forming step of forming the gate electrode.   In the insulator layer forming step, the semiconductor layer is formed on the surface using at least one selected from the group consisting of sulfuric acid, hydrogen peroxide solution, ammonia, hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. The manufacturing method according to claim 15, comprising a step of forming the first insulating film by processing.   The manufacturing method according to claim 15, wherein the insulator layer forming step includes a step of forming the first insulating film by subjecting the semiconductor layer to plasma oxidation treatment and / or ozone oxidation treatment at 500 ° C. or less. Method.   The insulator layer forming step is performed on the semiconductor layer using an electron beam evaporation method and / or MBE method at 700 ° C. or less, using a CVD method at 870 ° C. or less, and performing an HVPE method at 700 ° C. or less. The manufacturing method according to claim 15, comprising: using the ALD method at 500 ° C. or lower and / or laminating the first insulating film using a sputtering method at 500 ° C. or lower. .   In the insulator layer forming step, a gallium oxide crystal is formed on the semiconductor layer by a heat treatment of 500 ° C. or more and 870 ° C. or less, and then etching is performed to reduce the thickness of the gallium oxide crystal to 10 nm or less. The manufacturing method according to claim 15, comprising a step of forming the first insulating film.