JP2009152349A - Hetero-junction field effect transistor and method of producing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent increase in parasitic resistance by lowering potential barrier in the lower side of source/drain electrodes. <P>SOLUTION: The hetero-junction field effect transistor (FET) is formed of a nitride semiconductor provided with including a channel layer 30 and a barrier layer 50 formed on the channel layer 30 via a spacer layer 40. Moreover, this transistor is additionally provided with a gate electrode 80 formed on the barrier layer 50 and source/drain electrodes 70 formed on the barrier layer 50 to hold the gate electrode 80. The spacer layer 40 is formed in a region at the lower side of the gate electrode 80 and is provided with a first spacer layer 41 that is larger in a band gap than any of the channel layer 30 and barrier layer 50. The spacer layer 40 is formed in a region at the lower side of the source/drain electrodes 70 and is provided with a second spacer layer 42 that is smaller in the band gap than the first spacer layer 41. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a heterojunction field effect transistor made of a semiconductor containing nitride and a method of manufacturing the same.

  In a conventional heterojunction field effect transistor made of a semiconductor containing nitride, a spacer layer made of AlN (Al: aluminum, N: nitrogen) having a thickness of about 1 to 2 nm is formed between the channel layer and the barrier layer as a substrate. The structure is provided over the entire surface. With this structure, the concentration and mobility of the two-dimensional electron gas generated at the interface between the channel layer and the barrier layer are improved. This structure is described in Patent Document 1, for example.

Japanese Patent No. 3708810

  However, since AlN has a large band gap, if a spacer layer made of AlN is also formed in the lower region of the source / drain electrode, the potential barrier between the source / drain electrode and the two-dimensional electron gas is high. Become. For this reason, the above-described structure has a problem that parasitic resistance increases, and many device characteristics such as drain current, mutual conductance, output, and efficiency are deteriorated accordingly.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent an increase in parasitic resistance by lowering a potential barrier below a source / drain electrode.

  A heterojunction field effect transistor according to the present invention is a heterojunction field effect transistor made of a nitride semiconductor, and includes a channel layer, a barrier layer formed on the channel layer via a spacer layer, and the barrier A gate electrode formed on the layer; and a source / drain electrode formed on the barrier layer with the gate electrode interposed therebetween. The spacer layer is formed in at least a partial region below the gate electrode, and has a first spacer layer having a band gap larger than any of the channel layer and the barrier layer, and the source / drain electrode. And a second spacer layer having a band gap smaller than that of the first spacer layer.

  According to the heterojunction field effect transistor of the present invention, since the second spacer having a small band gap is formed below the source / drain electrode, the potential barrier below the source / drain electrode can be lowered. As a result, an increase in parasitic resistance can be prevented.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a heterojunction field effect transistor (hereinafter referred to as a transistor) made of a nitride semiconductor according to the present embodiment. This transistor includes a semi-insulating substrate 10, a buffer layer 20, a channel layer 30, a spacer layer 40, a barrier layer 50, an element isolation region 60, a source / drain electrode 70, and a gate electrode 80. .

  As the semi-insulating substrate 10, for example, a substrate made of SiC (silicon carbide) is used. The channel layer 30 is formed above the lowermost semi-insulating substrate 10 via the buffer layer 20. The barrier layer 50 is formed on the channel layer 30 via the spacer layer 40.

  The element isolation region 60 is a region that isolates the transistor according to the present embodiment from other elements, and is formed outside the region where the transistor is formed. The gate electrode 80 is formed on the barrier layer 50. The material of the gate electrode 80 is made of, for example, an alloy (Ni / Au) of Ni (nickel) and Au (gold). The source / drain electrode 70 is formed on the barrier layer 50 with the gate electrode 80 interposed therebetween. The source / drain electrode 70 is made of, for example, an alloy of Ti (titanium) and Al (Ti / Al).

  The spacer layer 40 includes a first spacer layer 41 and a second spacer layer 42. The first spacer layer 41 is formed in at least a partial region below the gate electrode 80, and has a larger band gap than both the channel layer 30 and the barrier layer 50. The second spacer layer 42 is formed in at least a partial region below the source / drain electrode 70, and has a band gap smaller than that of the first spacer layer 41. In the transistor according to FIG. 1, both ends of the second spacer layer 42 and both ends of the source / drain electrode 70 are aligned. That is, the width of the second spacer layer 42 is adjusted to the width of the source / drain electrode 70.

In the transistor according to the present embodiment, the channel layer 30, the first and second spacer layers 41 and 42 included in the spacer layer 40, and the barrier layer 50 include at least one of Al and Ga (gallium). N only. Therefore, the channel layer 30 is Al _X30 Ga _{1 -X30} N (0 ≦ X ₃₀ <1), the first spacer layer 41 is Al _X41 Ga _{1 -X41} N (0 <X ₄₁ ≦ 1), and the second spacer layer. 42 is made of Al _X42 Ga _{1 -X42} N (0 <X ₄₂ ≦ 1), and the barrier layer 50 is made of Al _X50 Ga _{1 -X50} N (0 <X ₅₀ ≦ 1).

Al _X Ga _1-X N has a higher band gap as the Al composition is higher (X is larger). In the transistor according to the present embodiment, X ₃₀ <X ₅₀ <X ₄₁ so that “band gap of channel layer 30 <band gap of barrier layer 50 <band gap of first spacer layer 41”. I have to. By adopting such a structure, the concentration and mobility of the two-dimensional electron gas are improved. In the present embodiment, in particular, X ₄₁ = 1, that is, the first spacer layer 41 is made of AlN. Further, by setting X ₄₂ <X ₄₁ , “the band gap of the second spacer layer 42 <the band gap of the first spacer layer 41” is satisfied. Note that in the transistor according to this embodiment, the Al composition of the second spacer layer 42 is uniform throughout the layer.

  In the transistor according to the present embodiment configured as described above, the second spacer layer 42 having a small band gap is formed below the source / drain electrode 70. Therefore, the potential barrier on the lower side of the source / drain electrode 70 can be lowered, and accordingly, the parasitic resistance can be reduced.

  As described above, the typical structure of the transistor according to this embodiment has been described with reference to FIG. 1, but the same effect as described above can be obtained even with the structure described below. In the transistor according to FIG. 1, both ends of the second spacer layer 42 and both ends of the source / drain electrode 70 are aligned. That is, the width of the second spacer layer 42 is adjusted to the width of the source / drain electrode 70. If the second spacer layer 42 is formed on at least a part of the lower side of the source / drain electrode 70, the potential barrier in that region is lowered, thereby reducing the parasitic resistance. Therefore, for example, as shown in FIG. 2, the width of the second spacer layer 42 may be smaller than the width of the source / drain electrode 70. On the other hand, the second spacer layer 42 only needs to be formed in a region other than the lower region of the gate electrode 80. As shown in FIG. 3, the width of the second spacer layer 42 is set to the source / drain electrode. It may be larger than the width of 70.

  In the former case (FIG. 2), the concentration and mobility of the two-dimensional electron gas can be improved, but the effect of lowering the potential barrier between the source / drain electrode 70 and the two-dimensional electron gas is reduced. As a result, the device characteristics also deteriorate. On the other hand, in the latter case (FIG. 3), the potential barrier between the source / drain electrode 70 and the two-dimensional electron gas can be further reduced, but the concentration and mobility of the two-dimensional electron gas are reduced. As a result, the device characteristics also deteriorate.

  Therefore, as shown in FIG. 1, if both ends of the second spacer layer 42 and both ends of the source / drain electrode 70 are aligned, the effect of reducing the potential barrier and the two-dimensional electron gas can be reduced. Both the effects of improving the concentration and mobility can be obtained.

In the above transistor, the Al composition of the second spacer layer 42 is assumed to be uniform throughout the layer. However, the band gap of the second spacer layer 42 is equal to the band of the first spacer layer 41 if X ₄₂ <X _{41 in} at least a part of the region parallel to the surface. It becomes smaller than the gap, and the parasitic resistance is reduced. Therefore, when the position in the plane parallel to the semi-insulating substrate 10 is (x, y), X ₄₂ does not need to be constant with respect to x and y. Therefore, instead of the second spacer layer 42, as shown in FIG. 4, Al _X43 Ga _{1 -X43} N (0 ≦ X ₄₃ (0 ≦ X ₄₃ (where the Al composition is a variable with respect to the plane direction (x, y)). x, y) ≦ X ₄₁ , X _43min <X ₄₁ (X _{43 min} is the minimum value of X ₄₃ (x, y)))).

In the above-mentioned transistors, the second spacer layer 42, be thicker than the first spacer layer 41, if the Al composition X ₄₂ is sufficiently small as compared with the X _41, since the potential barrier is lowered, the parasitic resistance Reduced. Therefore, the thickness of the second spacer layer 42 is not necessarily the same as the thickness of the first spacer layer 41, and may be thicker than the first spacer layer 41 as shown in FIG. . Alternatively, as shown in FIG. 6, the second spacer layer 42 may be thinner than the first spacer layer 41. In the transistor shown in FIG. 4 as well, as long as the Al composition X ₄₃ (x, y) is sufficiently smaller than X ₄₁ , the second spacer layer 42 shown in FIGS. The spacer layer 43 may have a thickness different from that of the first spacer layer 41.

In FIG. 4, the case has been described in which the second spacer layer 42 has a relationship of X ₄₂ <X _{41 in} at least a part of the region in the plane direction (x, y) parallel to the surface. Similarly, if the relationship of X ₄₂ <X ₄₁ is satisfied in at least a part of the region in the depth direction z, the band gap of the second spacer layer 42 is equal to that of the first spacer layer 41. It becomes smaller than the band gap, and the parasitic resistance is reduced. Therefore, instead of the second spacer layer 42 described above, as shown in FIG. 7, Al _X44 Ga _{1 -X44} N (0 ≦ X ₄₄ (z ) ≦ X ₄₁ , X _{44 min} <X ₄₁ (X _{44 min} is the minimum value of X ₄₄ (z)))). Similarly, instead of the second spacer layer 43 shown in FIG. 4, as shown in FIG. 8, Al _X45 Ga _{1 -X45} N (0 ≦ X ₄₅ ( (x, y, z) ≦ X ₄₁ , X _{45 min} <X ₄₁ (X _{45 min} is the minimum value of X ₄₅ (x, y, z)))).

In the above description, the channel layer 30, the barrier layer 50, and the first and second spacer layers 41 and 42 to 45 include only at least one of Al and Ga, and N. It is not necessarily limited to this. For example, the band gap sizes of the channel layer 30, the first and second spacer layers ₄₁ , _{42 to} 45, and the barrier layer 50 are set to B ₃₀ , B ₄₁ , B ₄₂ , B ₄₃ (x, y), respectively. , B ₄₄ (z), B ₄₅ (x, y, z), and B ₅₀ . In this case, B ₃₀ <B ₅₀ <B ₄₁ , B ₄₂ <B ₄₁ , 0 ≦ B ₄₃ (x, y) ≦ B ₄₁ , B _43min <B ₄₁ , 0 ≦ B ₄₄ (z) ≦ B ₄₁ , B Other compounds may be used as long as _{44 min} <B ₄₁ , 0 ≦ B ₄₅ (x, y, z) ≦ B ₄₁ , and B _{45 min} <B ₄₁ are satisfied. Here, B _43min is the minimum value of B ₄₃ (x, y), B _44min is the minimum value of B ₄₄ (z), and B _45min is the minimum value of B ₄₅ (x, y, z). Examples of the other compounds mentioned above include at least two kinds of compounds containing N among Al and Ga to which In is added.

However, when the channel layer 30, the barrier layer 50, and the first and second spacer layers 41, 42 to 45 include only at least one of Al and Ga and N, the barrier layer 50 has a large polarization. Since the effect is generated, a high-concentration two-dimensional electron gas can be generated at the heterointerface. In the present embodiment, the first spacer layer 41 is made of X ₄₁ = 1, that is, AlN. Thereby, the mobility of the concentration of the two-dimensional electron gas at the heterointerface can be improved. These structures are advantageous for increasing the current and further increasing the output of the transistor, and are more preferable structures.

In general, a heterojunction field effect transistor has a higher breakdown voltage as the breakdown electric field of a semiconductor material used for the channel layer 30 is higher. As described above, Al _X Ga _1-X N has a higher band gap and a higher breakdown electric field as the Al composition is higher. Therefore, Al _X30 Ga _{1 -X30} N used for the channel layer 30 described above preferably has a high Al composition (X ₃₀ is close to 1). Similarly, Al _X50 Ga _{1 -X50} N used for the barrier layer 50 also has a high Al composition from the viewpoint of making it difficult for the gate leakage current flowing from the gate electrode 80 to the heterointerface through the barrier layer 50 (X ₅₀ is close to 1).

  Further, the channel layer 30 and the barrier layer 50 described above do not necessarily have a structure composed of one layer having the same composition as long as the above-described band gap relational expression is satisfied. For example, the In composition, Al composition, and Ga composition may be spatially changed, or a multilayer film formed by stacking a plurality of films having different composition ratios may be used. In addition, these layers may contain, for example, an n-type or p-type impurity in a nitride semiconductor containing Si.

The transistor according to FIG. 9 further includes a cap layer 90 in addition to the above structure. The cap layer 90 is formed between the gate electrode 80 and the barrier layer 50 and has a band gap smaller than that of the barrier layer 50. In this figure, the barrier layer 50 is covered with a cap layer 90. The cap layer 90 has a thickness of 0.1 to 50 nm, for example, and is made of Al _X90 Ga ₁ -X90 N (0 ≦ X ₉₀ <X ₅₀ ). With such a structure, the Schottky barrier generated at the gate electrode 80 and the semiconductor interface is increased, the gate leakage current can be reduced, and the Schottky breakdown voltage can be increased.

  In the above description, the semi-insulating substrate 10 has been described as being made of SiC. However, the semi-insulating substrate 10 is not necessarily limited to this, and for example, a substrate made of Si, sapphire, GaN, or AlN may be used. In particular, when GaN is used as the semi-insulating substrate 10, the buffer layer 20 is not necessarily formed. That is, in that case, the channel layer 30 may be formed directly on the semi-insulating substrate 10.

  The transistor according to FIG. 10 is obtained by changing a part of the barrier layer 50 described above. In this transistor, the thickness of the portion under the source / drain electrode 70 of the barrier layer 50 is thinner than the other portions. With such a structure, the potential barrier generated by the barrier layer 50 below the source / drain electrode 70 can be reduced, and the parasitic resistance can be further reduced.

  In the above description, the source / drain electrode 70 is described as being made of Ti / Al. However, the present invention is not necessarily limited to this, and if ohmic characteristics are obtained, for example, Ti, Al, Nb (niobium), Hf (hafnium), Zr (zirconium), Sr (strontium), Ni, Ta (tantalum) , Au, Mo (molybdenum), W (tungsten), or the like, or a multilayer film composed of a plurality of these metals.

  The transistor according to FIG. 11 further includes an insulating film 100 in addition to the above structure. This insulating film 100 is formed between the gate electrode 80 and the barrier layer 50. Thus, the gate electrode 80 has a structure that is not in contact with the barrier layer 50. As the material of the insulating film 100, for example, an oxide, nitride, or oxynitride of at least one kind of atoms of Al, Ga, Si, Hf, and Ti is used. With such a structure, gate leakage current can be reduced.

  The transistor according to FIG. 12 is obtained by changing a part of the gate electrode 80 whose cross section shown in FIGS. In this transistor, the width of the lower portion of the gate electrode 81 is smaller than the portion other than the lower portion. Such a gate electrode 81 corresponds to, for example, a gate electrode having a Y-shaped or T-shaped cross section shown in FIG. With this structure, the width of the gate electrode 81 can be increased except for the contacted portion while maintaining the contact area between the gate electrode 81 and the barrier layer 50, thereby reducing the gate resistance. can do.

  The transistor according to FIGS. 13 and 14 further includes an insulating film 101 in addition to the transistor according to FIG. The insulating film 101 is formed between a portion other than the lower portion of the gate electrode 80 and the barrier layer 50. 13 shows a transistor in which the insulating film 101 is formed on the entire surface of the barrier layer 50, and FIG. 14 shows a transistor in which the insulating film 101 is partially formed. As the material of the insulating film 101, for example, an oxide, nitride, or oxynitride of at least one kind of atoms of Al, Ga, Si, Hf, and Ti is used. With such a structure, the electric field concentrated on the edge portion on the drain electrode side of the gate electrode 81 during high voltage operation is relieved, so that the breakdown voltage can be increased.

  The transistor according to FIG. 15 is obtained by changing a part of the barrier layer 50 described above. In this transistor, the thickness of the portion under the gate electrode 80 of the barrier layer 50 is thinner than the other portions. That is, the gate electrode structure according to this figure is not the planar structure shown in FIGS. 1 to 14, but a part of the barrier layer 50 sandwiched between the source / drain electrodes 70 is etched, and the gate electrode structure is located inside the etched region. A recess structure for forming the gate electrode 80 is formed. With such a structure, the source resistance can be reduced as compared with the planar structure. Although the gate electrode 80 has been described here, the same effect can be obtained even with the gate electrode 81.

  In the transistor according to FIG. 16, a recess 51, that is, a recess is provided in a portion of the barrier layer 50 below the gate electrode 81. The lower part of the gate electrode 81 is buried in the recess 51. That is, the gate electrode structure according to FIG. 15 is not the planar structure shown in FIGS. 1 to 14, but a part of the barrier layer 50 sandwiched between the source / drain electrodes 70 is etched, and the etched recess 51 is formed. It has a buried gate structure in which the gate electrode 81 is formed so as to cover it. By adopting such a structure, the source resistance can be reduced as compared with the planar structure, and the electric field concentrated on the edge part on the drain electrode side of the gate electrode 81 during the high voltage operation is relaxed. The breakdown voltage can be increased.

Further, the material of the gate electrodes 80 and 81 is not necessarily limited to Ni / Al, but a metal such as Ti, Al, Pt (platinum), Au, Ni, and Pd (palladium), IrSi, PtSi, and NiSi. _It may be formed of a silicide such as ₂ or a metal nitride such as TiN or WN, or a multilayer film composed of a plurality of these.

  Note that all of the above-described structures may be employed individually, or a structure in which each of them is combined. Although only the minimum necessary elements that operate as a transistor are described above, the device may further be formed with a protective film, wiring, and via hole.

<Embodiment 2>
In the present embodiment, a method for manufacturing a heterojunction field effect transistor according to the first embodiment will be described. Here, in particular, a method for manufacturing the transistor according to FIG. 1 will be described. Note that, in the method for manufacturing a transistor according to this embodiment, components that are the same as or equivalent to those in Embodiment 1 are denoted by the same reference numerals.

First, as shown in FIG. 17, the buffer layer 20, the channel layer 30, the spacer layer 40, and the barrier layer 50 are sequentially stacked on the semi-insulating substrate 10. In the present embodiment, the channel layer 30 is the Al _X30 Ga _{1 -X30} N described above, the spacer layer 40 is the same Al _X41 Ga _{1 -X41} N as the first spacer layer 41 described above, and the barrier layer 50 is the Al _X50 described above. It shall consist of _Ga1-X50N . For this lamination method, for example, MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method is used. In the present embodiment, these layers are stacked on the semi-insulating substrate 10 by the latter epitaxial growth method.

Next, as shown in FIG. 18, a resist mask 110 is formed on the barrier layer 50 and patterned. The partially ion-implanted barrier layer 50, a second spacer layer 42 made of Al _X41 first spacer layer 41 made of _{Ga 1-X41 N, Al X42} Ga 1-X42 N. In the present embodiment, ions are implanted into a desired region, and a part of the spacer layer 40 in that region is mixed, that is, the Al composition of each of the channel layer 30, the spacer layer 40, and the barrier layer 50 is averaged. First and second spacer layers 41 and 42 are formed. In this ion implantation, for example, Ga, Al, and Ar ions are implanted under conditions of an implantation dose amount of 1 × 10 ¹³ to 1 × 10 ¹⁷ (cm ⁻² ) and an implantation energy of 10 to 1000 (keV).

  Next, as shown in FIG. 19, after removing the resist mask 110, for example, a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Mo, and W is formed on the barrier layer 50. Alternatively, a plurality of types of multilayer films are deposited using an evaporation method or a sputtering method, and a lift-off method is performed. As a result, the source / drain electrode 70 is formed on the barrier layer 50.

  Next, as shown in FIG. 20, element isolation regions 60 are formed in the channel layer 30, the first spacer layer 41, and the barrier layer 50 outside the region in which the transistor is to be formed using, for example, ion implantation or etching. To do. In the present embodiment, it is assumed that the element isolation region 60 is formed by ion implantation.

Next, as shown in FIG. 21, on the barrier layer 50, for example, metal such as Ti, Al, Pt, Au, Ni, Pd, silicide such as IrSi, PtSi, NiSi ₂ , or TiN, WN, etc. A metal nitride or a multilayer film composed of a plurality of these is deposited using, for example, a vapor deposition method or a sputtering method, and a lift-off method is performed. Thereby, the gate electrode 80 is formed on the barrier layer 50 sandwiched between the source / drain electrodes 70.

  With the above method, the heterojunction field effect transistor shown in FIG. 1 can be formed. Although only the minimum necessary elements that operate as a transistor are described above, a device is finally formed through a process of forming a protective film, a wiring, and a via hole. In the above, the production of a typical transistor according to FIG. 1 has been described, but various transistors described in Embodiment 1 can be produced under the following conditions.

  In FIG. 18, formation of the resist mask 110 and ion implantation are repeated a plurality of times while changing the resist pattern and implantation conditions (for example, implantation energy and implantation amount). Thus, the transistor according to FIGS. 1 to 8 shown in Embodiment Mode 1 can be formed.

  In FIG. 17, during the growth of the channel layer 30, the spacer layer 40, and the barrier layer 50, the flow rate, pressure, temperature, and time of trimethylammonium, trimethylgallium, trimethylindium, and ammonia used as the nitride semiconductor source gas are adjusted. Thereby, the channel layer 30, the spacer layer 40, and the barrier layer 50 have a desired composition and thickness. In this way, various nitride semiconductor heterojunction field effect transistors described in the first embodiment can be formed.

In FIG. 17, after growing the barrier layer 50, a thin cap layer 90 made of Al _X90 Ga ₁ -X90 N (0 ≦ X ₉₀ <X ₅₀ ) having a thickness of 0.1 to ₅₀ nm is formed on the barrier layer 50. If grown, the transistor shown in FIG. 9 of Embodiment 1 can be formed.

In FIG. 19, before the source / drain electrode 70 is formed, a part of the surface of the barrier layer 50 above the second spacer layer 42 is removed by using, for example, a dry etching method using Cl ₂ . Then, the source / drain electrode 70 may be formed in the removed portion. Thus, the transistor shown in FIG. 10 of Embodiment 1 can be formed.

  In FIG. 21, before forming the gate electrode 80, as shown in FIG. 22, for example, at least one of Al, Ga, Si, Hf, and Ti is used, for example, by vapor deposition or plasma CVD. An insulating film 100 is formed by depositing oxides, nitrides, and oxynitrides of atoms. Then, the gate electrode 80 may be formed over the insulating film 100. Thus, the transistor illustrated in FIG. 11 of Embodiment 1 can be formed. For final use as a device, it is necessary to form a wiring after removing a portion of the insulating film 100 covering the source / drain electrode 70 by wet etching using, for example, fluorine. is there.

After the formation of the insulating film 100 in FIG. 22, as shown in FIG. 23, the insulating film 100 sandwiched between the source / drain electrodes 70 by, for example, dry etching using CF ₄ or wet etching using hydrofluoric acid. The insulating film 101 is formed by removing the portion. After that, by forming a Y-shaped gate electrode 81, the transistor shown in FIG. 13 of Embodiment 1 can be formed. For final use as a device, it is necessary to form a wiring after removing a portion of the insulating film 101 covering the source / drain electrode 70 by wet etching using, for example, fluorine. is there.

  As shown in FIG. 13, after the gate electrode 81 is formed, the insulating film 101 is entirely removed by wet etching using hydrofluoric acid, for example. Thus, the transistor shown in FIG. 12 of Embodiment 1 can be formed. Further, the insulating film 101 in a desired region is left by adjusting the processing conditions (for example, time and concentration) of the wet etching here. Thus, the transistor shown in FIG. 14 of Embodiment 1 can be formed.

After the element isolation region 60 in FIG. 20 is formed, a part of the surface of the barrier layer 50 sandwiched between the source / drain electrodes 70 is removed by dry etching using, for example, Cl _2, and a recess 51, that is, a recess is formed in advance. To do. Thereafter, by forming gate electrodes 80 and 81 in the recess 51, the transistor shown in FIGS. 15 and 16 of the first embodiment can be produced.

  In the above process, the source / drain electrode 70 formation, the element isolation region 60 formation, and the gate electrodes 80 and 81 were performed in this order. However, the order is not necessarily limited to this order. For example, the order of these three steps may be changed such that the element isolation region 60 is formed before the source / drain electrode 70 is formed.

2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. 2 is a diagram illustrating a structure of a transistor according to Embodiment 1. FIG. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment. FIG. 10 is a diagram illustrating a method for manufacturing the transistor according to the second embodiment.

Explanation of symbols

  10 semi-insulating substrate, 20 buffer layer, 30 channel layer, 41 first spacer layer, 42 to 45 second spacer layer, 50 barrier layer, 51 recess, 60 element isolation region, 70 source / drain electrode, 80, 81 gate electrode, 90 cap layer, 100, 101 insulating film, 110 resist mask.

Claims (4)

A heterojunction field effect transistor made of a nitride semiconductor,
A channel layer;
A barrier layer formed on the channel layer via a spacer layer;
A gate electrode formed on the barrier layer;
A source / drain electrode formed on the barrier layer with the gate electrode interposed therebetween;
The spacer layer is
A first spacer layer formed in at least a partial region below the gate electrode and having a larger band gap than any of the channel layer and the barrier layer;
A second spacer layer formed in at least a partial region below the source / drain electrode and having a band gap smaller than that of the first spacer layer;
Heterojunction field effect transistor. The channel layer, the spacer layer, and the barrier layer are
Including at least one of Al and Ga and N;
The heterojunction field effect transistor according to claim 1. The first spacer layer is made of AlN.
The heterojunction field effect transistor according to claim 1. A method of manufacturing a heterojunction field effect transistor according to any one of claims 1 to 3,
(A) laminating the channel layer, the spacer layer, and the barrier layer in order;
(B) after the step (a), partially ion-implanting from the barrier layer to form the first and second spacer layers;
A method of manufacturing a heterojunction field effect transistor.

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