JP2013055224A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a heterojunction field effect transistor capable of achieving normally-off operation by suppressing formation of a damage layer to a semiconductor layer in a region facing a gate electrode, and to provide a manufacturing method therefor.SOLUTION: An impurity doping region 26 is formed by doping impurities for forming a level in a bandgap having an energy depth up to the energy sum (ΔEc+ΔEp) of a band discontinuous amount ΔEc, from the conduction band of a barrier layer 24 to the heterointerface of a channel layer 23 and the barrier layer 24, and the energy difference ΔEp between the gate electrode 29 side of the barrier layer 24 and the heterointerface side due to polarization generated in the barrier layer 24, in a region of the barrier layer 24 forming a heterojunction and the channel layer 23 excepting a region facing the gate electrode 29.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a heterojunction field effect transistor using a nitride semiconductor and a manufacturing method thereof.

  In a normally-off heterostructure field effect transistor using a nitride semiconductor, in order to eliminate the two-dimensional electron gas in the semiconductor layer in the region facing the gate electrode (hereinafter sometimes referred to as “gate region”), Before the formation, some process treatment is performed on the semiconductor layer in the gate region (see, for example, Patent Documents 1 and 2 and Non-Patent Document 1).

  For example, Patent Document 1 discloses a structure in which a part of a semiconductor layer in a gate region is removed by dry etching. Patent Document 2 discloses a structure in which a part of a semiconductor layer in a gate region is doped with a p-type impurity. Non-Patent Document 1 discloses a structure in which a plasma treatment using a fluorine-based gas is performed on a semiconductor layer in a gate region.

JP 2005-183733 A JP 2004-273486 A

Yong Cai, three others, “High-Performance Enhancement-Mode AlGaN / GaN HEMTs Using Fluoride-Based Plasma Treatment”, IEEE ELECTRON DEVICE LETTERS, JULY 2005, VOL. 26, no. 7, pp 435-437

  As disclosed in Patent Document 1, Patent Document 2, and Non-Patent Document 1 described above, in a normally-off heterostructure field effect transistor using a nitride semiconductor, the two-dimensional electron gas in the semiconductor layer in the gate region disappears. In order to achieve this, some process treatment is performed on the semiconductor layer in the gate region before forming the gate electrode. By this process treatment, some damage layer is formed at the semiconductor layer in the gate region and at the interface between the gate electrode and the semiconductor layer.

  Since this damaged layer is close to the gate electrode that plays a role in controlling the current of the transistor, it has a great influence on the characteristics of the transistor. For example, the damage layer tends to cause adverse effects such as an increase in leakage current in the off state and current collapse in which the drain current decreases during pulse operation.

  An object of the present invention is to provide a semiconductor having a heterojunction field effect transistor capable of suppressing a formation of a semiconductor layer in a region facing a gate electrode and a damage layer at an interface between the gate electrode and the semiconductor layer and realizing a normally-off operation. An apparatus and a method for manufacturing the same are provided.

  The semiconductor device of the present invention is a semiconductor device including a heterojunction field effect transistor including a nitride semiconductor layer, and the heterojunction field effect transistor includes a first nitride semiconductor layer provided on a substrate, A second nitride provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer and forming a heterojunction with the first nitride semiconductor layer A semiconductor layer; and a gate electrode, a source electrode, and a drain electrode provided on the second nitride semiconductor layer, the gate electrode being interposed between the source electrode and the drain electrode, The nitride semiconductor layer includes a band discontinuity amount ΔEc at the heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer, from the conduction band of the second nitride semiconductor layer, An energy depth up to an energy (ΔEc + ΔEp) obtained by adding an energy difference ΔEp between the gate electrode side and the heterointerface side of the second nitride semiconductor layer due to polarization generated in the second nitride semiconductor layer An impurity that forms a level in a band gap includes a concentration of the impurity in at least a part of a region facing the gate electrode in the second nitride semiconductor layer. It is characterized in that it is lower than the concentration of the impurity in at least a part of the other region excluding the region facing the gate electrode.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device including a heterojunction field effect transistor including a nitride semiconductor layer, wherein the first layer is formed on the substrate. A second layer forming step of forming a second nitride semiconductor layer forming a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer, and the second nitride An electrode forming step of forming a gate electrode, a source electrode, and a drain electrode on the physical semiconductor layer, wherein the gate electrode is interposed between the source electrode and the drain electrode in the electrode forming step. Formed between the second layer forming step and the electrode forming step, in a region excluding at least a part of a region predetermined as a region for forming the gate electrode in the second nitride semiconductor layer, From the conduction band of the second nitride semiconductor layer, the band discontinuity ΔEc at the heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer, and the second nitride semiconductor layer In the band gap of the energy depth up to the energy (ΔEc + ΔEp) obtained by adding the energy difference ΔEp between the gate electrode side and the heterointerface side of the second nitride semiconductor layer due to the polarization generated in A doping step of doping impurities to be formed is provided.

  According to the semiconductor device of the present invention, the second nitride semiconductor layer forming the heterojunction with the first nitride semiconductor layer of the heterojunction field effect transistor has a conduction band of the second nitride semiconductor layer. The band discontinuity ΔEc at the heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer and the gate electrode of the second nitride semiconductor layer due to the polarization generated in the second nitride semiconductor layer Includes an impurity that forms a level in the band gap of energy depth up to the energy (ΔEc + ΔEp) obtained by adding the energy difference ΔEp between the side and the hetero interface side (hereinafter sometimes referred to as “level-forming impurity”) It is. In the second nitride semiconductor layer, the concentration of the level forming impurity in at least a part of the region facing the gate electrode (hereinafter sometimes referred to as “gate region”) excludes the gate region of the second nitride semiconductor layer. It is lower than the concentration of the level forming impurity in at least a part of the other region.

  By configuring in this way, the concentration of the two-dimensional electron gas generated in other regions other than the gate region of the second nitride semiconductor layer is made higher than the concentration of the two-dimensional electron gas generated in at least a part of the gate region. Can be high. As a result, the electric resistance of the other region excluding the gate region of the second nitride semiconductor layer can be made lower than the electric resistance of at least a portion of the gate region of the second nitride semiconductor layer.

  Therefore, current can be prevented from flowing between the source electrode and the drain electrode when no voltage is applied to the gate electrode, so that a normally-off operation of the heterojunction field effect transistor can be realized.

  In realizing this normally-off operation, as described above, in the second nitride semiconductor layer, the concentration of the level forming impurity in at least a part of the gate region is set to other than the gate region of the second nitride semiconductor layer. The concentration may be lower than the concentration of the level forming impurity in at least a part of the region. In other words, it is not necessary to perform a process on the second nitride semiconductor layer such that a damage layer is formed at the interface between the second nitride semiconductor layer in the gate region and the gate electrode and the second nitride semiconductor layer. .

  Therefore, it is possible to suppress the formation of the second nitride semiconductor layer in the gate region and the damage layer at the interface between the gate electrode and the second nitride semiconductor layer, and to achieve a normally-off operation, and the heterojunction field effect A semiconductor device including a type transistor can be obtained. By suppressing the formation of the damage layer in this way, in the heterojunction field effect transistor, it is possible to suppress an increase in leakage current and generation of current coplus, etc., so that the characteristics of the heterojunction field effect transistor deteriorate. Can be prevented.

  According to the method for manufacturing a semiconductor device of the present invention, the first nitride semiconductor layer is formed on the substrate in the first layer forming step. In the second layer forming step, a second nitride semiconductor layer is formed on the first nitride semiconductor layer, and a heterojunction is formed with the first nitride semiconductor layer. In the doping step, a level forming impurity is doped into a region of the second nitride semiconductor layer excluding at least a part of a region predetermined as a region for forming the gate electrode. Next, in the electrode formation step, the gate electrode, the source electrode, and the drain electrode are formed on the second nitride semiconductor layer so that the gate electrode is interposed between the source electrode and the drain electrode.

  As a result, the second nitride semiconductor layer is not subjected to a process in which a damage layer is formed at the interface between the second nitride semiconductor layer in the gate region and the gate electrode and the second nitride semiconductor layer. In the second nitride semiconductor layer, the concentration of the level forming impurity in at least a part of the gate region is such that the concentration of the level forming impurity in at least a part of the other region excluding the gate region of the second nitride semiconductor layer. A semiconductor device including a lower heterojunction field effect transistor can be obtained.

  The semiconductor device having such a configuration can realize the normally-off operation of the heterojunction field effect transistor as described above. Therefore, it is possible to suppress the formation of the second nitride semiconductor layer in the gate region and the damage layer at the interface between the gate electrode and the second nitride semiconductor layer, and to achieve a normally-off operation, and the heterojunction field effect A semiconductor device including a type transistor can be obtained.

It is sectional drawing which shows the structure of the semiconductor device 101 which is one Embodiment of this invention. FIG. 4 is a cross-sectional view showing a state in which the stacking of the buffer layer 22, the carrier layer 23, and the barrier layer 24 on the substrate 21 is completed. 7 is a cross-sectional view showing a state at a stage where the formation of the impurity doping region is completed. FIG. FIG. 6 is a cross-sectional view showing a state at a stage where the formation of the source electrode 27 and the drain electrode 28 is completed. FIG. 10 is a cross-sectional view showing a state in which the formation of the element isolation region 25 is completed. It is sectional drawing which shows the state in the stage where formation of the gate electrode 29 was complete | finished. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. 6 is a cross-sectional view showing a state at a stage where the formation of the high-concentration n-type impurity region 35 is completed. FIG. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the state in the stage where formation of the insulating film 40 was complete | finished. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention. 7 is a cross-sectional view showing a stage where removal of a part of the insulating film 45 is completed. FIG. It is sectional drawing which shows the other example of the semiconductor device of this invention. It is sectional drawing which shows the other example of the semiconductor device of this invention.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device 101 according to an embodiment of the present invention. The semiconductor device 101 according to the present embodiment includes a heterojunction field effect transistor (hereinafter sometimes simply referred to as “transistor”) 1 using a nitride semiconductor. In the present embodiment, the semiconductor device 101 includes the transistor 1 and other semiconductor elements (not shown).

  As shown in FIG. 1, the semiconductor device 101 includes a substrate 21, a buffer layer 22, a channel layer 23, a barrier layer 24, an element isolation region 25, an impurity doping region 26, a source electrode 27, a drain electrode 28, and a gate electrode 29. Configured. The buffer layer 22, the channel layer 23, the barrier layer 24, the impurity doping region 26, the source electrode 27, the drain electrode 28, and the gate electrode 29 constitute the transistor 1.

  The substrate 21 is realized by silicon carbide (SiC). The material of the substrate 21 is not limited to SiC, and may be any material that can form a nitride semiconductor layer on the substrate 21, more specifically, any material that can epitaxially grow the nitride semiconductor layer on the substrate 21. Specifically, the material of the substrate 21 may be silicon (Si), sapphire, gallium nitride (GaN), aluminum nitride (AlN), or the like.

  A buffer layer 22 is provided on the surface of one side in the thickness direction of the substrate 21. A channel layer 23 is provided on the surface of one side in the thickness direction of the buffer layer 22. A barrier layer 24 is provided on the surface of the channel layer 3 on one side in the thickness direction. The buffer layer 22, the channel layer 23, and the barrier layer 24 are nitride semiconductor layers and are made of a nitride semiconductor. The channel layer 23 and the barrier layer 24 form a heterojunction. The barrier layer 24 has a larger band gap than the channel layer 23. The channel layer 23 corresponds to a first nitride semiconductor layer. The barrier layer 24 corresponds to a second nitride semiconductor layer.

  The impurity doping region 26 is formed in the barrier layer 24. The impurity doping region 26 contains impurities. The impurity doping region 26 is formed by doping the barrier layer 24 with impurities. As the impurities contained in the impurity doping region 26, in the nitride semiconductor constituting the barrier layer 24, an impurity that forms a level in a band gap of an energy depth from a conduction band to a level formable width ΔEt described later. Can be mentioned. Examples of such a material include Si, oxygen atoms (O), and nitrogen vacancies.

  The gate electrode 29 is provided on the surface on one side in the thickness direction of the barrier layer 24. The gate electrode 29 functions as a Schottky electrode.

The gate electrode 29 only needs to obtain Schottky characteristics. For example, titanium (Ti), aluminum (Al), platinum (Pt), gold (Au), nickel (Ni), palladium (Pd), and other metals, iridium Formed by silicide such as silicide (IrSi), platinum silicide (PtSi), nickel silicide (NiSi ₂ ), nitride metal such as titanium nitride (TiN), tungsten nitride (WN), or a multilayer film composed of these. Is done.

  The source electrode 27 and the drain electrode 28 are provided on the surface on one side in the thickness direction of the barrier layer 24 so as to face each other with the gate electrode 29 interposed therebetween. Both the source electrode 27 and the drain electrode 28 are provided at a distance from the gate electrode 29. In other words, the gate electrode 29 is interposed between the source electrode 27 and the drain electrode 28.

  For example, titanium (Ti), aluminum (Al), niobium (Nb), hafnium (Hf), zirconium (Zr), strontium (Sr), nickel may be used for the source electrode 27 and the drain electrode 28. It is formed of a metal such as (Ni), tantalum (Ta), gold (Au), molybdenum (Mo) or tungsten (W), or a multilayer film composed of these metals.

  The element isolation region 25 isolates the transistor 1 from other semiconductor elements (not shown) provided on the substrate 21. In this embodiment mode, a semiconductor element other than the transistor 1 is provided over the substrate 21, and the semiconductor device 101 includes the transistor 1 and another semiconductor element. In another embodiment of the present invention, the semiconductor device may not include other semiconductor elements. In this case, the element isolation region 25 may not be provided.

  The element isolation region 25 is formed in an epitaxial crystal layer in a region other than the region where the transistor 1 is formed. More specifically, the element isolation region 25 is formed in an epitaxial crystal layer between a region where the transistor 1 is formed and a region where another semiconductor element is formed. In the present embodiment, the epitaxial crystal layers are the buffer layer 22, the channel layer 23, and the barrier layer 24, and the element isolation region 25 is formed in the channel layer 23 and the barrier layer 24.

  The barrier layer 24 will be described more specifically. A band discontinuity formed at the heterointerface between the channel layer 23 and the barrier layer 24 is represented by ΔEc. When the channel layer 23 and the barrier layer 24 form a hetero bond, polarization occurs in the barrier layer 24. An energy difference between the gate electrode 29 side and the heterointerface side of the barrier layer 24 due to polarization generated in the barrier layer 24 is represented by ΔEp. The energy obtained by adding the band discontinuity amount ΔEc and the energy difference ΔEp between the gate electrode 29 side and the heterointerface side of the barrier layer 24 (ΔEc + ΔEp, hereinafter referred to as “level-formable width”) is denoted as ΔEt (ΔEt = ΔEc + ΔEp).

  Here, the heterointerface side of the barrier layer 24 refers to the surface side of the barrier layer 24 in contact with the channel layer 23, that is, the surface side of the other side in the thickness direction of the barrier layer 24. The gate electrode 29 side of the barrier layer 24 refers to the surface side facing the gate electrode 29 of the barrier layer 24. Specifically, the gate electrode 29 side of the barrier layer 24 is the surface side opposite to the surface in contact with the channel layer 23 of the barrier layer 24, that is, the surface side on one side in the thickness direction of the barrier layer 24 (hereinafter referred to as “barrier layer 24”). It may be referred to as “the front side of the surface”).

  In the transistor 1 of the present embodiment, the barrier layer 24 has an impurity doping region 26. The impurity doping region 26 is doped with an impurity (hereinafter referred to as a “level-forming impurity”) that forms a level in a band gap having an energy depth from the conduction band of the barrier layer 24 to the level-formable width ΔEt. Yes. In other words, the impurity doping region 26 includes a level forming impurity.

  The impurity-doped region 26 is formed in at least a part of the barrier layer 24 other than a region facing the gate electrode 29 (hereinafter sometimes referred to as “gate region”). Specifically, the impurity doping region 26 is formed in at least a part of a region other than the gate region in the portion of the barrier layer 24 on the gate electrode 29 side. Specifically, the gate region that is the region facing the gate electrode 29 of the barrier layer 24 is a region adjacent to the gate electrode 29 of the barrier layer 24. The region of the barrier layer 24 adjacent to the gate electrode 29 includes a portion in contact with the gate electrode 29 of the barrier layer 24 and a portion in the vicinity thereof.

  By forming the impurity doped region 26 in the barrier layer 24, the concentration of the level forming impurity in at least a part of the gate region of the barrier layer 24 is changed to a quasi level in at least a part of other regions of the barrier layer 24 except for the gate region. The concentration can be lower than the concentration of the potential forming impurities. In other words, the concentration of the level forming impurity in at least a part of the barrier layer 24 other than the gate region can be higher than the concentration of the level forming impurity in at least a part of the gate region.

  Here, at least a part of the gate region of the barrier layer 24 is a portion of the gate region of the barrier layer 24 where the impurity doping region 26 is not formed. In the present embodiment, the gate region of the barrier layer 24 is formed. Of the whole. At least a part of the other region excluding the gate region of the barrier layer 24 is a portion of the other region other than the gate region of the barrier layer 24 where the impurity doping region 26 is formed. In the present embodiment, the impurity doping region 26 is formed in a region excluding the gate region and the element isolation region 25 in the portion of the barrier layer 24 on the gate electrode 29 side.

  In other words, in the present embodiment, the concentration of the level formation impurity in the gate region of the barrier layer 24 is at least a part of the other region excluding the gate region of the barrier layer 24. It is lower than the concentration.

Specifically, in the gate layer of the barrier layer 24, the concentration of the level forming impurity is sufficiently lowered to, for example, 1 × 10 ¹² cm ⁻² or less so that two-dimensional electron gas is not generated at the heterointerface. . In other regions except the gate region, specifically, the impurity doping region 26, the level forming impurity concentration exceeds the level forming impurity concentration in the gate region so that a two-dimensional electron gas is generated at the heterointerface. Be high enough to the extent. For example, when the concentration of the level formation impurity in the gate region is 1 × 10 ¹² cm ⁻² or less, the concentration of the level formation impurity in the impurity doping region 26 exceeds about 1 × 10 ¹² cm ^−2. Specifically, it is made sufficiently high to about 1 × 10 ¹³ cm ⁻² .

  As described above, in the present embodiment, the concentration of the level formation impurity in the gate region of the barrier layer 24 is at least a part of other regions except the gate region of the barrier layer 24, specifically, the quasi level in the impurity doping region 26. It is lower than the concentration of the potential forming impurities. With such a configuration, the concentration of the two-dimensional electron gas generated in other regions of the barrier layer 24 other than the gate region can be made higher than the concentration of the two-dimensional electron gas generated in the gate region. As a result, the electric resistance of the other region except the gate region of the barrier layer 24 can be made lower than the electric resistance of the gate region of the barrier layer 24.

  Therefore, it is possible to prevent a current from flowing between the source electrode 27 and the drain electrode 28 in a state where no voltage is applied to the gate electrode 29, thereby realizing a normally-off operation of the heterojunction field effect transistor 1. Can do.

  In realizing the normally-off operation, as described above, the concentration of the level forming impurity in at least a part of the gate region in the barrier layer 24 is set to the level formation in at least a part of the other region of the barrier layer 24 except for the gate region. The concentration may be lower than the impurity concentration. That is, it is not necessary to perform a treatment on the barrier layer 24 such that a damage layer is formed at the barrier layer 24 in the gate region and at the interface between the gate electrode 29 and the barrier layer 24.

  Therefore, the semiconductor device including the heterojunction field effect transistor 1 capable of realizing the normally-off operation by suppressing the formation of the damage layer at the barrier layer 24 in the gate region and the interface between the gate electrode 29 and the barrier layer 24. 101 can be obtained. By suppressing the formation of the damaged layer in this manner, in the transistor 1, an increase in leakage current and generation of current coplus can be suppressed, so that the characteristics of the transistor 1 can be prevented from being deteriorated.

  Below, the relationship between the density | concentration of the level formation impurity in the barrier layer 24 and the density | concentration of two-dimensional electron gas is demonstrated. When a heterostructure is formed using nitride semiconductors having different bandgap sizes, polarization occurs in a layer having a relatively large bandgap among the nitride semiconductor layers constituting the heterostructure. In the present embodiment, the channel layer 23 and the barrier layer 24 form a heterostructure, and the barrier layer 24 has a relatively large band gap, so that the barrier layer 24 is polarized. This increases the energy of the portion of the barrier layer 24 on the gate electrode 29 side.

  At this time, if an impurity level is formed in the band gap of the barrier layer 24 and the level is within the band gap of the energy depth of the level formation width ΔEt from the conduction band, it is shifted to the high energy side by polarization. In the portion of the gate electrode 29 of the barrier layer 24, the impurity level is depleted. In the gate electrode 29 portion of the barrier layer 24, a two-dimensional electron gas corresponding to the depleted concentration is formed at the hetero interface in order to preserve the electrical equilibrium state of the system. Therefore, the concentration of the level-forming impurity that forms the impurity level in the band gap of the energy depth from the conductor in the barrier layer 24 to the level formation width ΔEt is closely related to the concentration of the two-dimensional electron gas. Have

  From the above, in the present embodiment, as described above, the concentration of the level formation impurity in the gate region of the barrier layer 24 is set lower than the concentration of the level formation impurity in other regions other than the gate region. ing. As a result, the gate region is removed from the barrier layer 24 without subjecting the barrier layer 24 to a process in which a damage layer is formed at the barrier layer 24 in the gate region and at the interface between the gate electrode 29 and the barrier layer 24. A configuration is realized in which the concentration of the two-dimensional electron gas generated in the other region is higher than the concentration of the two-dimensional electron gas generated in the gate region.

  In the present embodiment, as described above, the impurity doping region 26 containing the level forming impurity is formed in the region other than the gate region in the portion of the barrier layer 24 on the gate electrode 29 side. This easily realizes a configuration in which the concentration of the level forming impurity in the region other than the gate region in the portion on the gate electrode 29 side of the barrier layer 24 is higher than the concentration of the level forming impurity in the gate region. be able to.

  Next, a method for manufacturing the semiconductor device 101 according to the embodiment of the present invention shown in FIG. 1 will be described. 2 to 6 are views for explaining a method of manufacturing the semiconductor device 101 according to the embodiment of the present invention. 2 to 6, portions corresponding to those in FIG. 1 are denoted by the same reference numerals, and common description is omitted.

  FIG. 2 is a cross-sectional view showing a state in which the stacking of the buffer layer 22, the carrier layer 23, and the barrier layer 24 on the substrate 21 is completed. A buffer layer 22, a channel layer 23, and a barrier layer 24 are stacked in this order on the substrate 21, specifically, on the surface on one side in the thickness direction of the substrate 21. The step of forming the channel layer 23 corresponds to the first layer forming step. The step of forming the barrier layer 24 corresponds to the second layer forming step.

  The buffer layer 22, the channel layer 23, and the barrier layer 24 are each formed by an epitaxial growth method such as a metal organic chemical vapor deposition (abbreviation: MOCVD) method or a molecular beam epitaxy (abbreviation: MBE) method. Is formed by epitaxial growth.

  FIG. 3 is a cross-sectional view showing a state in which the formation of the impurity doping region 26 is completed. In the barrier layer 24, the impurity doping region 26 is formed in a region that is predetermined as a region for forming the impurity doping region 26 (hereinafter sometimes referred to as “doping region formation region”). The doping region forming region is a region excluding at least a part of a region predetermined as a region for forming the gate electrode 29 in the barrier layer 24. In the present embodiment, the doping region forming region is a region excluding the entire region predetermined as a region for forming the gate electrode 29 in the barrier layer 24.

  Specifically, the impurity doping region 26 is formed as follows. Doping is performed by implanting ions such as Si and O into the doping region forming region of the barrier layer 24 using an ion implantation method or the like using a resist pattern or the like as a mask. Next, after removing a mask such as a resist pattern, the doped ions are activated using a rapid thermal annealing (abbreviation: RTA) method or the like. In this manner, the impurity doping region 26 is formed in the surface side portion on one side in the thickness direction of the barrier layer 24. Impurity doping regions 26 are formed in two places. The step of forming the impurity doping region 26 corresponds to a doping step.

  FIG. 4 is a cross-sectional view showing a state where the formation of the source electrode 27 and the drain electrode 28 is completed. A metal film to be a source electrode 27 and a drain electrode 28 is deposited on the impurity doping region 26 by a lift-off method or the like using an evaporation method or a sputtering method, and then alloyed using an RTA method or the like to form the source electrode 27 and A drain electrode 28 is formed. The metal film to be the source electrode 27 and the drain electrode 28 is, for example, titanium (Ti), aluminum (Al), niobium (Nb), hafnium (Hf), zirconium (Zr), strontium (Sr), nickel (Ni), tantalum. It is a single layer film made of a metal such as (Ta), gold (Au), molybdenum (Mo) or tungsten (W), or a multilayer film made of these.

  FIG. 5 is a cross-sectional view showing a state in which the formation of the element isolation region 25 has been completed. An element isolation region 25 is formed in the channel layer 23 and the barrier layer 24 outside the region for manufacturing the transistor 1 by using, for example, an ion implantation method or etching. FIG. 5 shows a case where the element isolation region 25 is formed by ion implantation.

FIG. 6 is a cross-sectional view showing a state where the formation of the gate electrode 29 is completed. A metal film to be the gate electrode 29 is deposited on the barrier layer 24 in which the impurity doping region 26 is formed by using an evaporation method or a sputtering method, and the gate electrode 29 is formed in a predetermined region by a lift-off method or the like. The gate electrode 29 is formed on the barrier layer 24 between the impurity doping regions 26. The metal film to be the gate electrode 29 is, for example, a metal such as titanium (Ti), aluminum (Al), platinum (Pt), gold (Au), nickel (Ni) and palladium (Pd), iridium silicide (IrSi), platinum It is a single layer film made of silicide such as silicide (PtSi), nickel silicide (NiSi ₂ ), or nitride metal such as titanium nitride (TiN) or tungsten nitride (WN), or a multilayer film composed of these.

  The process for forming the source electrode 27 and the drain electrode 28 shown in FIG. 4 and the process for forming the gate electrode 29 shown in FIG. 6 correspond to an electrode formation process.

  By the above method, the heterojunction field effect transistor 1 having the structure shown in FIG. 1 can be manufactured. In this embodiment mode, only a minimum necessary element that operates as a transistor is described, but finally, a device is formed through a formation process of a protective film, a wiring, a via hole, and the like. When the semiconductor device 101 includes another semiconductor element as in this embodiment, the semiconductor device 101 is obtained through a process for forming another semiconductor element.

  As described above, according to the present embodiment, in the step of forming the impurity doped region 26 shown in FIG. 3, the impurity doped region 26 is not formed in the portion of the barrier layer 24 where the gate electrode 29 is formed. . In the step of forming the gate electrode 29 shown in FIG. 6, the gate electrode 29 is formed on the barrier layer 24 between the impurity doping regions 26.

  Accordingly, the barrier layer 24 in the gate region is not subjected to a treatment such that a damage layer is formed at the interface between the barrier layer 24 in the gate region and the gate electrode 29 and the barrier layer 24. The semiconductor device 101 including the transistor 1 in which the 26 is not formed can be manufactured. In other words, in the barrier layer 24, the gate region of the gate region is not subjected to a treatment such that a damage layer is formed at the barrier layer 24 in the gate region and the interface between the gate electrode 29 and the barrier layer 24. The semiconductor device 101 including the transistor 1 can be obtained in which the concentration of the level formation impurity in at least a portion is lower than the concentration of the level formation impurity in at least a portion of the other region except the gate region of the barrier layer 24.

  The semiconductor device 101 of this embodiment having such a configuration can realize the normally-off operation of the transistor 1 as described above. Therefore, it is possible to obtain the semiconductor device 101 including the transistor 1 that can realize the normally-off operation by suppressing the formation of the damage layer at the barrier layer 24 in the gate region and the interface between the gate electrode 29 and the barrier layer 24. it can.

  Further, in the present embodiment, when the impurity doping region 26 is formed, the level forming impurity is doped by an ion implantation method. Thereby, the impurity doped region 26 can be easily formed in a desired region.

  The semiconductor device 101 of this embodiment and the manufacturing method thereof will be further described below. In the step of epitaxially growing the channel layer 23 and the barrier layer 24 shown in FIG. 2, the flow rate, pressure, and temperature of trimethylammonium, trimethylgallium, ammonia, etc., which are AlGaN source gases, are adjusted, and the channel layer 23 and the barrier layer 24 are desired. The composition is as follows. Thereby, the semiconductor device 101 including the transistor 1 having various characteristics can be manufactured.

The channel layer 23 and the barrier layer 24 may be any material that can form a heterojunction in which polarization occurs in the barrier layer 24. For example, the channel layer 23 is made of In _a Al _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1), and the barrier layer 24 is made of In _c Al _d Ga _1-cd N (0 ≦ c ≦ 1, 0 ≦ d ≦ 1).

Among these, the case where the channel layer 23 is made of Al _b Ga _1-b N and the barrier layer 24 is made of Al _d Ga _1-d N is considered. However, b <d. In this case, since a large polarization effect is generated in the barrier layer 24, a high concentration two-dimensional electron gas can be generated at the heterointerface between the channel layer 23 and the barrier layer 24. Therefore, this structure is advantageous for increasing the current and further increasing the output of the transistor 1, and is a more preferable structure.

In the heterostructure field effect transistor 1, the breakdown voltage increases as the breakdown electric field of the semiconductor material used for the channel layer 23 increases. Al _b Ga _1-b N, the higher Al composition higher band gap is large, the dielectric breakdown electric field is high. Therefore, in the above structure, Al _b Ga _1-b N used for the channel layer 23 preferably has a higher Al composition, in other words, b is close to 1.

Further, as the band gap of the semiconductor material used for the barrier layer 24 is larger, the gate leakage current flowing from the gate electrode 29 to the hetero interface between the channel layer 23 and the barrier layer 24 through the barrier layer 24 becomes less likely to flow. Therefore, Al _d Ga _1-d N used as the barrier layer 24 is also preferably higher in Al composition. Specifically, when AlN, which is a case where _{d of} Al _d Ga _1-d N is 1, the leakage current can be reduced most.

  The channel layer 23 and the barrier layer 24 do not necessarily have a structure composed of a single layer having the same composition, and are a multilayer film composed of a plurality of layers having different In composition, Al composition, and Ga composition (a, b, c, d). It may be configured. In addition, each layer constituting the channel layer 23 and the barrier layer 24 may contain an impurity that functions as an n-type impurity or a p-type impurity with respect to the nitride semiconductor.

  In the step of forming the impurity doped layer 26 shown in FIG. 3, the case where the impurity doped region 26 is formed by the ion implantation method is shown, but the method of forming the impurity doped region 26 is not limited to this. For example, a material containing an element that becomes an impurity such as Si or O may be deposited in a desired region, and then annealed at a high temperature and thermally diffused. Alternatively, plasma treatment may be performed in an atmosphere containing an element that becomes an impurity. Alternatively, nitrogen vacancies may be formed by performing heat treatment in a low-pressure state to desorb nitrogen of the nitride semiconductor constituting the barrier layer 24.

  In the step of forming the impurity doped region 26 shown in FIG. 3, the formation of the resist pattern and the ion implantation are repeated several times while changing the resist pattern and the implantation conditions such as the implantation energy and the implantation amount. As a result, impurity doped regions 26, 32, 33 and 34 having various structures as shown in FIG. 1 described above and FIGS. 9, 10 and 11 described later can be formed.

  The three steps of forming the source electrode 27 and the drain electrode 28 shown in FIG. 4, the forming step of the element isolation region 25 shown in FIG. 5, and the forming step of the gate electrode 29 shown in FIG. Alternatively, the order of the steps may be changed. For example, the step of forming the element isolation region 25 may be performed before the step of forming the source electrode 27 and the drain electrode 28.

  FIG. 7 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the semiconductor device 102 according to another embodiment of the present invention, as shown in FIG. 7, the transistor 2 includes a spacer layer 30 between the channel layer 23 and the barrier layer 24 in the transistor 1 shown in FIG. It may be interposed. The spacer layer 30 is formed relatively thin. The thickness of the spacer layer 30 is, for example, 0.1 nm to 5 nm. The spacer layer 30 is made of a binary semiconductor such as indium nitride (InN), GaN, or AlN.

  Thus, by interposing the spacer layer 30 made of a binary semiconductor between the channel layer 23 and the barrier layer 24, the electron mobility at the heterointerface can be improved. Therefore, a large drain current can flow through the transistor 2.

  The semiconductor device 2 shown in FIG. 7 can be manufactured by forming the spacer layer 30 after forming the channel layer 23 and then forming the barrier layer 24 in the step shown in FIG. As with the channel layer 23 and the barrier layer 24, the spacer layer 30 is formed by, for example, epitaxial growth. The spacer layer 30 is formed of a binary semiconductor such as InN, GaN, or AlN. The spacer layer 30 is formed with a thickness of 0.1 nm to 5 nm, for example.

  FIG. 8 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the semiconductor device 102 according to another embodiment of the present invention, as shown in FIG. 8, the transistor 3 has a cap layer in which the region facing the gate electrode 29 in the barrier layer 24 in the transistor 1 shown in FIG. 31 may be covered. In the barrier layer 24, the region facing the gate electrode 29 is specifically a region between the impurity doping regions 26 in the surface portion on one side in the thickness direction of the barrier layer 24. The cap layer 31 is formed relatively thin. The thickness of the cap layer 31 is, for example, 0.1 nm to 5 nm. The cap layer 31 is made of, for example, GaN.

  By covering the region of the barrier layer 24 that faces the gate electrode 29 with the cap layer 31 in this way, the Schottky barrier of the gate electrode 29 is increased, so that the breakdown voltage of the transistor 3 can be increased.

  In the semiconductor device 3 shown in FIG. 8, the cap layer 31 is formed after the barrier layer 24 is formed in the step shown in FIG. 2, and then the barrier layer 24 and the cap layer 11 are formed in the step shown in FIG. It can be manufactured by forming the impurity doped region 26 in the predetermined region. Similar to the channel layer 23 and the barrier layer 24, the cap layer 31 is formed by, for example, epitaxial growth. The cap layer 31 is made of, for example, GaN. The cap layer 31 is formed with a thickness of 0.1 nm to 5 nm, for example.

  9 and 10 are cross-sectional views showing other examples of the semiconductor device of the present invention. In the semiconductor device 101 of the present embodiment shown in FIG. 1 described above, the impurity doping region 26 is formed up to the portion in contact with the source electrode 27 and the drain electrode 28 in the portion on the surface side of the barrier layer 24. In another embodiment of the present invention, the impurity doping region 32 is a region between the source electrode 27 and the gate electrode 29 in the portion on the surface side of the barrier layer 24 as shown in FIGS. It suffices if it is formed at least in part and in at least part of the region between the drain electrode 28 and the gate electrode 29.

  For example, in the transistor 4 of the semiconductor device 104 shown in FIG. 9, the impurity doping region 32 includes a part of the region between the source electrode 27 and the gate electrode 29 in the portion on the surface side of the barrier layer 24, and the drain electrode 28. And part of the region between the gate electrode 29 and the gate electrode 29. In other words, the impurity doping region 32 is formed in a region between the source electrode 27 and the gate electrode 29 with a distance from the source electrode 27 and the gate electrode 29. Further, the impurity doping region 32 is formed in a region between the drain electrode 28 and the gate electrode 29 and spaced from the drain electrode 28 and the gate electrode 29.

  In the transistor 5 of the semiconductor device 105 shown in FIG. 10, the impurity doping region 33 includes all regions between the source electrode 27 and the gate electrode 29 in the portion on the surface side of the barrier layer 24, and the drain electrode 28 and the gate. It is formed in all regions between the electrodes 29.

  If the impurity doping regions 32 and 33 are formed in at least a part of the region between the source electrode 27 and the gate electrode 29 and at least a part of the region between the drain electrode 28 and the gate electrode 29, The resistance between the source electrode 27 and the drain electrode 28 can be lowered by increasing the two-dimensional electron gas concentration. Therefore, as shown in FIGS. 9 and 10, the impurity doping regions 32 and 33 are at least a part of the region between the source electrode 27 and the gate electrode 29 and the region between the drain electrode 28 and the gate electrode 29. What is necessary is just to be formed in at least one part.

  Comparing the structures shown in FIGS. 9 and 10, as shown in FIG. 10, all regions between the source electrode 27 and the gate electrode 29 and all regions between the drain electrode 28 and the gate electrode 29 are shown. When the impurity-doped region 33 is formed, the resistance between the source electrode 27 and the drain electrode 28 is made lower than when the impurity-doped region 32 is formed in a part of the region as shown in FIG. Can do. Therefore, from the viewpoint of reducing the resistance between the source electrode 27 and the drain electrode 28, as shown in FIG. 10, the entire region between the source electrode 27 and the gate electrode 29, and the drain electrode 28 and the gate are arranged. A structure in which the impurity doping region 33 is formed in all regions between the electrode 29 is preferable.

  Comparing the structure shown in FIGS. 9 and 10 with the structure shown in FIG. 1 described above, the contact resistance is lower when the two-dimensional electron gas concentration in the portion of the barrier layer 24 in contact with the source electrode 27 and the drain electrode 28 is higher. can do. Therefore, as shown in FIG. 1, a structure in which an impurity doping region 26 is also formed in the barrier layer 24 in contact with the source electrode 27 and the drain electrode 28 is preferable.

  The semiconductor device 104 shown in FIG. 9 and the semiconductor device 105 shown in FIG. 10 are different from the semiconductor device 101 of the present embodiment shown in FIGS. 2 to 6 except that the region where the impurity doping region 32 is formed is different. It can be manufactured in the same manner as the manufacturing method.

  FIG. 11 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the transistor of the semiconductor device 106 according to another embodiment of the present invention, the impurity doping region 34 is formed inside the barrier layer 24.

  If the impurity doping region 26 shown in FIG. 1 is formed on the surface side of the barrier layer 24 with respect to the heterointerface where the two-dimensional electron gas is generated, it becomes a source of the two-dimensional electron gas under the effect of polarization. Therefore, the impurity doping region does not necessarily have to be formed on the outermost surface of the portion on the surface side of the barrier layer 24 as in the impurity doping region 26 shown in FIG. 1, and the barrier layer as in the impurity doping region 34 shown in FIG. 24 may be formed inside.

  Impurity levels formed in the impurity doping regions 26 and 34 are more susceptible to polarization as they are closer to the surface of the barrier layer 24, and deeper energy levels are also depleted, which easily becomes a source of two-dimensional electron gas. In addition, the impurity doping regions 26 and 34 are more likely to be a scattering factor of the two-dimensional electron gas as they are closer to the heterointerface where the two-dimensional electron gas is generated.

  Therefore, it is preferable to form the impurity doping regions 26 and 34 shallowly in a region closer to the outermost surface of the surface side portion of the barrier layer 24. For example, when the structure shown in FIG. 1 is compared with the structure shown in FIG. 11, it is more preferable to form it on the outermost surface of the portion on the surface side of the barrier layer 24 like the impurity doping region 26 shown in FIG. The impurity doping region 34 shown is more preferable than being formed inside the barrier layer 24.

  The impurity doping region 34 shown in FIG. 11 can be formed by adjusting the implantation energy in the impurity doping region forming step shown in FIG.

  FIG. 12 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the transistor 7 of the semiconductor device 107 according to another embodiment of the present invention, at least a part of the region facing the source electrode 27 and the drain electrode 28 in the channel layer 23 and the barrier layer 24 which are epitaxial crystal layers has a high concentration. An n-type impurity region 35 may be formed. By forming the high-concentration n-type impurity region 35, the contact resistance between the source electrode 27 and the semiconductor layer and the contact resistance between the drain electrode 28 and the semiconductor layer can be reduced. Here, the semiconductor layer refers to a semiconductor layer formed on the substrate 21, and specifically refers to a channel layer 23 and a barrier layer 24.

  In the high-concentration n-type impurity region 35, the concentration of the n-type impurity is not necessarily constant, and the concentration may be distributed. The high concentration n-type impurity region 35 is preferably structured so that the concentration of the n-type impurity increases from the gate electrode 29 side to the drain electrode 28 side. With such a structure, when a high voltage is applied to the drain electrode 28, the electric field concentrated on the end of the gate electrode 29 on the drain electrode 28 side can be relaxed. Can be achieved.

  FIG. 13 is a cross-sectional view showing a state where the formation of the high concentration n-type impurity region 35 is completed. The semiconductor device 107 shown in FIG. 12 is manufactured by forming the high-concentration n-type impurity region 35 as shown in FIG. 13 before the step of forming the source electrode 27 and the drain electrode 28 shown in FIG. Can do.

  In the step of forming the high-concentration n-type impurity region 35 shown in FIG. 13, an ion implantation method or the like is used in a desired region of the barrier layer 24 and the channel layer 23 in which the impurity doping region 26 is formed, using a resist pattern or the like as a mask. Then, ions such as Si are implanted and doped. Next, after removing a mask such as a resist pattern, the doped ions are activated using an RTA (Rapid Thermal Annealing) method or the like. Thereby, a high concentration n-type impurity region 35 is formed.

  The high-concentration n-type impurity region 35 is formed in at least a part of a region facing the source electrode 27 and the drain electrode 28 in the channel layer 23 and the barrier layer 24. In the example shown in FIG. 12, the high-concentration n-type impurity region 35 is formed in the barrier layer 24 and the channel layer 23 in the region where the impurity doping region 26 is formed.

  The high concentration n-type impurity region 35 is not limited to the structure shown in FIG. The formation of the resist pattern and the ion implantation in the process shown in FIG. 13 are repeated a plurality of times by changing the resist pattern and the implantation conditions such as the implantation energy and the implantation amount, whereby high-concentration n-type impurity regions 35 having various structures are formed. Can be formed.

  FIG. 14 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the transistor 8 of the semiconductor device 108 according to another embodiment of the present invention, a recess may be formed in the barrier layer 50 in a region facing the source electrode 37 and the drain electrode 38. In the example shown in FIG. 14, a recess is formed in the impurity doping region 36 formed in a portion of the barrier layer 50 on the surface side of the barrier layer 50. A source electrode 37 and a drain electrode 38 are provided in this recess.

  With such a structure, the contact resistance between the source electrode 37 and the semiconductor layer, and the drain electrode 38 and the semiconductor layer are formed as in the case where the high concentration n-type impurity region 35 is formed as shown in FIG. Contact resistance can be reduced.

In the semiconductor device 108 shown in FIG. 14, a recess is formed in the barrier layer 24 before the step of forming the source electrode and the drain electrode shown in FIG. 4, and then the formation of the source electrode and the drain electrode shown in FIG. In the same manner as in the process, it can be manufactured by forming the source electrode 37 and the drain electrode 38 in the recess. The recess is formed by removing at least a part of the barrier layer 24 in the region where the source electrode 37 and the drain electrode 38 are to be formed, for example, by dry etching using ion milling or Cl ₂ .

  FIG. 15 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the transistor 9 of the semiconductor device 109 according to another embodiment of the present invention, the gate electrode 39 may overlap a part of the impurity doping region 26. Since all the impurities doped in the impurity doping region 26 are depleted by the polarization generated in the barrier layer 24, they do not cause a gate leakage current that is so large as to hinder the operation of the transistor 9. Therefore, the gate electrode 39 may overlap a part of the impurity doped region 26 as long as the entire region of the barrier layer 24 not doped with impurities is covered with the gate electrode 39.

  The semiconductor device 109 shown in FIG. 15 can be manufactured by forming a resist pattern used in the lift-off method in a desired region in the gate electrode formation step shown in FIG.

  FIG. 16 is a cross-sectional view showing another example of the semiconductor device of the present invention. In the transistor 10 of the semiconductor device 110 according to another embodiment of the present invention, an insulating film 40 is interposed between the gate electrode 29 and the barrier layer 24. Thus, the gate electrode 29 is not necessarily in direct contact with the barrier layer 24 and may be formed on the insulating film 40 formed on the barrier 24 layer. Thus, by providing the insulating film 40 between the gate electrode 29 and the barrier layer 24, the gate leakage current can be reduced.

  The insulating film 40 includes an oxide, nitride, or oxynitride of at least one atom selected from aluminum (Al), gallium (Ga), silicon (Si), hafnium (Hf), titanium (Ti), and the like. Consists of.

  FIG. 17 is a cross-sectional view illustrating a state in which the formation of the insulating film 40 has been completed. The semiconductor device 110 shown in FIG. 16 can be manufactured by forming the gate electrode 29 after forming the insulating film 40 before the step of forming the gate electrode 29 shown in FIG.

  Specifically, aluminum oxide (AlOx), silicon nitride, for example, using a vapor deposition method or a plasma CVD method so as to cover the barrier layer 24, the impurity doping region 26, the element isolation region 25, the source electrode 27, and the drain electrode 28. An insulating film 40 made of (SiNx), silicon oxide (SiOx), hafnium oxide (HfOx), titanium oxide (TiOx), or the like is deposited.

  Thereafter, the gate electrode 29 is formed on the insulating film 40 between the source electrode 27 and the drain electrode 28 in the same manner as the process shown in FIG. Next, a part of the insulating film 40 formed on the source electrode 27 and the drain electrode 28 is removed so that a part of the source electrode 27 and the drain electrode 28 is exposed. As a result, the semiconductor device 110 having the structure shown in FIG. 16 is obtained.

  18 and 19 are cross-sectional views showing other examples of the semiconductor device of the present invention. The insulating films 40 and 41 interposed between the gate electrode 29 and the barrier layer 24 cover the entire region of the barrier layer 24 between the source electrode 27 and the drain electrode 28 as shown in FIG. It is not necessary to form it, and it is sufficient that it is formed in at least a part of the region facing the gate electrode 29 of the barrier layer 24.

  For example, like the transistor 11 of the semiconductor device 111 shown in FIG. 18, the insulating film 41 is formed only between the gate electrode 29 and the barrier layer 24 so as to cover the entire region facing the gate electrode 29 of the barrier layer 24. May be. Further, like the transistor 12 of the semiconductor device 112 illustrated in FIG. 19, the insulating film 41 may be formed so as to cover a part of the barrier layer in the region facing the gate electrode 29.

  In the semiconductor device 111 shown in FIG. 18 and the semiconductor device 112 shown in FIG. 19, after forming the insulating film 41 in the same manner as the insulating film forming step shown in FIG. 17, the gate electrode 29 shown in FIG. It can be manufactured by forming the gate electrode 29 in the same manner as the forming step, and then removing the insulating film 41 formed outside the desired region. For example, after the gate electrode 29 is formed, the resist film or the gate electrode 29 itself is used as a mask, for example, wet etching using hydrofluoric acid, or fluorine gas is used to remove the insulating film 41 formed outside the desired region. It is performed by the plasma etching used.

  FIG. 20 is a cross-sectional view showing another example of the semiconductor device of the present invention. As in the gate electrode 29 shown in FIG. 1 described above, the gate electrode does not necessarily have a quadrangular cross-sectional shape in a virtual plane perpendicular to the substrate 21 (hereinafter may be simply referred to as “cross-sectional shape”). The gate electrode may have a shape in which the area of the region in contact with the barrier layer 24 is smaller than that in the case where the cross-sectional shape is a square shape.

  An example of such a shape is the shape shown in FIG. In the transistor 13 of the semiconductor device 113 according to another embodiment of the present invention shown in FIG. 20, the gate electrode 44 has a Y-shaped cross section.

  Compared with the case where the cross-sectional shape is a square shape, the gate electrode having a shape in which the area of the region in contact with the barrier layer 24 is small may have a Y-shaped cross-section as shown in FIG. The cross-sectional shape may be a T-shape.

  Thus, the area where the gate electrode is in contact with the barrier layer 24 is maintained by making the gate electrode into a shape in which the area of the region in contact with the barrier layer 24 is smaller than when the cross-sectional shape is a quadrangle. The cross-sectional area of the gate electrode perpendicular to the direction in which the gate current flows can be increased as compared with the case where the cross-sectional shape of the gate electrode is rectangular. Therefore, gate resistance can be reduced.

  FIG. 21 is a cross-sectional view showing a stage where the removal of a part of the insulating film 45 is completed. The semiconductor device 113 shown in FIG. 20 can be manufactured as follows. After the insulating film 45 is deposited in the same manner as the insulating film 40 shown in FIG. 17 described above, a part of the insulating film 45 is formed by, for example, plasma etching using a fluorine-based gas or wet etching using hydrofluoric acid. Remove. As shown in FIG. 21, in the insulating film 45, a part of the insulating film 45 in a region sandwiched between the source electrode 27 and the drain electrode 28, specifically, the impurity doping region 26 and the element isolation region 25 are not formed. A portion formed on the barrier layer 24 is removed.

  The gate electrode 44 is formed in the same manner as the formation process of the gate electrode 29 shown in FIG. 6 so as to fill the portion from which the insulating film 45 has been removed. Thereafter, all the insulating film 45 is removed by wet etching or the like. As a result, as shown in FIG. 20, the gate electrode 44 having a Y-shaped cross section is formed. A gate electrode having a T-shaped cross section can be formed in a similar manner.

  22 and 23 are cross-sectional views showing other examples of the semiconductor device of the present invention. In another embodiment of the present invention, insulating films 41 and 45 are provided in at least a part of a region between the portions of the gate electrodes 44 and 46 that are not in contact with the barrier layer 24 and the barrier layer 24. May be. The insulating films 41 and 45 are made of an oxide, nitride or oxynitride of at least one kind of atoms of Al, Ga, Si, Hf, Ti and the like.

  The transistor 14 of the semiconductor device 114 illustrated in FIG. 22 includes an insulating film between the barrier layer 24 and the portion of the gate electrode 44 that is not in contact with the barrier layer 24 in the transistor 13 of the semiconductor device 113 illustrated in FIG. 45 is provided. In the example illustrated in FIG. 22, the insulating film 45 covers a portion of the barrier layer 24 that is not in contact with the source electrode 27, the drain electrode 28, and the gate electrode 44, a portion of the source electrode 27, and a portion of the drain electrode 28. It is provided as follows.

  The transistor 15 of the semiconductor device 115 illustrated in FIG. 23 includes a gate electrode 46 having a U-shaped cross section instead of the gate electrode 44 in the transistor 13 of the semiconductor device 113 illustrated in FIG. Insulating film 41 is provided between 46 and barrier layer 24. In the example illustrated in FIG. 23, the insulating film 41 is provided in the entire region between the portion of the gate electrode 46 that is not in contact with the barrier layer 24 and the barrier layer 24.

  As described above, the structure in which the insulating films 41 and 45 are provided in at least a part of the region between the gate electrode 44 and 46 that is not in contact with the barrier layer 24 and the barrier layer 24 can provide a high voltage. When operated, the electric field concentrated on the end of the gate electrodes 44 and 46 on the drain electrode 28 side can be relaxed. Therefore, the breakdown voltage of the transistors 14 and 15 can be increased.

  The semiconductor device 114 shown in FIG. 22 can be manufactured as follows. Similarly to the semiconductor device 113 shown in FIG. 20, the gate electrode 44 is formed so as to fill the removed portion of the insulating film 45 shown in FIG. Thereafter, a part of the insulating film 45 formed on the source electrode 27 and the drain electrode 28 is removed so that a part of the source electrode 27 and the drain electrode 28 is exposed. As a result, the semiconductor device 114 shown in FIG. 22 is obtained.

  The semiconductor device 115 shown in FIG. 23 can be manufactured as follows. After the insulating film 45 is formed in the same manner as the insulating film forming step shown in FIG. 21, the insulating film 45 is not removed, and the gate electrode 29 is formed in the same manner as the gate electrode 29 forming step shown in FIG. An electrode 46 is formed. Thereafter, the insulating film 45 other than the portion between the gate electrode 46 and the barrier layer 24 is removed from the insulating film 45 by wet etching using hydrofluoric acid.

  By adjusting the processing conditions of wet etching using hydrofluoric acid, for example, the processing time and the concentration of the etchant such as hydrofluoric acid, the insulating film 45 in a desired region can be left, and the transistor having the structure shown in FIG. The semiconductor device 115 including 15 can be manufactured.

  The structures of the semiconductor devices 101 to 115 described above do not have to be individually adopted, and some structures or a combination of all structures may be used. Further, in the semiconductor devices 1 to 115 described above, only the minimum necessary elements that operate as a transistor are described, but finally, they are used as devices in a structure in which a protective film, a wiring, a via hole, and the like are formed. .

  1 to 15 transistor, 21 substrate, 22 buffer layer, 23 channel layer, 24, 50 barrier layer, 25 element isolation region, 26, 32, 33, 34, 36, 43 impurity doping region, 27, 37 source electrode, 28, 38 drain electrode, 29, 39, 42, 43, 46 gate electrode, 30 spacer layer, 31 cap layer, 35 high-concentration n-type impurity region, 40, 41, 45 insulating film, 101-115 semiconductor device.

Claims (4)

A semiconductor device comprising a heterojunction field effect transistor comprising a nitride semiconductor layer,
The heterojunction field effect transistor is
A first nitride semiconductor layer provided on the substrate;
A second nitride semiconductor provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer and forming a heterojunction with the first nitride semiconductor layer Layers,
A gate electrode, a source electrode and a drain electrode provided on the second nitride semiconductor layer;
The gate electrode is interposed between the source electrode and the drain electrode;
The second nitride semiconductor layer has a band discontinuity ΔEc at the heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer from the conduction band of the second nitride semiconductor layer. And an energy up to an energy (ΔEc + ΔEp) obtained by adding the energy difference ΔEp between the gate electrode side and the heterointerface side of the second nitride semiconductor layer due to polarization generated in the second nitride semiconductor layer An impurity that forms a level in the band gap of depth;
The concentration of the impurity in at least a part of the region facing the gate electrode in the second nitride semiconductor layer is at least a part of the other region except for the region facing the gate electrode of the second nitride semiconductor layer. A semiconductor device, wherein the concentration of the impurity is lower than that of the impurity.   2. The semiconductor device according to claim 1, wherein the second nitride semiconductor layer has a region containing the impurity in at least a part of the other region. A method of manufacturing a semiconductor device including a heterojunction field effect transistor including a nitride semiconductor layer,
A first layer forming step of forming a first nitride semiconductor layer on the substrate;
A second layer forming step of forming a second nitride semiconductor layer that forms a heterojunction with the first nitride semiconductor layer on the first nitride semiconductor layer;
An electrode forming step of forming a gate electrode, a source electrode and a drain electrode on the second nitride semiconductor layer,
In the electrode formation step, the gate electrode is formed so as to be interposed between the source electrode and the drain electrode,
Between the second layer forming step and the electrode forming step,
In the second nitride semiconductor layer, a region excluding at least a part of a region predetermined as a region for forming the gate electrode is removed from the conduction band of the second nitride semiconductor layer. A band discontinuity ΔEc at the heterointerface between the second nitride semiconductor layer and the gate electrode side of the second nitride semiconductor layer due to polarization generated in the second nitride semiconductor layer; A method of manufacturing a semiconductor device, comprising: a doping step of doping an impurity forming a level in a band gap having an energy depth up to an energy (ΔEc + ΔEp) obtained by adding an energy difference ΔEp with the heterointerface side .   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the doping step, the impurity is doped by an ion implantation method.

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