JP2011233612A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving withstand voltage and preventing short channel effect, and to provide a method of manufacturing the same.SOLUTION: The semiconductor device comprises: a buffer layer 2 formed on an SiC substrate 1 that is a semiconductor substrate; a channel layer 3 having a smaller band gap than the buffer layer 2, which is formed on the buffer layer 2; a barrier layer 4 having a larger band gap than the channel layer 3, which is formed on the channel layer 3; a source and a drain electrode 7 and 8 separately formed each other on the barrier layer 4; and an impurity region 5 extending from a bottom surface of the source and the drain electrode 7 and 8 to within the channel layer 3 through the barrier layer 4. The bottom edge of the impurity region 5 does not reach the buffer layer 2.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure of a heterojunction field effect transistor made of a semiconductor containing nitride.

  In a conventional heterojunction field-effect transistor made of a semiconductor containing nitride, when the gate length needs to be reduced as the frequency increases, a so-called short channel effect occurs in which the modulation effect of the two-dimensional electron gas by the gate decreases. To do.

  In order to suppress this, an epi structure that enhances the confinement of the two-dimensional electron gas is effective. By making the band gap of the semiconductor layer below the channel layer larger than that of the channel layer, A so-called double heterostructure (Non-patent Document 1) that improves confinement, and a thin layer (back barrier layer) with a small band gap and a channel layer are inserted into the channel layer, and the upper and lower layers of this back barrier layer (divided into two parts) Even if the band gap of the channel layer is the same, a notch is generated in the conduction band due to the polarization effect of the back barrier layer, and the two-dimensional electron gas is confined by the barrier formed by lifting the conduction band under the back barrier layer. So-called back barrier structure (Non-Patent Document 2) is reported.

IEEE IEDM Tech. Dig. , Pp. 807-810, 2004 IEEE Electron Device Lett. , Vol. 27, no. 1, pp. 13-15, 2006

  When a double heterostructure is applied to a heterojunction field effect transistor made of a nitride semiconductor, a channel band conduction band (conduction band) is raised because a layer having a larger band gap than the channel layer is formed below the channel layer. The two-dimensional electron gas concentration is reduced.

  In order to prevent this, the electron supply layer is made thicker or the electron supply layer is widened. However, this causes an increase in contact resistance with the source / drain electrode and parasitic resistance under the electrode, resulting in characteristic deterioration such as a decrease in drain current and an increase in on-resistance.

  Therefore, a low resistance region is formed below the source / drain electrode formation region. As a result, the contact resistance with the source / drain electrode and the parasitic resistance under the electrode can be reduced, resulting in improved characteristics such as an increase in drain current and a decrease in on-resistance.

  However, the formation of this low resistance region increases the drain current (drain leakage current) flowing through the interface between the channel layer and its lower layer in the off state, and the drain current characteristics at the gate voltage (off state) lower than the threshold ( There was a problem that deterioration of the sub-threshold characteristics) occurred.

  On the other hand, when a back barrier structure is applied to a heterojunction field effect transistor made of a nitride semiconductor, a conduction band (conduction band) under the back barrier is raised, and the two-dimensional electron gas concentration decreases.

  In order to prevent this, the electron supply layer is made thicker or the electron supply layer is widened. However, this causes an increase in contact resistance with the source / drain electrode and parasitic resistance under the electrode, resulting in characteristic deterioration such as a decrease in drain current and an increase in on-resistance.

  Therefore, a low resistance region is formed below the source / drain electrode formation region. As a result, the contact resistance with the source / drain electrode and the parasitic resistance under the electrode can be reduced, resulting in improved characteristics such as an increase in drain current and a decrease in on-resistance.

  However, the formation of the low resistance region increases the drain leakage current flowing through the back barrier layer in the off state, resulting in deterioration of the subthreshold characteristics in the off state. Furthermore, since the band gap of the back barrier layer inserted into the channel layer is small, the withstand voltage between the back barrier layer and the gate electrode decreases (increases the gate leakage current), resulting in deterioration of electrical characteristics and reliability. there were.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can improve the breakdown voltage and suppress the short channel effect.

  A semiconductor device according to the present invention is formed on a buffer layer formed on a semiconductor substrate, a channel layer formed on the buffer layer and having a smaller band gap than the buffer layer, and the channel layer. A barrier layer having a larger band gap than the channel layer; a source / drain electrode formed on the barrier layer and spaced apart from each other; and the channel layer from below the source / drain electrode through the barrier layer And an impurity region reaching the inside, and a lower end of the impurity region does not reach the buffer layer.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: (a) a step of forming a buffer layer on a semiconductor substrate; and (b) a channel layer having a smaller band gap than the buffer layer on the buffer layer. And (c) forming a barrier layer having a larger band gap than the channel layer on the channel layer; and (d) forming source and drain electrodes spaced apart from each other on the barrier layer. And (e) prior to the step (d), forming an impurity region that reaches the channel layer through the barrier layer from below the source and drain electrodes, respectively. In (e), the lower end of the impurity region is formed so as not to reach the buffer layer.

  According to the semiconductor device of the present invention, the buffer layer formed on the semiconductor substrate, the channel layer having a smaller band gap than the buffer layer, formed on the buffer layer, and formed on the channel layer The barrier layer having a larger band gap than the channel layer, the source and drain electrodes formed on the barrier layer so as to be separated from each other, and the source and drain electrodes from below and through the barrier layer An impurity region that reaches each of the channel layers, and the lower end of the impurity region does not reach the buffer layer, thereby making it possible to suppress the short channel effect and improve the withstand voltage by improving the sub-threshold characteristics. Improved characteristics and reliability.

  According to the method for manufacturing a semiconductor device of the present invention, (a) a step of forming a buffer layer on a semiconductor substrate; and (b) a channel having a band gap smaller than that of the buffer layer on the buffer layer. Forming a layer; (c) forming a barrier layer having a larger band gap than the channel layer on the channel layer; and (d) separating the source and drain electrodes from each other on the barrier layer. And (e) prior to the step (d), forming an impurity region reaching the channel layer through the barrier layer from below the source and drain electrodes, respectively. In the step (e), the lower end of the impurity region is formed so as not to reach the buffer layer, so that the short channel is improved by improving the subthreshold characteristic. Becomes possible to improve the suppression and pressure of the fruit, the transistor characteristics and reliability is improved.

It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the structure of heterojunction FET by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of heterojunction FET by Embodiment 2 of this invention.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is an example of the structure of a heterojunction field effect transistor (FET) made of a nitride semiconductor provided in the present invention.

  In FIG. 1, the lowest layer is a semi-insulating SiC substrate 1, on which a channel layer 3 made of GaN is formed via a buffer layer 2 made of AlGaN. Further thereon, a barrier layer 4 made of AlGaN is formed. At this time, the band gap of the buffer layer 2 is larger than the band gap of the channel layer 3, and the band gap of the barrier layer 4 is larger than the band gap of the channel layer 3. Further, the band gap of the barrier layer 4 can be configured to be larger than the band gap of the buffer layer 2.

  A plurality of element isolation regions 6 are selectively formed on the buffer layer 2. Further, a plurality of impurity regions 5 doped with Si, which is an n-type impurity, are formed from the barrier layer 4 to the channel layer 3 at a high concentration. On the impurity region 5, a source electrode 7 made of Ti / Al and a drain electrode 8 made of Ti / Al are formed separately from each other. A gate electrode 9 made of Ni / Au is formed in a region between the source electrode 7 and the drain electrode 8 on the barrier layer 4. The surface of the barrier layer 4 is covered with an insulating film 10.

The impurity concentration of the impurity region 5 is desirably equal to or higher than the concentration used when n-type GaN or AlGaN is intentionally formed during crystal growth, for example, 1 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or higher or higher concentration.

It is not necessary for such a high concentration of impurities to be distributed throughout the impurity region 5, and at least the barrier layer 4 and the channel layer 3, which are regions where electrons flow from the semiconductor surface under the source electrode 7 and the drain electrode 8. Any structure having a high impurity concentration of about 1 × 10 ¹⁸ cm ⁻³ or more in the region up to about 10 nm on the interface and the channel layer side may be used.

Further, the lower limit end in the vertical direction of the impurity region 5 is arranged at a position 10 nm or more away from the interface in the channel layer 3 above the interface between the buffer layer 2 and the channel layer 3. The drain leakage current flowing through the interface with the channel layer 3 can be reduced. Therefore, the concentration of the n-type impurity in the channel layer 3 and the buffer layer 2 (on the substrate side) below the high-concentration n-type impurity region 5 is the background impurity concentration of GaN that is not intentionally doped. For example, less than 5 × 10 ¹⁷ cm ⁻³ , more preferably less than 1 × 10 ¹⁶ cm ⁻³ or lower. The GaN background impurities include conductive crystal defects and impurities.

  In the double hetero structure which is a kind of structure for enhancing the confinement of the two-dimensional electron gas 11, the source / drain electrode 7 is formed by providing a structure having the low resistance n-type impurity region 5 under the source electrode 7 and the drain electrode 8. , 8 and the impurity region 5 and a low access resistance between the source / drain electrodes 7 and 8 and the two-dimensional electron gas 11 as well as the buffer layer 2 and the channel layer 3 in the off state. As a result, the drain leakage current flowing through the interface can be reduced, so that a good subthreshold characteristic can be obtained.

  Note that it is not always necessary to implant Si as the n-type impurity, and it is a condition that the n-type impurity is doped at a high concentration, and a material that forms an n-type impurity level in the nitride semiconductor (O , C, N vacancies, etc.) may be doped or formed.

  Although typical conditions are described in FIG. 1, similar effects can be obtained even under the following conditions.

<A-2. Modification>
<A-2-1. Modification 1>
First, a cap layer 100 made of a material (for example, GaN) having a smaller band gap than the barrier layer 4 may be formed on the barrier layer 4 in FIG. 1 (FIG. 2). By adopting such a structure, the valence band of the barrier layer 4 is lifted, and the barrier between the surface of the cap layer 100 and the two-dimensional electron gas 11 is increased, thereby causing depletion due to electrons trapped on the surface. The influence of the layer on the two-dimensional electron gas 11 can be reduced, and an effect of suppressing current collapse can be obtained.

  The cap layer 100 may be doped with n-type impurities as well as undoped, and not only the entire cap layer 100 is doped, but also the lower layer region of the cap layer 100 in the vicinity of the barrier layer 4. Alternatively, the n-type impurity may be doped only in the structure, and the upper layer region may be undoped.

<A-2-2. Modification 2>
Second, a spacer layer 110 made of a material (for example, AlN) having a larger band gap than the material forming these layers may be formed between the channel layer 3 and the barrier layer 4 in FIGS. FIG. 3). By adopting such a structure, the confinement effect of the two-dimensional electron gas 11 generated on the barrier layer 4 side of the channel layer 3 can be increased, so that the two-dimensional electron gas concentration increases and the alloy scattering also decreases. Thus, the transistor current can be increased, that is, the output can be increased.

<A-2-3. Modification 3>
Third, the buffer layer 2, the channel layer 3, the spacer layer 110, the barrier layer 4, and the cap layer 100 in FIGS. 1 to 3 have respective band gap sizes of Eg2, Eg3, Eg110, Eg4, and Eg100. In case,
Eg3 <Eg2 <Eg4 <Eg110, Eg100 <Eg4
If so, it is possible to more effectively operate the heterojunction field effect transistor and suppress the short channel effect by improving the confinement of the two-dimensional electron gas 11. Furthermore, the current collapse can be reduced by the cap layer 100, and the concentration and mobility of the two-dimensional electron gas 11 can be improved by the spacer layer 110.

Therefore, it is not necessarily required to be GaN, AlN, or AlGaN as shown in FIGS. 1 to 3, and a nitride semiconductor composed of at least two elements including N among Al, Ga, and N having different composition of constituent elements. For example, the nitride semiconductors constituting the buffer layer 2, the channel layer 3, the spacer layer 110, the barrier layer 4, and the cap layer 100 may be Al _X2 Ga _{1 -X2} N and Al _X3 Ga _{1 -X3, respectively.} N, Al _X110 Ga _{1 -X110} N, Al _X4 Ga _{1 -X4} N, Al _X100 Ga _{1 -X100} N
0 ≦ X2 <1, 0 ≦ X3 <1, 0 <X110 ≦ 1, 0 <X4 ≦ 1, 0 ≦ X100 <1, X3 <X2 <X4 <X110, X100 <X4
That is, the aforementioned five-layer band gap is
Eg3 <Eg2 <Eg4 <Eg110, Eg100 <Eg4
It is only necessary that the nitride semiconductor be configured to satisfy the above relationship. Furthermore, it is not always necessary to use a nitride semiconductor composed of at least two elements including N among the three elements of Al, Ga, and N. Of the added Al and Ga, it may be composed of at least two types of nitride semiconductors containing N.

<A-2-4. Modification 4>
Fourth, in the structure of the third modification, the buffer layer 2, the channel layer 3, the spacer layer 110, the barrier layer 4, and the cap layer 100 are composed of at least two elements including N among Al, Ga, and N. In the case of being composed of a nitride semiconductor (the structure shown in FIGS. 1 to 3 is an example thereof), a large polarization effect is generated in the barrier layer 4, so that a high concentration two-dimensional electron gas is formed on the barrier layer 4 side of the channel layer 3 11 can be generated. Therefore, it is advantageous for increasing the current and further increasing the output of the transistor, and can be said to be a more preferable structure.

<A-2-5. Modification 5>
Fifth, the withstand voltage of the heterojunction field effect transistor increases as the breakdown electric field of the semiconductor material used for the channel layer 3 increases. Since Al _X Ga _1-X N has a higher band gap and a higher dielectric breakdown electric field as the Al composition is higher, Al _x3 Ga _1-x3 N used for the channel layer 3 in the structure of Modification 4 has a higher Al composition X3. Is higher (X is close to 1). In addition, since the gate leakage current flowing from the gate electrode 9 to the hetero interface through the barrier layer 4 is less likely to flow through the barrier layer 4 as the band gap of the semiconductor material used for the barrier layer 4 is larger, Al _X4 Ga _{1 -X4} used as the barrier layer _4. Similarly, N is preferably higher in Al composition X4 (X3 <X4).

<A-2-6. Modification 6>
Sixth, the configuration of each of the buffer layer 2, the channel layer 3, the barrier layer 4, the spacer layer 110, and the cap layer 100 shown in FIGS. 1 to 3 does not necessarily have to be a single layer having the same composition. If the conditions of the band gap size shown in the structure of the modification 3 and the structure of the modification 5 are satisfied, the In composition, the Al composition, and the Ga composition may be spatially changed, or these layers may be different. A multilayer film consisting of several layers may be used. Further, these layers may contain an impurity that becomes n-type or p-type in the nitride semiconductor.

<A-2-7. Modification 7>
Seventh, the semi-insulating SiC substrate 1 in FIGS. 1 to 3 may be Si, sapphire, GaN, AlN, or the like.

<A-2-8. Modification 8>
Eighth, at least a part of the semiconductor layer below the source electrode 7 and the drain electrode 8 in FIGS. 1 to 3 may be removed as shown in FIG. With this structure, the resistance between the two-dimensional electron gas 11 generated on the barrier layer 4 side of the channel layer 3 and the source / drain electrodes 7 and 8 can be reduced, and the efficiency of the transistor can be increased. This is advantageous for increasing the output by increasing the current and is a more preferable structure.

  In FIG. 4, the region extending from the semiconductor surface to the vicinity of the lower layer of the barrier layer 4 is removed, but the limit in the depth direction to be removed is up to the interface between the channel layer 3 and the barrier layer 4, and the spacer layer 110 In the case of the structure provided with the above, by limiting the removal until the spacer layer 110 is removed, the above effect can be obtained if at least a part of the semiconductor layer below the source electrode 7 and the drain electrode 8 is removed. .

<A-2-9. Modification 9>
Ninth, the source / drain electrodes 7 and 8 in FIGS. 1 to 4 do not necessarily need to be Ti / Al. If ohmic characteristics are obtained, Ti, Al, Nb, Hf, Zr, Sr, Ni, It may be formed of a metal such as Ta, Au, Pt, V, Mo, W, or a multilayer film composed of these metals.

<A-2-10. Modification 10>
Tenth, the gate electrode 9 in FIGS. 1 to 4 suppresses current collapse as compared with the case where the gate electrode 9 is in contact with the surface of the barrier layer 4 unless the bottom surface of the gate electrode 9 is in contact with the surface of the barrier layer 4. can do. Similarly, in the case of the structure in which the cap layer 100 is provided, if the bottom surface of the gate electrode 9 is not in contact with the surface of the cap layer 100, current collapse is suppressed as compared with the case of being in contact with the surface of the cap layer 100. For example, a structure in contact with the inside of the barrier layer 4 (FIG. 5) or a structure in which the cap layer 100 is provided is in contact with the inside of the cap layer 100. The structure (FIG. 6) or the structure in which the cap layer 100 is provided may be a structure in which the cap layer 100 and the barrier layer 4 are in contact with each other (FIG. 7). However, in order to etch the etching depth of the semiconductor layer immediately below the gate electrode 9 with good controllability, it is preferable to use a difference in rate when etching layers having different structures, in which case FIG. A structure in which the bottom surface of the gate electrode 9 is in contact with the vicinity of the interface between the barrier layer 4 and the cap layer 100 is more preferable.

<A-2-11. Modification 11>
Eleventh, the gate electrode 9 in FIGS. 1 to 7 does not necessarily have a square cross section as shown in these drawings. For example, a gate electrode 91 having a T-type or Y-type structure as shown in FIG. It doesn't matter. With such a structure, the gate resistance can be reduced while maintaining the area where the gate electrode 91 is in contact with the semiconductor.

  Although FIG. 8 shows a structure in which the umbrella of the T-type gate electrode 91 is not in contact with the insulating film 10, a structure in which the umbrella of the T-type gate electrode 91 is in contact with the insulating film 10 is shown in FIG. Thus, the electric field concentrated on the edge portion of the gate electrode 91 on the drain electrode 8 side during high voltage operation can be relaxed, and current collapse can be suppressed and the breakdown voltage can be increased. Further, as shown in FIG. 10, the insulating film 10 is formed only under the umbrella of the gate electrode 91, and is generated between the source electrode 7 and the gate electrode 91 or between the gate electrode 91 and the drain electrode 8. Capacitance can be reduced, and gain and efficiency during high-frequency operation can be improved.

<A-2-12. Modification 12>
Twelfth, the insulating film 10 in FIGS. 1 to 10 is formed of an oxide, nitride, oxynitride, or the like of at least one atom among Al, Ga, Si, Hf, Ti, Zr, Ta, V, and the like. Alternatively, it may be formed of a multilayer film composed of these.

<A-2-13. Modification 13>
13thly, the gate electrodes 9 and 91 in FIGS. 1 to 10 are not necessarily made of Ni / Au, but metals such as Ti, Al, Pt, Au, Ni and Pd, IrSi, PtSi, NiSi _{2 and the} like. It may be formed of silicide, nitride metal such as TiN, WN, TaN, or a multilayer film composed of these.

<A-2-14. Modification 14>
14thly, it is not necessary to employ all the above-mentioned structures individually, and for example, a structure combining them as shown in FIG. 11 may be used.

<A-2-15. Modification 15>
Fifteenth, the structure for improving the confinement of the two-dimensional electron gas 11 in the heterojunction field effect transistor made of a nitride semiconductor is not limited to that shown in FIG. 1, but in the channel layer 3 as shown in FIG. There is a structure in which a thin layer of a nitride semiconductor layer (back barrier layer 120) having a band gap smaller than that of the channel layer 3 is inserted. With this structure, even if the band gaps of the upper and lower channel layers 3 of the back barrier layer 120 are the same, a notch is generated in the conduction band due to the polarization effect of the back barrier layer 120, and the back barrier layer The confinement of the two-dimensional electron gas 11 can be improved by the barrier formed by lifting the lower conduction band of 120.

  For example, a buffer layer 2 made of GaN is formed on a semi-insulating SiC substrate 1, and a channel layer 3 made of GaN is formed on the buffer layer 2 made of InGaN via a back barrier layer 120 made of InGaN. A barrier layer 4 is formed. Similarly, in the heterojunction field effect transistor using this epi structure, the n-type impurity region 5 has a high concentration of Si as an n-type impurity in the semiconductor layer below the source electrode 7 and the drain electrode 8. A desired impurity concentration and distribution of the doped region are the same as in the case of the double hetero described with reference to FIG.

  However, when the impurity region 5 is formed in the InGaN back barrier structure, the lower limit end in the vertical direction of the impurity region 5 is disposed at a position 10 nm or more away from the interface between the buffer layer 2 and the back barrier layer 120, thereby The drain leakage current flowing through the interface between the layer 2 and the back barrier layer 120 can be reduced.

  Such a structure not only has a low contact resistance with the source / drain electrodes 7 and 8 and a low access resistance between the electrode and the two-dimensional electron gas 11, but also the back barrier layer 120 and the channel layer in the off state. 3 can reduce the drain leakage current flowing through the interface between the back barrier layer 120 and the gate electrode 9, and the breakdown voltage between the back barrier layer 120 and the gate electrode 9 having a small band gap can be improved.

  In addition, although the typical conditions were described in the said FIG. 12, even if the conditions of the above-mentioned modification 1-14 are applied, the same effect is acquired.

However, regarding the band gap of the third modification, for example, the nitride semiconductors constituting the buffer layer 2, the channel layer 3, the spacer layer 110, the barrier layer 4, the cap layer 100, and the back barrier layer 120 are Al _X2 Ga _{1− X2 N, Al X3 Ga 1-} X3 N, Al X110 Ga 1-X110 N, Al X4 Ga 1-X4 N, Al X100 Ga 1-X100 N, when the In _Y120 Ga _1-Y120 N,
0 ≦ X2 <1, 0 ≦ X3 <1, 0 <X110 ≦ 1, 0 <X4 ≦ 1, 0 ≦ X100 <1, 0 <Y120 ≦ 1, X3 ≦ X2 <X4 <X110, X100 <X4
And in terms of band gap,
Eg120 <Eg3 ≦ Eg2 <Eg4 <Eg110, Eg100 <Eg4
As long as it is made of a nitride semiconductor satisfying the above relationship, it may be made of at least two types of nitride semiconductors including N in Al and Ga to which In is added.

  Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device in a structure in which a protective film, a wiring, a via hole, and the like are formed.

<A-3. Effect>
According to the first embodiment of the present invention, in the semiconductor device, the buffer layer 2 formed on the SiC substrate 1 which is a semiconductor substrate and the band gap formed on the buffer layer 2 are larger than the buffer layer 2. A small channel layer 3, a barrier layer 4 having a larger band gap than the channel layer 3 formed on the channel layer 3, and source and drain electrodes 7 and 8 formed on the barrier layer 4 so as to be separated from each other , Impurity regions 5 respectively reaching the channel layer 3 through the barrier layer 4 from below the source and drain electrodes 7 and 8, and the lower end of the impurity region 5 does not reach the buffer layer 2. The drain leakage current flowing at the interface between the channel layer 3 and the channel layer 3 can be reduced, and the short channel effect can be suppressed and the breakdown voltage can be improved by improving the subthreshold characteristics. Register characteristics and reliability can be improved.

  In addition, according to the first embodiment of the present invention, the semiconductor device further includes the back barrier layer 120 disposed in the channel layer 3 and having a band gap smaller than that of the channel layer 3, and the lower end of the impurity region 5 is By not reaching the back barrier layer 120, the drain leakage current flowing through the interface between the back barrier layer 120 and the channel layer 3 can be reduced, and the short channel effect can be suppressed and the breakdown voltage can be improved by improving the subthreshold characteristics. Transistor characteristics and reliability are improved.

<B. Second Embodiment>
<B-1. Manufacturing method>
13 to 25 show an example of a manufacturing process of a heterojunction field effect transistor made of a nitride semiconductor having the structure shown in FIG. In these figures, the same reference numerals as those in FIGS. 1 to 12 denote the same or corresponding parts.

  First, as shown in FIG. 13, by applying an epitaxial growth method such as MOCVD method or MBE method on the SiC substrate 1, a buffer layer 2 made of AlGaN, a channel layer 3 made of GaN, and a barrier layer 4 made of AlGaN are respectively formed. Epitaxial growth is performed sequentially from the bottom.

  Buffer layer 2 is formed on SiC substrate 1, and channel layer 3 formed on buffer layer 2 has a smaller band gap than buffer layer 2. Further, the barrier layer 4 formed on the channel layer 3 has a band gap larger than that of the channel layer 3.

Next, as shown in FIG. 14, the resist pattern or the like is used as a mask 15 in at least a part of the semiconductor layer below the region where the source / drain electrodes 7 and 8 are formed (the channel layer 3 through the barrier layer 4). N-type in a nitride semiconductor under the conditions of an implantation dose of 1 × 10 ¹³ to 1 × 10 ¹⁷ (cm ⁻² ) and an implantation energy of 10 to 1000 (keV). Then, ions 16 such as Si are implanted into a desired region, and a high-concentration n-type impurity region 5 is formed by subsequent heat treatment. The impurity regions 5 reach the channel layer 3 through the barrier layer 4.

The impurity concentration of the impurity region 5 is desirably equal to or more than that used when intentionally forming n-type GaN or AlGaN during crystal growth, for example, 1 × 10 ¹⁸ cm ⁻³ or more, more preferably 1 × 10 ¹⁹ cm ⁻³ or higher or higher concentration.

One desirable distribution of impurities in the n-type impurity region 5 is that the interface between the barrier layer 4 and the channel layer 3 where electrons flow from the semiconductor surface under the source electrode 7 and the drain electrode 8 and the channel layer 3 side thereof. In particular, a structure having a high impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more in a region up to about 10 nm can be mentioned. As a method of determining the implantation amount and implantation energy for forming such an impurity distribution, Monte Carlo calculation is used. By simulating the ion range using the implantation energy and the structure of the irradiation object as parameters, the implantation energy and the implantation dose satisfying the above conditions can be determined.

Further, in order to prevent atoms (Al, Ga, In, N, etc.) constituting the barrier layer 4 from jumping into the vacuum by the implanted ions, a nitride film of about 10 to 100 nm on the barrier layer 4 After forming (SiN _x , AlN, etc.) or an oxide film (SiO ₂ , Al ₂ O _3, etc.), a resist pattern as an implantation mask may be formed. Thereafter, heat treatment is performed to activate the implanted ions, thereby reducing the resistance of the high-concentration n-type impurity region 5 below the source electrode 7 and the drain electrode 8. During this heat treatment, a nitride film (SiN _x , AlN, etc.) having a thickness of about 10 to 100 nm, an oxide film, etc. (SiO ₂ , Al ₂ , etc.) are formed on the barrier layer 4 to prevent nitrogen atoms from escaping from the semiconductor surface. Heat treatment may be performed after the nitride semiconductor surface is covered with O ₃ or the like.

  Next, as shown in FIG. 15, for example, a source made of a metal such as Ti, Al, Nb, Hf, Zr, Sr, Ni, Ta, Au, Pt, V, Mo, W, or a multilayer film composed of these metals. The electrode 7 and the drain electrode 8 are deposited using an evaporation method or a sputtering method, and formed by a lift-off method or the like. The source electrode 7 and the drain electrode 8 are formed separately from each other on the barrier layer 4 in which the impurity region 5 is formed. The contact resistance and access resistance may be further reduced by forming a reaction layer (alloy layer) with the semiconductor layer by performing a heat treatment after the electrodes are formed.

  Next, as shown in FIG. 16, for example, He, N, O, Mg, Ar, Ca, Fe, Zn, Sr, Ba, etc. The element isolation region 6 is formed using an ion implantation method of irradiating the ions 17 or etching. FIG. 16 shows a method using an ion implantation method.

Next, as shown in FIG. 17, Ti, Al, Pt, Au, Ni, metals such as Pd, or IrSi, PtSi, silicide such as NiSi _2, or TiN, WN, metal nitride such as TaN or from these, A gate electrode 9 composed of a multilayer film is deposited by vapor deposition or sputtering, and formed by lift-off or the like.

  Next, as shown in FIG. 18, at least one kind of oxide, nitride, oxynitride or the like of Al, Ga, Si, Hf, Ti, Zr, Ta, V, or the like is composed of these. An insulating film 10 made of a multilayer film is formed by a plasma CVD method, a cat-CVD method, or a sputtering method.

  By the above method, a heterojunction field effect transistor having the structure shown in FIG. 1 can be manufactured. Although only the minimum necessary elements that operate as a transistor are described above, the element is finally used as a device through a formation process of a protective film, a wiring, a via hole, and the like. In addition, as described above, as an example of the order of the manufacturing process after producing the epicrystal, the formation of the low resistance layer under the source / drain electrode and the electrode formation thereon, the element isolation formation, the gate electrode formation, and the insulating film formation are described in this order. However, element isolation may be performed after forming the gate electrode, or an insulating film may be formed and the gate electrode may be formed after removing the insulating film in the gate formation region, and element isolation is performed after the insulating film is formed. The gate electrode may be formed after removing the insulating film in the gate formation region.

  Although typical conditions have been described above, a heterojunction field effect transistor made of a nitride semiconductor that can achieve the effects of the present invention can be manufactured even under the following conditions.

<B-2. Modification>
<B-2-1. Modification 1>
First, if the cap layer 100 made of a material having a smaller band gap than the material forming the barrier layer 4 is continuously formed after the barrier layer 4 shown in FIG. 13 is grown, the first modification of the first embodiment will be described. A nitride semiconductor heterojunction field effect transistor having a structure as shown in FIG. 2 can be manufactured.

<B-2-2. Modification 2>
Second, after the channel layer 3 shown in FIG. 13 is grown, the spacer layer 110 made of a material having a larger band gap than the material forming the barrier layer 4 is formed, and then the barrier layer 4 and the cap layer 100 are formed continuously. Then, the nitride semiconductor heterojunction field effect transistor having the structure shown in FIG. 3 according to the second modification of the first embodiment can be manufactured.

<B-2-3. Modification 3>
Third, when growing the buffer layer 2, the channel layer 3, the barrier layer 4, the cap layer 100, and the spacer layer 110 shown in FIG. 13, trimethylammonium, trimethylgallium, trimethylindium, ammonia, which is a source gas of the nitride semiconductor, Alternatively, the flow rate, pressure, temperature, and time of silane that is a source gas of the n-type dopant are adjusted, so that the buffer layer 2, the channel layer 3, the barrier layer 4, the cap layer 100, and the spacer layer 110 have a desired composition and thickness. By setting the doping concentration, various nitride semiconductor heterojunction field effect transistors shown in Modifications 1 to 6 and 15 in Embodiment 1 can be manufactured.

<B-2-4. Modification 4>
Fourth, before the ion implantation to be an n-type impurity into source / drain electrodes 7 and 8 forming region shown in FIG. 14, as shown in FIG. 19, a resist pattern such as a mask 15, using a Cl ₂ or the like As shown in FIG. 4 of Modification 8 of Embodiment 1, by removing at least a part of the semiconductor layer below the region where the source electrode 7 and the drain electrode 8 are formed by dry etching or the like. A nitride semiconductor heterojunction field effect transistor having a simple structure can be manufactured. Note that the low resistance layer forming step below the formation region of the source / drain electrodes 7 and 8 may be performed before or after this etching step. The source / drain electrodes 7 and 8 are formed on the low resistance layer by a lift-off method or the like, and a nitride semiconductor heterojunction field effect transistor having a structure as shown in FIG. 4 can be manufactured.

<B-2-5. Modification 5>
Fifth, before forming the gate electrode 9 shown in FIG. 17, the barrier layer in the gate formation region 13 in which the gate electrode 9 is formed by a dry etching method using Cl ₂ or the like using the resist pattern or the like as a mask 15. 4 is removed (FIG. 20). When performing etching, the etching time and gas flow rate are adjusted to form a desired etching depth, and then the gate electrode is formed by the method shown in FIG. A nitride semiconductor heterojunction field effect transistor having a recess depth as shown in FIG. 5 can be manufactured. In addition, before forming the gate electrode 9 shown in FIG. 17 in the structure in which the cap layer 100 is provided, the gate is formed by a dry etching method using Cl ₂ or the like using the resist pattern or the like as a mask 15 in the same manner as the above manufacturing method. The cap layer 100 in the gate formation region 13 for forming the electrode 9 is removed (FIG. 21). At this time, when the Al composition ratios of the cap layer 100 and the barrier layer 4 are different, in addition to a chlorine-based gas such as Cl ₂ , for example, a fluorine-based gas such as oxygen or SF ₆ is used during etching. This makes it possible to selectively etch only the cap layer 100 and improve the controllability of the etching depth. Furthermore, the etching may be performed to a desired depth of not only the cap layer 100 but also the barrier layer 4 (FIG. 22), and then the gate electrode is formed by the method shown in FIG. 10, nitride semiconductor heterojunction field effect transistors having various recess depths shown in FIGS. 6 and 7 can be fabricated.

<B-2-6. Modification 6>
Sixth, before forming the gate electrode in FIG. 17, the surface of the semiconductor is formed of Al, Ga, Si, Hf, Ti, Zr, Ta, V, etc. by using, for example, vapor deposition, plasma CVD, Cat-CVD, or the like. Among them, an insulating film 10 made of oxide, nitride, oxynitride or the like containing at least one kind of atoms is deposited, and a resist mask or oxide film mask having an opening in the gate formation region 13 for forming the gate electrode 9 is used. Then, the insulating film 10 in the gate formation region 13 is removed by dry etching or wet etching (FIG. 23). After removing the mask, an electrode metal to be a gate metal is deposited by an evaporation method using a resist pattern having an opening wider than the opening of the insulating film 10 opened by etching, and a gate electrode 91 is formed by a lift-off method or the like. Thus, the nitride semiconductor field effect transistor having the structure shown in FIG. 9 according to the eleventh modification of the first embodiment can be manufactured.

  For final use as a device, a part of the insulating film 10 covering the source / drain electrodes 7 and 8 must be removed by wet etching using, for example, hydrofluoric acid, and then wiring must be formed. There is. Further, an insulating film that can be easily removed by wet etching after forming the insulating film 10, for example, an insulating film 210 such as SiO is formed. The insulating film 210 and the insulating film 10 in the gate forming region 13 are sequentially removed by dry etching or wet etching through a resist mask or an oxide film mask having an opening in the gate forming region 13 for forming the gate electrode 9 (FIG. 24). ). After removing the mask, an electrode metal serving as a gate metal is deposited by an evaporation method using the insulating pattern 210 opened by etching and a resist pattern having an opening wider than the opening of the insulating film 10, and the gate electrode 91 is formed by a lift-off method or the like. Form. The insulating film 210 that is easily wet-etched is removed by, for example, buffered hydrofluoric acid, so that the insulating film 210 under the gate electrode 91 is not present, and the structure of the modification 11 in Embodiment 1 shown in FIG. A nitride semiconductor field effect transistor can be manufactured.

  Further, the nitride semiconductor field effect type having the structure shown in FIG. 10 of the modification 11 in the first embodiment in which the insulating film 210 in a desired region is left by adjusting the processing conditions (time and concentration) of the wet etching. A transistor can be manufactured.

<B-2-7. Modification 7>
Seventh, after the gate recess structure described in Modification 5 of Embodiment 2 is formed, the gate shape described in Modification 6 of Embodiment 2 may be formed.

<B-2-8. Modification 8>
Eighth, formation of the impurity region 5 and the source electrode 7 and the drain electrode 8 which are low resistance regions under the source / drain electrode formation region shown in FIGS. 14 and 15, and formation of the element isolation region 6 shown in FIG. The steps of forming the gate electrode 9 shown in FIG. 17 and forming the insulating film 10 shown in FIG. 18 are not necessarily performed in this order, and the order of the steps may be changed. For example, the element isolation region 6 may be formed before the source / drain electrodes 7 and 8 are formed. Further, the gate electrode 9 may be formed after the insulating film 10 is formed.

<B-2-9. Modification 9>
Ninth, it is not necessary to adopt all the processes described above, and a structure as shown in FIG. 11 can be formed by a process combining them.

<B-2-10. Modification 10>
Tenth, by applying an epitaxial growth method such as MOCVD or MBE on the SiC substrate 1, a buffer layer 2 made of GaN, a channel layer 3 made of GaN, a back barrier layer 120 made of InGaN, and a barrier made of AlGaN. By epitaxially growing the layers 4 sequentially from the bottom (FIG. 25), a nitride semiconductor heterojunction field effect transistor having a structure as shown in FIG. 12 according to the modified example 15 of the first embodiment can be produced. . The back barrier layer 120 has a smaller band gap than the channel layer 3 and is disposed in the channel layer 3.

<B-2-11. Modification 11>
Eleventh, this embodiment has a layer structure in which the buffer layer 2, the back barrier layer 120, the channel layer 3, and the barrier layer 4 made of a nitride semiconductor satisfy the band gap relationship described in the modification 15 in the first embodiment. The nitride semiconductor heterojunction field effect transistor of Modification 15 of Embodiment 1 can be manufactured by epitaxial growth using the method described in Modification 10 of Embodiment 2.

<B-2-12. Modification 12>
Twelfth, a nitride semiconductor heterojunction is formed on the epitaxial substrate having the layer structure described in Modifications 10 and 11 of the Second Embodiment by using the methods of Modifications 1 to 9 of the Second Embodiment. A field effect transistor can be manufactured.

<B-3. Effect>
According to the second embodiment of the present invention, in the method of manufacturing a semiconductor device, (a) a step of forming the buffer layer 2 on the SiC substrate 1 that is a semiconductor substrate, and (b) on the buffer layer 2. Forming a channel layer 3 having a smaller band gap than the buffer layer 2; (c) forming a barrier layer 4 having a larger band gap than the channel layer 3 on the channel layer 3; and (d) a barrier layer. Step of forming source and drain electrodes 7 and 8 spaced apart from each other on 4 and (e) Prior to step (d), channel layer through source and drain electrodes 7 and 8 through barrier layer 4 from below 3, and forming the impurity region 5, each reaching the inside of the buffer layer 2. In step (e), the lower end of the impurity region 5 is formed so as not to reach the buffer layer 2, so that the buffer layer 2 and the channel layer are formed. 3 and Reducing the drain leakage current flowing through the interface, the sub-threshold characteristics improve suppression and pressure of short channel effect due to the improvement of the enabling transistor characteristics and reliability are improved.

  Further, according to the second embodiment of the present invention, in the method for manufacturing a semiconductor device, (f) the band gap is smaller than the channel layer 3 disposed in the channel layer 3 prior to the step (c). The step of forming the back barrier layer 120 is further provided. In step (e), the lower end of the impurity region 5 is formed so as not to reach the back barrier layer 120, so that the back barrier layer 120 and the channel layer 3 are formed. The drain leakage current flowing through the interface is reduced, the short channel effect can be suppressed and the breakdown voltage can be improved by improving the subthreshold characteristics, and the transistor characteristics and reliability are improved.

  1 SiC substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 impurity region, 6 element isolation region, 7 source electrode, 8 drain electrode, 9,91 gate electrode, 10,210 insulating film, 11 two-dimensional electron gas , 13 Gate formation region, 15 mask, 16, 17 ions, 100 cap layer, 110 spacer layer, 120 back barrier layer.

Claims (4)

A buffer layer formed on a semiconductor substrate;
A channel layer formed on the buffer layer and having a smaller band gap than the buffer layer;
A barrier layer formed on the channel layer and having a larger band gap than the channel layer;
Source and drain electrodes formed on the barrier layer and spaced apart from each other;
Impurity regions that respectively reach the channel layer through the barrier layer from below the source and drain electrodes,
The lower end of the impurity region does not reach the buffer layer;
Semiconductor device. A back barrier layer disposed in the channel layer and having a smaller band gap than the channel layer;
The lower end of the impurity region does not reach the back barrier layer;
The semiconductor device according to claim 1. (A) forming a buffer layer on the semiconductor substrate;
(B) forming a channel layer having a smaller band gap than the buffer layer on the buffer layer;
(C) forming a barrier layer having a larger band gap than the channel layer on the channel layer;
(D) forming a source electrode and a drain electrode spaced apart from each other on the barrier layer;
(E) prior to the step (d), forming an impurity region that reaches the channel layer through the barrier layer from below the source and drain electrodes, respectively.
In the step (e), the lower end of the impurity region is formed so as not to reach the buffer layer.
A method for manufacturing a semiconductor device. (F) Prior to the step (c), further comprising a step of forming a back barrier layer disposed in the channel layer and having a smaller band gap than the channel layer,
In the step (e), a lower end of the impurity region is formed so as not to reach the back barrier layer.
A method for manufacturing a semiconductor device according to claim 3.

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