JP2013232557A - Silicon carbide semiconductor element manufacturing method - Google Patents

Silicon carbide semiconductor element manufacturing method Download PDF

Info

Publication number
JP2013232557A
JP2013232557A JP2012104224A JP2012104224A JP2013232557A JP 2013232557 A JP2013232557 A JP 2013232557A JP 2012104224 A JP2012104224 A JP 2012104224A JP 2012104224 A JP2012104224 A JP 2012104224A JP 2013232557 A JP2013232557 A JP 2013232557A
Authority
JP
Japan
Prior art keywords
silicon carbide
electrode
metal
contact
titanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012104224A
Other languages
Japanese (ja)
Other versions
JP6156814B2 (en
Inventor
Kenji Fukuda
憲司 福田
Noriyuki Iwamuro
憲幸 岩室
Masahide Goto
雅秀 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, National Institute of Advanced Industrial Science and Technology AIST filed Critical Fuji Electric Co Ltd
Priority to JP2012104224A priority Critical patent/JP6156814B2/en
Publication of JP2013232557A publication Critical patent/JP2013232557A/en
Application granted granted Critical
Publication of JP6156814B2 publication Critical patent/JP6156814B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To form an ohmic electrode which can ensure adhesion of the electrode by inhibiting release of carbon while ensuring an ohmic property.SOLUTION: A silicon carbide semiconductor element manufacturing method comprises a process of forming a contact electrode on a silicon carbide substrate 1. In the process of forming the contact electrode, metal (pure metal or alloy which includes any one or more among titanium, zirconium and hafnium) which easily generates carbide and also easily generates nitride is used as an electrode chief material of the contact electrode and thermal annealing is performed in an atmosphere consisting primarily of nitrogen thereby to convert in thermal annealing, the metal in the electrode material of the contact electrode in a region of a contact hole 9 where the silicon carbide substrate 1 and the metal in the contact electrode material directly contact each other to a mixed layer 12 which includes both of carbide and nitride.

Description

本発明は、単結晶の炭化珪素基板を用いた炭化珪素半導体素子の製造方法に関し、特に、高耐圧縦型デバイスとして製造する炭化珪素半導体素子の製造方法に関する。   The present invention relates to a method for manufacturing a silicon carbide semiconductor device using a single crystal silicon carbide substrate, and more particularly to a method for manufacturing a silicon carbide semiconductor device manufactured as a high breakdown voltage vertical device.

単結晶炭化珪素(SiC)は、単結晶シリコン(Si)を大幅に上回るバンドギャップや破壊電界強度を有し、単体で耐圧10kVを超える超高耐圧半導体素子を実現することができると期待されている。炭化珪素半導体素子の製造プロセスでは、オーミック電極を形成する際、金属薄膜を堆積し、アルゴンなどの不活性ガス中で1000℃程度の熱アニールを行うのが、最も簡便であるとされている。上記金属の材料としては、現在のところニッケル(Ni)系が一般的である(例えば、下記非特許文献1参照。)。   Single crystal silicon carbide (SiC) has a band gap and breakdown electric field strength that are significantly higher than single crystal silicon (Si), and is expected to be able to realize an ultrahigh breakdown voltage semiconductor device exceeding a breakdown voltage of 10 kV by itself. Yes. In the manufacturing process of a silicon carbide semiconductor element, it is most convenient to deposit a metal thin film and perform thermal annealing at about 1000 ° C. in an inert gas such as argon when forming an ohmic electrode. Currently, nickel (Ni) is generally used as the metal material (for example, see Non-Patent Document 1 below).

オーミック電極形成の熱アニールの際、ニッケルと炭化珪素との組み合わせからは珪化ニッケルしか生成されないため、余った炭素がグラファイトの形で電極の内部や表面に析出し、コンタクト抵抗の増大、電極の密着性の低下、といった問題の原因になることが知られている。解決策の一つとして、チタンなど炭化物を生成し易い金属をニッケルと共に予め堆積しておき、これをグラファイトと反応させる、という手法が開発されている(例えば、下記特許文献1,2参照。)。   During thermal annealing for ohmic electrode formation, only nickel silicide is produced from the combination of nickel and silicon carbide, so excess carbon precipitates in the interior and surface of the electrode in the form of graphite, increasing contact resistance and electrode adhesion. It is known to cause problems such as deterioration of sex. As one of the solutions, a technique has been developed in which a metal that easily generates carbides such as titanium is deposited together with nickel and reacted with graphite (see, for example, Patent Documents 1 and 2 below). .

特開2000−208438号公報JP 2000-208438 A 特開2006−344688号公報JP 2006-344688 A

佐治学、安田和人、早川俊高:電気学会研究会資料、EFM−90、17−23号、pp.31−33、1990年Saji Manabu, Yasuda Kazuto, Hayakawa Toshitaka: Material of the Institute of Electrical Engineers of Japan, EFM-90, No. 17-23, pp. 31-33, 1990

しかし、一般的な半導体素子の製造工程において、配線同士の電気的な分離に用いられる、二酸化珪素を主成分とする堆積膜(層間絶縁膜)と、上記のチタンやニッケルといった金属が直接接触している部分があると、熱アニールの条件によっては、金属が層間絶縁膜を分解しながら拡散し、下地の基板まで達してしまうことがある(スパイク現象と呼ぶ)。層間絶縁膜に設けた開口部にのみ金属を残し、不要な部分を薬液エッチングあるいはドライエッチングで除去すれば、このような問題は起こらないが、これらの手法では、フォトリソグラフィ工程の位置合わせ精度が要求され、エッチングに伴い金属有効線幅が減少するという問題が生じるため、プロセスルールの微細化を達成できなくなる。   However, in a general semiconductor device manufacturing process, a deposited film (interlayer insulating film) mainly composed of silicon dioxide, which is used for electrical isolation between wirings, and the metal such as titanium and nickel are in direct contact with each other. If there is a portion, the metal may diffuse while decomposing the interlayer insulating film depending on the thermal annealing conditions, and may reach the underlying substrate (referred to as a spike phenomenon). If the metal is left only in the opening provided in the interlayer insulating film and unnecessary portions are removed by chemical etching or dry etching, such a problem does not occur. However, in these methods, the alignment accuracy of the photolithography process is improved. As a result, there arises a problem that the effective metal line width decreases with etching, so that it is impossible to achieve fine process rules.

本発明は、上記課題に鑑み、オーミック特性を確保しつつ、炭素の遊離を抑制して電極の密着性を確保できるオーミック電極を形成できる炭化珪素半導体素子の製造方法を提供することを目的とする。   In view of the above-described problems, an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor element capable of forming an ohmic electrode capable of suppressing the liberation of carbon and ensuring the adhesion of the electrode while ensuring ohmic characteristics. .

上記目的を達成するため、本発明の炭化珪素半導体素子の製造方法は、単結晶の炭化珪素基板を用いた炭化珪素半導体素子の製造方法において、前記炭化珪素基板にコンタクト電極を形成する工程を含み、当該コンタクト電極を形成する工程は、前記コンタクト電極として、炭化物を生成し易くかつ窒化物も生成し易い金属を電極主材料として用い、窒素を主成分とする雰囲気中で熱アニールを行い、前記炭化珪素基板と前記コンタクト電極の材料の金属とが直接接触しているコンタクトホールの領域において、当該熱アニール時に前記コンタクト電極の材料の金属を炭化物と窒化物の両方を含む混合物に変換することを特徴とする。   In order to achieve the above object, a method for manufacturing a silicon carbide semiconductor device of the present invention includes a step of forming a contact electrode on the silicon carbide substrate in a method for manufacturing a silicon carbide semiconductor device using a single crystal silicon carbide substrate. The step of forming the contact electrode uses, as the contact electrode, a metal that easily generates carbides and nitrides as an electrode main material, and performs thermal annealing in an atmosphere containing nitrogen as a main component, In the region of the contact hole where the silicon carbide substrate and the metal of the contact electrode material are in direct contact, the metal of the contact electrode material is converted into a mixture containing both carbide and nitride during the thermal annealing. Features.

また、前記コンタクト電極材料の金属が、チタン、ジルコニウム、ハフニウムの内いずれか1種類以上を含む純金属もしくは合金であることを特徴とする。   The metal of the contact electrode material is a pure metal or alloy containing any one or more of titanium, zirconium, and hafnium.

上記構成によれば、炭化珪素基板とコンタクト電極の材料の金属とが直接接触しているコンタクトホールの領域において、熱アニール時にコンタクト電極の材料の金属を炭化物と窒化物の両方を含む混合物に変換する。これにより、ニッケルを用いなくても実用に足る低コンタクト抵抗を確保でき、かつ層間絶縁膜中にスパイクを起こさない。   According to the above configuration, in the contact hole region where the silicon carbide substrate and the metal of the contact electrode are in direct contact, the metal of the contact electrode is converted into a mixture containing both carbide and nitride during thermal annealing. To do. As a result, a practically low contact resistance can be ensured without using nickel, and no spike is caused in the interlayer insulating film.

本発明によれば、オーミック特性を確保しつつ、炭素の遊離を抑制して電極の密着性を確保できるオーミック電極を得られるという効果を奏する。   According to the present invention, it is possible to obtain an ohmic electrode that can ensure the adhesion of the electrode by suppressing the liberation of carbon while ensuring the ohmic characteristics.

この発明の実施の形態における炭化珪素半導体素子の電極の製造工程を示す断面図である(その1)。It is sectional drawing which shows the manufacturing process of the electrode of the silicon carbide semiconductor element in embodiment of this invention (the 1). この発明の実施の形態における炭化珪素半導体素子の電極の製造工程を示す断面図である(その2)。It is sectional drawing which shows the manufacturing process of the electrode of the silicon carbide semiconductor element in embodiment of this invention (the 2). この発明の実施の形態における炭化珪素半導体素子の電極の製造工程を示す断面図である(その3)。FIG. 7 is a cross sectional view showing a step for manufacturing an electrode for a silicon carbide semiconductor device in the embodiment of the present invention (No. 3). 比較例におけるコンタクト電極の電流電圧特性を示す図表である。It is a graph which shows the current-voltage characteristic of the contact electrode in a comparative example. 実施例におけるコンタクト電極の電流電圧特性を示す図表である。It is a graph which shows the current-voltage characteristic of the contact electrode in an Example.

以下に添付図面を参照して、この発明にかかる炭化珪素半導体素子の製造方法の好適な実施の形態を詳細に説明する。   Exemplary embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

発明者は、上記課題を解決するべく検討を重ねた結果、オーミック電極について、ニッケル(Ni)を含まず、チタン(Ti)、ジルコニウム(Zr)、ハフニウム(Hf)といった、炭化物を生成し易くかつ窒化物も生成し易い金属を電極主材料の内いずれか1種類以上を含む純金属もしくは合金を用い、窒素(N)を主成分とする雰囲気中で熱アニールを行って、炭化物と窒化物の両方を含む混合物に変換することとした。これにより、ニッケルを用いなくても実用に足る低コンタクト抵抗を確保でき、かつ層間絶縁膜中にスパイクを起こさないという本発明を完成するに至った。   As a result of repeated studies to solve the above problems, the inventor does not contain nickel (Ni), and is easy to generate carbides such as titanium (Ti), zirconium (Zr), hafnium (Hf), and the ohmic electrode. Using a pure metal or alloy containing at least one of the electrode main materials as a metal that easily generates nitrides, and performing thermal annealing in an atmosphere containing nitrogen (N) as a main component, the carbide and nitride It was decided to convert to a mixture containing both. As a result, the present invention has been completed, in which low contact resistance that is practical enough can be secured without using nickel, and no spike is caused in the interlayer insulating film.

(実施の形態)
以下、本発明による炭化珪素半導体素子の製造方法の好適な実施形態を、図面を参照しながら詳細に説明する。ここでは炭化物を生成し易くかつ窒化物も生成し易い金属として、チタンを用いるものとする。
(Embodiment)
Hereinafter, preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the drawings. Here, titanium is used as a metal that easily generates carbides and also easily generates nitrides.

図1〜図3は、それぞれこの発明の実施の形態における炭化珪素半導体素子の電極の製造工程を示す断面図である。n型炭化珪素基板1上に形成するオーミック電極の断面を、各製造工程で断面方向から見た模式図である。また、下記の手順1〜手順3はそれぞれ、図1〜図3の各番号と対応している。以下、オーミック電極をニッケルを含まず、チタンを用いて形成する例について説明する。   1 to 3 are cross-sectional views showing steps for manufacturing an electrode of a silicon carbide semiconductor element in the embodiment of the present invention. It is the schematic diagram which looked at the cross section of the ohmic electrode formed on the n-type silicon carbide substrate 1 from the cross-sectional direction in each manufacturing process. The following procedure 1 to procedure 3 correspond to the numbers in FIGS. Hereinafter, an example in which the ohmic electrode is formed using titanium without including nickel will be described.

〔手順1〕
図1に示すように、薬液洗浄やプラズマエッチングなどの方法で清浄化された単結晶n型炭化珪素基板(炭化珪素基板)1の上に、必要なデバイス構造を形成し、層間絶縁膜2で密封する。本実施例では上記デバイス構造の一例として、MOSFET構造の一部を示している。MOSFET形成時には、p型ウェル層3、n型ドリフト層4、n型イオン注入領域5、ゲート酸化膜6、ゲート電極7、素子分離メサ8を有する。
[Procedure 1]
As shown in FIG. 1, a necessary device structure is formed on a single crystal n-type silicon carbide substrate (silicon carbide substrate) 1 cleaned by a chemical cleaning method or a plasma etching method. Seal. In this embodiment, a part of the MOSFET structure is shown as an example of the device structure. When the MOSFET is formed, the p-type well layer 3, the n-type drift layer 4, the n-type ion implantation region 5, the gate oxide film 6, the gate electrode 7, and the element isolation mesa 8 are provided.

〔手順2〕
次に、図2に示すように、ドライエッチングなどの手法を用い、層間絶縁膜2およびゲート酸化膜6の一部を開口してコンタクトホール9を形成し、メタルスパッタ装置を用いて層間絶縁膜2およびn型イオン注入領域5を覆うチタン層10を堆積する。このように、チタン層10は、手順2で堆積させ、最初の手順1において窒化チタンの形で堆積しない。これは、窒化チタンは化学的安定性が高いため、電極として窒化チタン層を形成した場合、薬液エッチングで窒化チタン層をパターニングできず、チタン層10上に形成するパターンニング工程(後述する)がドライエッチングに限定されてしまうためである。チタン層10は、薬液エッチングおよびドライエッチングのいずれでもパターニング可能なチタン層がよい。
[Procedure 2]
Next, as shown in FIG. 2, using a technique such as dry etching, a part of the interlayer insulating film 2 and the gate oxide film 6 is opened to form a contact hole 9, and the interlayer insulating film is used using a metal sputtering apparatus. A titanium layer 10 is deposited covering the 2 and n-type ion implantation regions 5. Thus, the titanium layer 10 is deposited in Procedure 2 and not in the form of titanium nitride in the initial Procedure 1. This is because, since titanium nitride has high chemical stability, when a titanium nitride layer is formed as an electrode, the titanium nitride layer cannot be patterned by chemical etching, and a patterning step (described later) is formed on the titanium layer 10. This is because it is limited to dry etching. The titanium layer 10 is preferably a titanium layer that can be patterned by either chemical etching or dry etching.

チタン層10の膜厚は、最低50nm程度あればオーミック接合を形成することが可能だが、縦型デバイスの裏面電極として用いる場合は、炭化珪素基板1の裏面がダイヤモンドスラリー等の機械研磨により仕上げられることが多いため、研磨ダメージ層よりも深くまでチタンを浸透させなければならない。この観点から、チタン層10の膜厚を最低でも100nm程度とすることが好ましい。   If the thickness of the titanium layer 10 is at least about 50 nm, an ohmic junction can be formed. However, when used as a back electrode of a vertical device, the back surface of the silicon carbide substrate 1 is finished by mechanical polishing such as diamond slurry. In many cases, titanium must be penetrated deeper than the polishing damage layer. From this viewpoint, it is preferable that the thickness of the titanium layer 10 be at least about 100 nm.

電極パターンの形成が必要な場合は、一般的なフォトリソグラフィ工程の手順で所望の電極パターンをチタン層10の上に塗布したフォトレジストに焼き付け(図示略)、電極パターンが形成されたレジストマスクをマスクとして薬液エッチングもしくはドライエッチングでチタン層10のパターンニングを行う。薬液エッチングの場合は、アンモニアを含む薬液(例えばアンモニア水−過酸化水素混合液)を、ドライエッチングの場合は、塩素系のプラズマをエッチャントとして用いると良い。なお、実施にあたっては、必ずしもエッチャントが上記の薬液やプラズマに限定されるものではない。   When it is necessary to form an electrode pattern, a desired electrode pattern is baked onto the photoresist coated on the titanium layer 10 by a general photolithography process (not shown), and a resist mask on which the electrode pattern is formed is applied. The titanium layer 10 is patterned by chemical etching or dry etching as a mask. In the case of chemical etching, a chemical solution containing ammonia (for example, a mixed solution of ammonia water and hydrogen peroxide) may be used as an etchant, and in the case of dry etching, chlorine-based plasma may be used as an etchant. In implementation, the etchant is not necessarily limited to the above chemical solution or plasma.

〔手順3〕
次に、図3に示すように、炭化珪素基板1をアニール炉に導入し、高純度の窒素雰囲気中で熱アニールを行う。窒素の純度は、半導体デバイス製造工程で一般的に使われる6N(99.9999%)で良い。窒素の分圧は、本発明の性格上、反応性スパッタで窒化チタンを堆積する場合(1Pa前後)と比べてかなり高めに設定する必要があるが、100kPa程度あれば確実にチタンの窒化反応が起こることが確認されている。
[Procedure 3]
Next, as shown in FIG. 3, silicon carbide substrate 1 is introduced into an annealing furnace, and thermal annealing is performed in a high-purity nitrogen atmosphere. The purity of nitrogen may be 6N (99.9999%) generally used in the semiconductor device manufacturing process. Due to the nature of the present invention, the partial pressure of nitrogen needs to be set considerably higher than when titanium nitride is deposited by reactive sputtering (around 1 Pa). It has been confirmed that this happens.

コンタクトホール9の部分では、チタン層10は、最表面30〜40nm程度が窒素のみと反応して窒化チタン層11に変化する。また、このコンタクトホール9のより深い部分、炭化珪素基板1側では、窒素および炭化珪素と反応して、窒化チタンと炭化チタンの混合層12に変化する。   In the contact hole 9 portion, the titanium layer 10 changes to the titanium nitride layer 11 when the outermost surface of about 30 to 40 nm reacts only with nitrogen. Further, at a deeper portion of the contact hole 9, that is, on the silicon carbide substrate 1 side, it reacts with nitrogen and silicon carbide and changes to a mixed layer 12 of titanium nitride and titanium carbide.

一方、層間絶縁膜2の上では、チタン層10の最表面30〜40nm程度が窒素のみと反応して窒化チタン層11に変化し、残りは二酸化珪素とも反応して、窒化チタンと酸化チタンと珪化チタンの混合層13に変化する。窒素を主成分とする雰囲気中では、二酸化珪素とチタンとの反応がほぼ均一に進むため、真空中もしくは希ガス中での反応のようにスパイク現象を起こすことはない。   On the other hand, on the interlayer insulating film 2, the outermost surface of the titanium layer 10 of about 30 to 40 nm reacts only with nitrogen and changes to the titanium nitride layer 11, and the rest reacts with silicon dioxide to form titanium nitride and titanium oxide. It changes to the mixed layer 13 of titanium silicide. In an atmosphere containing nitrogen as a main component, the reaction between silicon dioxide and titanium proceeds almost uniformly, so that a spike phenomenon does not occur as in a reaction in a vacuum or a rare gas.

(実施例および比較例)
比較例としての従来の真空中での熱アニールと、実施例として上記手順の窒素雰囲気中での熱アニールとを行った。この際、いずれもn型ベア基板(窒素ドープ、1×1018cm-3、表面は0.5μmダイヤモンドスラリーによる機械研磨仕上げ)に、伝送線路モデルに基づく測定を行うためのTLM電極パターンを形成し、コンタクト抵抗の違いを比べた。
(Examples and Comparative Examples)
Conventional thermal annealing in vacuum as a comparative example and thermal annealing in a nitrogen atmosphere of the above procedure were performed as examples. At this time, a TLM electrode pattern for measurement based on a transmission line model is formed on an n-type bare substrate (nitrogen-doped, 1 × 10 18 cm −3 , surface is mechanically polished with a 0.5 μm diamond slurry). The difference in contact resistance was compared.

熱アニール前の金属の膜厚は、比較例では、ニッケル100nmとチタン80nmの積層構造(ニッケルが基板に近い側)であり、実施例ではチタン100nmである。各電極間のギャップ長は10μmから100μmまで刻み幅10μmとした。熱アニールのピーク温度は全て1000℃とした。   The film thickness of the metal before thermal annealing is a laminated structure of nickel 100 nm and titanium 80 nm (nickel closer to the substrate) in the comparative example, and titanium 100 nm in the example. The gap length between the electrodes was 10 μm to 100 μm and the width was 10 μm. The peak temperatures for thermal annealing were all set to 1000 ° C.

図4は、比較例におけるコンタクト電極の電流電圧特性を示す図表である。横軸が電圧、縦軸が電流である。比較例のニッケルとチタンとを含むコンタクト電極では、図4に示すように電流−電圧特性にショットキー接合の成分が乗る形となっており、ほぼ直線と見なせる範囲で定義したコンタクト抵抗は5×10-3Ωcm2と高くなった。また、膜厚500nmの層間絶縁膜2を介した測定では、コンタクト電極と下地の炭化珪素基板1との間に僅か1V未満の交流電圧を印加した時点で導通が確認され、スパイク現象が起きていることが示された。 FIG. 4 is a chart showing current-voltage characteristics of contact electrodes in a comparative example. The horizontal axis is voltage, and the vertical axis is current. As shown in FIG. 4, the contact electrode containing nickel and titanium in the comparative example has a shape in which a Schottky junction component is superimposed on the current-voltage characteristics, and the contact resistance defined within a range that can be regarded as a substantially straight line is 5 ×. It was as high as 10 −3 Ωcm 2 . In the measurement through the interlayer insulating film 2 having a thickness of 500 nm, conduction was confirmed when an AC voltage of less than 1 V was applied between the contact electrode and the underlying silicon carbide substrate 1, and a spike phenomenon occurred. It was shown that

図5は、実施例におけるコンタクト電極の電流電圧特性を示す図表である。横軸が電圧、縦軸が電流である。本実施例のコンタクト電極は、チタンのみでニッケルを含まないコンタクト電極であり、図5に示すように、ニッケルを用いなくても、電流−電圧特性にショットキー接合の成分が乗らなくなり、コンタクト抵抗は1×10-4Ωcm2と明確な改善が見られた。また、膜厚500nmの層間絶縁膜2を介した測定では、縦型パワーMOSFETのゲート/ソース間耐久試験を想定した80Vの交流電圧を印加しても、コンタクト電極と下地の炭化珪素基板1との間で全く導通は確認されず、絶縁が保たれていることが示された。 FIG. 5 is a chart showing current-voltage characteristics of the contact electrodes in the example. The horizontal axis is voltage, and the vertical axis is current. The contact electrode of this example is a contact electrode that contains only titanium and does not contain nickel. As shown in FIG. 5, even if nickel is not used, the current-voltage characteristics are not subjected to the Schottky junction component, and the contact resistance is reduced. A clear improvement of 1 × 10 −4 Ωcm 2 was observed. Further, in the measurement through the interlayer insulating film 2 having a thickness of 500 nm, the contact electrode and the underlying silicon carbide substrate 1 are not affected even when an AC voltage of 80 V assuming a gate-source durability test of the vertical power MOSFET is applied. No conduction was confirmed between the two, indicating that insulation was maintained.

以上説明したように、本発明の実施の形態によれば、オーミック電極について、チタン(Ti)、ジルコニウム(Zr)、ハフニウム(Hf)といった、炭化物を生成し易くかつ窒化物も生成し易い金属を電極主材料として用い、窒素(N)を主成分とする雰囲気中で熱アニールを行って、炭化物と窒化物の両方を含む混合物に変換する。これにより、ニッケルを用いなくても実用に足る低コンタクト抵抗を確保でき、かつ層間絶縁膜中にスパイクを起こさない。   As described above, according to the embodiment of the present invention, a metal such as titanium (Ti), zirconium (Zr), hafnium (Hf), which easily generates carbides and nitrides, is used for the ohmic electrode. It is used as an electrode main material and is thermally annealed in an atmosphere containing nitrogen (N) as a main component to convert it into a mixture containing both carbide and nitride. As a result, a practically low contact resistance can be ensured without using nickel, and no spike is caused in the interlayer insulating film.

以上のように、本発明にかかる炭化珪素半導体素子の製造方法は、例えばパワーデバイス等の電力用半導体装置や、産業用のモーター制御やエンジン制御に使用されるパワー半導体装置に有用である。   As described above, the method for manufacturing a silicon carbide semiconductor element according to the present invention is useful for power semiconductor devices such as power devices, and power semiconductor devices used for industrial motor control and engine control.

1 単結晶n型炭化珪素基板(炭化珪素基板)
2 層間絶縁膜
3 p型ウェル層
4 n型ドリフト層
5 n型イオン注入領域
6 ゲート酸化膜
7 ゲート電極
8 素子分離メサ
9 コンタクトホール
10 チタン層
11 窒化チタン層
12 窒化チタンと炭化チタンの混合層
13 窒化チタンと酸化チタンと珪化チタンの混合層
1 Single crystal n-type silicon carbide substrate (silicon carbide substrate)
2 Interlayer insulating film 3 p-type well layer 4 n-type drift layer 5 n-type ion implantation region 6 gate oxide film 7 gate electrode 8 element isolation mesa 9 contact hole 10 titanium layer 11 titanium nitride layer 12 mixed layer of titanium nitride and titanium carbide 13 Mixed layer of titanium nitride, titanium oxide and titanium silicide

Claims (2)

単結晶の炭化珪素基板を用いた炭化珪素半導体素子の製造方法において、
前記炭化珪素基板にコンタクト電極を形成する工程を含み、
当該コンタクト電極を形成する工程は、
前記コンタクト電極として、炭化物を生成し易くかつ窒化物も生成し易い金属を電極主材料として用い、
窒素を主成分とする雰囲気中で熱アニールを行い、前記炭化珪素基板と前記コンタクト電極の材料の金属とが直接接触しているコンタクトホールの領域において、当該熱アニール時に前記コンタクト電極の材料の金属を炭化物と窒化物の両方を含む混合物に変換することを特徴とする炭化珪素半導体素子の製造方法。
In a method for manufacturing a silicon carbide semiconductor element using a single crystal silicon carbide substrate,
Forming a contact electrode on the silicon carbide substrate;
The step of forming the contact electrode includes:
As the contact electrode, a metal that easily generates carbides and nitrides is used as an electrode main material,
In the contact hole region where the silicon carbide substrate and the metal of the contact electrode are in direct contact with each other, thermal annealing is performed in an atmosphere containing nitrogen as a main component. Is converted to a mixture containing both a carbide and a nitride.
前記コンタクト電極の材料の金属が、チタン、ジルコニウム、ハフニウムの内いずれか1種類以上を含む純金属もしくは合金であることを特徴とする請求項1に記載の炭化珪素半導体素子の製造方法。   2. The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the metal of the material of the contact electrode is a pure metal or an alloy containing any one or more of titanium, zirconium, and hafnium.
JP2012104224A 2012-04-27 2012-04-27 Method for manufacturing silicon carbide semiconductor element Active JP6156814B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012104224A JP6156814B2 (en) 2012-04-27 2012-04-27 Method for manufacturing silicon carbide semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012104224A JP6156814B2 (en) 2012-04-27 2012-04-27 Method for manufacturing silicon carbide semiconductor element

Publications (2)

Publication Number Publication Date
JP2013232557A true JP2013232557A (en) 2013-11-14
JP6156814B2 JP6156814B2 (en) 2017-07-05

Family

ID=49678737

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012104224A Active JP6156814B2 (en) 2012-04-27 2012-04-27 Method for manufacturing silicon carbide semiconductor element

Country Status (1)

Country Link
JP (1) JP6156814B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016025285A (en) * 2014-07-23 2016-02-08 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
JP2018088462A (en) * 2016-11-28 2018-06-07 トヨタ自動車株式会社 Method for manufacturing semiconductor device
US10790373B2 (en) 2017-10-17 2020-09-29 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283738A (en) * 1996-04-10 1997-10-31 Nippon Steel Corp Ohmic electrode for n-type silicon carbide and manufacturing method thereof
JP2005012099A (en) * 2003-06-20 2005-01-13 Nissan Motor Co Ltd Manufacturing method of silicon carbide semiconductor device
WO2009054140A1 (en) * 2007-10-24 2009-04-30 Panasonic Corporation Semiconductor device and method for manufacturing the same
JP2009272530A (en) * 2008-05-09 2009-11-19 Sharp Corp Semiconductor device and method for manufacturing same
WO2011027523A1 (en) * 2009-09-03 2011-03-10 パナソニック株式会社 Semiconductor device and method for producing same
JP2011233612A (en) * 2010-04-26 2011-11-17 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09283738A (en) * 1996-04-10 1997-10-31 Nippon Steel Corp Ohmic electrode for n-type silicon carbide and manufacturing method thereof
JP2005012099A (en) * 2003-06-20 2005-01-13 Nissan Motor Co Ltd Manufacturing method of silicon carbide semiconductor device
WO2009054140A1 (en) * 2007-10-24 2009-04-30 Panasonic Corporation Semiconductor device and method for manufacturing the same
JP2009272530A (en) * 2008-05-09 2009-11-19 Sharp Corp Semiconductor device and method for manufacturing same
WO2011027523A1 (en) * 2009-09-03 2011-03-10 パナソニック株式会社 Semiconductor device and method for producing same
JP2011233612A (en) * 2010-04-26 2011-11-17 Mitsubishi Electric Corp Semiconductor device and method of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016025285A (en) * 2014-07-23 2016-02-08 富士電機株式会社 Method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
JP2018088462A (en) * 2016-11-28 2018-06-07 トヨタ自動車株式会社 Method for manufacturing semiconductor device
US10790373B2 (en) 2017-10-17 2020-09-29 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing same

Also Published As

Publication number Publication date
JP6156814B2 (en) 2017-07-05

Similar Documents

Publication Publication Date Title
TWI311814B (en) Silicon carbide semiconductor device and method for producing the same
JP5141227B2 (en) Manufacturing method of semiconductor device
WO2012131898A1 (en) Silicon carbide semiconductor device
JP5458652B2 (en) Method for manufacturing silicon carbide semiconductor device
WO2013011740A1 (en) Method for manufacturing semiconductor device
US10263071B2 (en) Method of manufacturing semiconductor device
JP2007242744A (en) Method of manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device
CN108257858B (en) Preparation method of high-k gate dielectric layer and silicon carbide MOS power device
JP2012256774A (en) Semiconductor device manufacturing method
JP2012160485A (en) Semiconductor device and manufacturing method of the same
WO2012120731A1 (en) Production method for semiconductor device
JP2011146662A (en) METHOD OF MANUFACTURING SiC SEMICONDUCTOR ELEMENT
CN108257855B (en) Preparation method of high-k gate dielectric layer and silicon carbide MOS power device
JP2013105966A (en) Semiconductor device manufacturing method and semiconductor device
JP6156814B2 (en) Method for manufacturing silicon carbide semiconductor element
CN105580112A (en) Method for manufacturing silicon-carbide semiconductor device
TW201237960A (en) Production method for semiconductor device
CN113035951A (en) MOSFET structure and preparation method and application thereof
JP2015005669A (en) Method of manufacturing silicon carbide semiconductor device
JP6233210B2 (en) Method for manufacturing silicon carbide semiconductor device
US9659773B2 (en) Method for manufacturing silicon carbide semiconductor device by selectively removing silicon from silicon carbide substrate to form protective carbon layer on silicon carbide substrate for activating dopants
JP6582537B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2013172111A (en) Silicon carbide semiconductor device and manufacturing method of the same
Li et al. Morphology improvement of SiC trench by inductively coupled plasma etching using Ni/Al2O3 bilayer mask
KR20210030850A (en) SiC Trench Gate MOSFET Device and Manufacturing Method thereof

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20150319

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150305

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150916

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150929

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151130

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160607

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160808

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20161220

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170317

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20170328

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170509

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170530

R150 Certificate of patent or registration of utility model

Ref document number: 6156814

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250