CN112289683B - High electron mobility transistor and method for manufacturing the same - Google Patents
High electron mobility transistor and method for manufacturing the same Download PDFInfo
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- CN112289683B CN112289683B CN202011542433.1A CN202011542433A CN112289683B CN 112289683 B CN112289683 B CN 112289683B CN 202011542433 A CN202011542433 A CN 202011542433A CN 112289683 B CN112289683 B CN 112289683B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
- H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
- H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
- H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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Abstract
本发明提供了一种高电子迁移率晶体管及其制造方法，通过采用第二导电类型的掺杂离子对栅极堆叠结构底部所覆盖的区域的缓冲层进行离子注入，形成第一离子注入区，并在栅极堆叠结构底部所覆盖的多个局部区域再次进行离子注入，形成第二离子注入区，该第二离子注入区、第一离子注入区和盖帽层相互连接，由此形成了环绕源极和漏极之间的二维电子气沟道（2DEG沟道）的环绕栅，该环绕栅包围所述2DEG沟道的顶面、底面和垂直于源极和漏极的侧壁，增强了栅极对2DEG沟道的控制能力，提高了器件阈值电压。此外，在器件关断时，该环绕栅能帮助耗尽沟道中的二维电子气，减小关断漏电，提高器件耐压。
The present invention provides a high electron mobility transistor and a manufacturing method thereof. The first ion implantation region is formed by ion implanting the buffer layer in the region covered by the bottom of the gate stack structure by using doping ions of the second conductivity type. And ion implantation is performed again in a plurality of local regions covered by the bottom of the gate stack structure to form a second ion implantation region, the second ion implantation region, the first ion implantation region and the cap layer are connected to each other, thereby forming a surrounding source Surround gate of a two-dimensional electron gas channel (2DEG channel) between electrode and drain, which surrounds the top surface, bottom surface and sidewalls perpendicular to source and drain of the 2DEG channel, enhancing the The gate's ability to control the 2DEG channel increases the device threshold voltage. In addition, when the device is turned off, the surrounding gate can help to deplete the two-dimensional electron gas in the channel, thereby reducing the turn-off leakage and improving the withstand voltage of the device.
Description
Technical Field
The invention relates to the technical field of semiconductor device manufacturing, in particular to a high electron mobility transistor and a manufacturing method thereof.
Background
In a conventional enhanced GaN-based High Electron Mobility Transistor (HEMT) prepared based on a p-type gate technology, as shown in fig. 1, a p-GaN cap layer 100 is usually only arranged on one side of the upper surface of the device, and has a weak control capability on a two-dimensional Electron gas (2 DEG) channel, which results in disadvantages of low threshold voltage, large off-leakage, concentration of a lateral withstand voltage electric field on the surface of the device, and the like.
Disclosure of Invention
The invention aims to provide a high electron mobility transistor and a manufacturing method thereof so as to improve the performance of a device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a high electron mobility transistor, comprising the steps of:
providing a substrate, and sequentially forming a buffer layer, a barrier layer and a cap layer on the substrate, wherein the buffer layer has a first conductivity type;
carrying out first ion implantation on the buffer layer in the region to be formed with the grid electrode by adopting doping ions with a second conductivity type so as to form a first ion implantation region in the buffer layer;
carrying out second ion implantation on the first ion implantation regions of the plurality of local regions, the barrier layer above the first ion implantation regions and the cap layer by adopting doping ions with a second conductivity type to form second ion implantation regions;
forming a gate stack structure on the region where the gate is to be formed, and forming a source electrode and a drain electrode at two sides of the gate stack structure, wherein the bottom of the source electrode and the bottom of the drain electrode are in electrical contact with the buffer layer, the gate stack structure at least comprises the patterned cap layer and the gate electrode stacked on the cap layer, a two-dimensional electron gas channel is formed at the interface of the buffer layer and the barrier layer between the source electrode and the drain electrode, and the cap layer, the first ion injection region and the second ion injection region are connected with each other to form a surrounding gate surrounding the two-dimensional electron gas channel.
Based on the same inventive concept, the present invention also provides a high electron mobility transistor, comprising:
the semiconductor device comprises a substrate, a buffer layer and a barrier layer, wherein the buffer layer and the barrier layer are sequentially stacked on the substrate, and the buffer layer is of a first conduction type;
a gate stack structure including a cap layer and a gate electrode sequentially stacked on the barrier layer;
a first ion implantation region doped with doping ions of a second conductivity type, the first ion implantation region being formed in the buffer layer covering the bottom of the gate stack structure;
a second ion implantation region doped with doping ions of a second conductivity type, wherein the second ion implantation region is formed in a plurality of local regions covered by the bottom of the gate stack structure and extends from the first ion implantation region with at least partial thickness of each local region to the cap layer from bottom to top;
the source electrode and the drain electrode are formed on two sides of the grid electrode stacking structure, the bottom of the source electrode and the bottom of the drain electrode are respectively in electrical contact with the buffer layer, a two-dimensional electron air channel is formed at the interface of the buffer layer and the barrier layer between the source electrode and the drain electrode, and the cap layer, the first ion injection region and the second ion injection region are connected with each other to form a surrounding grid surrounding the two-dimensional electron air channel.
The high electron mobility transistor of the present invention can be obtained by the method for manufacturing a high electron mobility transistor of the present invention.
Compared with the prior art, according to the High Electron Mobility Transistor (HEMT) and the manufacturing method thereof, the doping ions of the second conduction type are adopted to carry out ion implantation on the buffer layer in the region covered by the bottom of the grid stacking structure (namely the region where the grid is to be formed), so that the first ion implantation region is formed, ion implantation is carried out again in a plurality of local regions covered by the bottom of the grid stacking structure, so that the second ion implantation region is formed, and the second ion implantation region, the first ion implantation region and the cap layer are connected with each other, so that a surrounding grid surrounding a two-dimensional electron gas (2 DEG) channel between a source electrode and a drain electrode is formed. Under the action of external grid voltage and polarization effect, the bottom of the grid stacking structure can form a 2DEG, and the surrounding grid surrounds the top surface and the bottom surface of the 2DEG channel and the side wall vertical to the source electrode and the drain electrode, so that the control capability of the 2DEG channel is enhanced, the threshold voltage of the device can be further improved, and meanwhile, the resistance influence on the device during conduction is small. In addition, when the device is turned off, the surrounding gate can help to exhaust two-dimensional electron gas in the channel, the turn-off leakage is reduced, and meanwhile, the depletion region of the two-dimensional electron gas can be easily expanded into the first ion injection region, so that the withstand voltage of the device is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional enhancement mode GaN-based hemt in the prior art.
Fig. 2 is a flow chart of a method of fabricating a high electron mobility transistor in accordance with an embodiment of the present invention.
Fig. 3 to fig. 10 are a schematic top view and a schematic cross-sectional view of a method for manufacturing a high electron mobility transistor according to an embodiment of the invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a high electron mobility transistor, including the following steps:
s1, providing a substrate, and sequentially forming a buffer layer, a barrier layer and a cap layer on the substrate, wherein the buffer layer has a first conductive type;
s2, performing first ion implantation on the buffer layer in the region where the gate is to be formed by adopting doping ions of the second conductivity type to form a first ion implantation region in the buffer layer;
s3, carrying out second ion implantation on the first ion implantation areas, the barrier layer and the cap layer above the first ion implantation areas in the plurality of local areas by adopting doping ions of a second conduction type to form second ion implantation areas;
s4, forming a grid stacking structure on the area where the grid is to be formed, and forming a source electrode and a drain electrode at two sides of the grid stacking structure, wherein the bottom of the source electrode and the drain electrode are in electrical contact with the buffer layer, the grid stacking structure at least comprises the patterned cap layer and the grid electrode stacked on the cap layer, a two-dimensional electron gas channel is formed in the buffer layer between the source electrode and the drain electrode, and the cap layer, the first ion injection region and the second ion injection region are connected with each other to form a surrounding grid surrounding the two-dimensional electron gas channel.
The technical solution proposed in the present embodiment will be further described in detail with reference to fig. 3 to 10. Fig. 3 is a schematic diagram of a top-view structure of the device when step S2 is performed, fig. 4 is a schematic diagram of a cross-sectional structure of the device along line AA 'in fig. 3, fig. 5 is a schematic diagram of a top-view structure of the device when step S3 is performed, fig. 6 is a schematic diagram of a cross-sectional structure of the device along line BB' in fig. 5, fig. 7 is a schematic diagram of a top-view structure of the device after step S4 is performed, fig. 8 is a schematic diagram of a cross-sectional structure of the device along line AA 'in fig. 7, fig. 9 is a schematic diagram of a cross-sectional structure of the device along line CC' in fig. 7, and fig. 10 is a schematic diagram of a cross.
Referring to fig. 3 and 4, in step S1, first, a substrate 200 is provided, where the substrate 200 may be any suitable semiconductor substrate, such as a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a sapphire (Al) substrate2O3) A substrate, etc. Then, a transition layer 201, a buffer layer 202, a barrier layer 203, a cap layer 204, and a contact layer 205 are sequentially formed on the surface of the substrate 200 by a suitable epitaxial growth process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), molecular beam epitaxy (MB), or Metal Organic Chemical Vapor Deposition (MOCVD).
The transition layer 201 can alleviate lattice constant difference and thermal expansion coefficient difference between the subsequently formed buffer layer 202 and the substrate 200, and provide a suitable interface for growing the buffer layer 202, thereby ensuring the quality of the formed buffer layer 202. As an example, the material of the transition layer 201 may include one or more of aluminum gallium nitride (AlGaN), aluminum nitride (AlN), silicon nitride (SiN), indium nitride (InN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and the like.
The buffer layer 202 can release stress generated between the epitaxially grown heterostructure and the substrate 200 due to lattice mismatch and thermal mismatch, and reduce current leakage during device operation. As an example, when the hemt to be fabricated is an enhancement mode GaN-based hemt having a p-type (i.e., second conductivity type) gate, the buffer layer 202 has an N-type (i.e., first conductivity type) conductivity and may be made of one or more of gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), indium aluminum nitride (InAlN), and the like. The buffer layer 202 may be a single-layer film structure, or may be a composite structure in which multiple films are stacked in sequence from bottom to top (for example, a composite material layer in which Al composition gradually decreases along the growth direction of the buffer layer).
The barrier layer 203 and the buffer layer 202 are of different materials, and the barrier layer 203 and the buffer layer 202 can form a semiconductor heterojunction of the device. After the gate electrode, the source electrode, and the drain electrode are formed in the subsequent step S4, and after the gate voltage is applied, a two-dimensional electron gas (2 DEG) with high electron mobility can be formed at and near the interface between the barrier layer 203 and the buffer layer 202, i.e., a two-dimensional electron gas channel 202c for transporting current can be formed between the source electrode and the drain electrode. The conductivity type of the barrier layer 203 is N-type, and the material thereof includes one or more of AlGaN, InAlN, AlN, InN, and InGaN.
The cap layer 204 can form a surrounding gate in combination with the subsequently formed first and second ion implantation regions to deplete carriers within the two-dimensional electron gas (2 DEG) channel 202 c. The cap layer 204 formed in step S1 has the second conductivity type, i.e., when the buffer layer 202 is N-type, the cap layer 204 is a P-type doped semiconductor material layer. Optionally, the material of the cap layer 204 includes one or more of P-type ion doped GaN (denoted as P-GaN), P-type ion doped InGaN (denoted as P-InGaN), P-type ion doped AlGaN (denoted as P-AlGaN), P-AlGaN with graded Al composition, or P-InGaN with graded In composition.
The contact layer 205 is used to make a schottky contact between the cap layer 204 and a gate electrode formed later, and has the same conductivity type as the cap layer 204 but different material from the cap layer 204. Optionally, the material of the contact layer 205 includes one or more of P-type ion doped GaN (denoted as P-GaN), P-type ion doped InGaN (denoted as P-InGaN), P-type ion doped AlGaN (denoted as P-AlGaN), P-AlGaN with graded Al composition, or P-InGaN with graded In composition.
Referring to fig. 3 and 4, in step S2, a patterned mask layer 206 may be formed on the surface of the contact layer 205 by coating a photoresist and performing photolithography, or by a series of processes such as hard mask material deposition, photolithography and etching, the material of the patterned mask layer 206 includes at least one of photoresist, silicon dioxide, silicon nitride, etc., and the patterned mask layer 206 has an opening 206a exposing the contact layer 205 in the region D where the gate is to be formed. Then, the patterned mask layer 206 is used as a mask, and P-type dopant ions (i.e., dopant ions of the second conductivity type) including, for example, at least one of magnesium ions, aluminum ions, fluorine ions, and carbon ions are used to form a maskThe buffer layer 202 in the region D of the gate (i.e., at the bottom of the opening 206 a) is subjected to a first ion implantation to form a first ion implantation region 202a in the buffer layer 202. Optionally, the implantation energy of the first ion implantation is 10KeV to 1MeV, and the implantation dose is 2.0 × 1012cm-2To 1.0X 1015cm-2. As an example, in this step, the ion implanter is used to implant an ion beam with an energy of 100KeV and a dose of 5.0X 1013cm-2Into the buffer layer 202 at the bottom of the opening 206a to form a first ion implantation region 202 a.
In step S2, after the first ion implantation, the concentration of the implanted second conductivity type dopant ions follows a gaussian distribution in the contact layer 205 to the buffer layer 202, the concentration of the second conductivity type dopant ions in the buffer layer 202 under the two-dimensional electron gas channel 202c is higher in the region D where the gate is to be formed, and the concentration of the second conductivity type dopant ions in the film layer in the two-dimensional electron gas channel region and above is lower, so that the buffer layer 202 under the two-dimensional electron gas channel in the region D where the gate is to be formed can be converted into the second conductivity type, but the conductivity type of the region of the two-dimensional electron gas channel and the film layer above the region D will not be affected.
It should be noted that in this embodiment, the first ion implantation is performed after the epitaxial processes of the barrier layer 203, the cap layer 204 and the contact layer 205 are completed, this is done because, the temperature of the epitaxial growth process of the barrier layer 203, the cap layer 204 and the contact layer 205 is generally high, and the epitaxial time is long, if the first ion implantation is performed after the formation of the buffer layer 202, then epitaxially growing barrier layers 203, cap layers 204, contact layers 205 and other film layers, the epitaxial growth process of the barrier layer 203, the cap layer 204 and the contact layer 205 may result in redistribution of the dopant ions from the first ion implantation, therefore, in this embodiment, the barrier layer 203, the cap layer 204, and the contact layer 205 are formed first, and then the first ion implantation is performed, so that the device performance can be ensured.
Referring to fig. 5 and 6, in step S3, the patterned mask layer 206 is removed, and a patterned mask layer 207 is formed on the surface of the contact layer 205 by a process similar to that for manufacturing the patterned mask layer 206, wherein the patterned mask layer 207 has openings 207a that respectively expose a plurality of (2 or more) local areas in the area D where the gate is to be formed, and the openings 207a are sequentially arranged at intervals along the length direction of the area D where the gate is to be formed. Then, using the patterned mask layer 207 as a mask, a second ion implantation is performed on the contact layer 205, the cap layer 204, the barrier layer 203, and the first ion implantation region 202a at the bottom of the opening 207a using, for example, P-type dopant ions (i.e., dopant ions of the second conductivity type) including at least one of magnesium ions, aluminum ions, fluorine ions, and carbon ions, so as to form a second ion implantation region 202 b. The main purpose of the second ion implantation is to increase the concentration of the second conductivity type dopant ions in a certain thickness on the surface layer of the local region, so that the conductivity type of the film layer in the local region is the second conductivity type (for example, P-type), and thus after subsequent annealing, the second ion implantation region 202b, the first ion implantation region 202a, and the cap layer 204 can be connected to form a surrounding gate surrounding the two-dimensional electron gas channel for one circle. The implantation depth of the second ion implantation region 202b is shallower than that of the first ion implantation region 202 a. Optionally, the implantation energy of the second ion implantation is 10KeV to 100KeV, and the implantation dose is 2.0 × 1012cm-2To 1.0X 1015cm-2. As an example, in this step, the ion implanter is used to implant an ion beam with an energy of 30KeV and a dose of 1.0X 1013cm-2To the buffer layer 202 at the bottom of the opening 207a and the upper layers to form a second ion implantation region 202 b. The second conductive type dopant ions used in the second ion implantation in this step may be the same as or different from the second conductive type dopant ions used in the first ion implantation in step S2. Then, the patterned mask layer 207 is removed, the surface of the contact layer 205 is cleaned, and annealing is further performed on the first ion implantation region 202a and the second ion implantation region 202b by an annealing processSpecifically, in the region D where the gate is to be formed, the first ion implantation region 202a covers the bottom surface of the two-dimensional electron gas channel, the cap layer 204 covers the top surface of the two-dimensional electron gas channel, and the two adjacent second ion implantation regions 202b cover the side walls of the two-dimensional electron gas channel. In addition, after the annealing treatment, a part of the thickness of the first ion implantation region 202a remains at the bottom of the second ion implantation region 202b, so that the ion doping concentration below the bottom of the second ion implantation region 202b in the region D where the gate is to be formed is relatively low.
Referring to fig. 7 to 10, in step S4, first, the contact layer 205 and the cap layer 204 outside the region D where the gate is to be formed are etched away, so as to form the patterned contact layer 205a and the patterned cap layer 204a in the region D where the gate is to be formed, and then the stacked patterned cap layer 204a and the patterned contact layer 205a are exposed to expose the surface of the barrier layer 203 in the region beyond the region D where the gate is to be formed; then, a passivation dielectric layer 208 is deposited on the patterned contact layer 205a and the exposed surface of the barrier layer 203, and further a photolithography and etching process is combined to open the passivation dielectric layer 208 of the region D where the gate is to be formed, so as to form a gate opening (not shown) of the patterned contact layer 205a exposing the region D where the gate is to be formed, wherein the passivation dielectric layer 208 is made of silicon dioxide, silicon nitride, and a high-k dielectric (e.g., hafnium oxide HfO) having a dielectric constant k higher than that of silicon nitride2Aluminum oxide Al2O3La, lanthanum oxide2O3Etc.); next, an electrode metal is coated on the patterned contact layer 205a by a process such as evaporation, an excess electrode metal is removed by a process such as etching, and thermal annealing is performed to form a gate electrode 209g, in which the gate electrode is formedThe gate 209g is a metal gate electrode, and the material thereof can be selected from conventional materials for manufacturing metal gate electrodes, such as at least one of TiN, TaN, Ni, Au, W, Cu, Pt, or Pd, and the patterned contact layer 205a realizes schottky contact between the gate electrode 209g and the patterned cap layer 205 a. Then, the passivation dielectric layer 208 and the barrier layer 203 on two sides of the gate stack structure are etched to form source and drain openings (not shown) exposing a part of the surface of the buffer layer 202; next, by a process such as evaporation, an electrode metal is filled in the source/drain openings, an excess electrode metal is removed by a process such as etching, and then thermal annealing is performed to form a source 209s and a drain 209d, where the source 209s and the drain 209d are in ohmic contact with the buffer layer 202, respectively. Finally, the final high electron mobility transistor device is obtained through processes of pressure welding, routing, packaging and the like. The material of the source 209s and the drain 209d includes, for example, at least one of TiN, TaN, Ni, Au, W, Cu, Pt, Pd, or the like.
Under the action of an applied gate voltage and polarization effect, two-dimensional electron gas can be formed at the interface of the buffer layer 202 and the barrier layer 203 below the gate electrode 209g, so that the device is conducted, i.e., the buffer layer 202 and barrier layer 203 interface between the source 209s and drain 209d, can form a two-dimensional electron gas channel 202c, the first ion implantation region 202a, second ion implantation region 202b, and patterned cap layer 204a can be interconnected, forming a wrap-around gate that can wrap around the top, bottom, and sidewalls of the two-dimensional electron gas channel 202c in the bottom region of the gate stack, the patterned cap layer 204a covers the top surface of the two-dimensional electron gas channel 202c, the first ion implantation region 202a covers the bottom surface of the two-dimensional electron gas channel 202c, and the second ion implantation regions 202b are located at two sides of the two-dimensional electron gas channel 202c to cover the two-dimensional electron gas channel 202c and the sidewalls perpendicular to the source 209s and the drain 209 d.
In this embodiment, the conductivity types of the first ion implantation region 202a, the second ion implantation region 202b and the cap layer 204 are all P-type, so that the surrounding gate surrounding the two-dimensional electron channel is a P-type gate, and the fabricated high electron mobility transistor is a P-type enhancement GaN-based high electron mobility transistor.
In the method for manufacturing the high electron mobility transistor of this embodiment, first, high-energy P-type ion implantation is performed on the buffer layer in the region where the gate is to be formed, so as to form a first ion implantation region in the buffer layer in the region where the gate is to be formed, and then, a second ion implantation region communicated with the first ion implantation region and the cap layer is formed by performing local P-type ion shallow implantation and performing annealing activation, so as to form a P-type wrap gate surrounding the two-dimensional electron gas channel. Due to the Gaussian distribution characteristic of ion injection, in the bottom area of the gate stack structure, the concentration of P-type ions in a film layer close to the interface of the barrier layer and the buffer layer and above the interface is low, so under the action of an external gate voltage and a polarization effect, two-dimensional electron gas can still be formed at the interface of the buffer layer and the barrier layer below the gate electrode, so that the device is conducted, the P-type surrounding gate can surround the top surface and the bottom surface of a two-dimensional electron gas channel and the side wall perpendicular to the source electrode and the drain electrode, the control capability of the gate electrode on the two-dimensional electron gas channel is improved, the threshold voltage of the device can be further improved, and meanwhile, the resistance influence on the conduction of the device is. In addition, when the device is turned off, the P-type surrounding gate can help to exhaust two-dimensional electron gas in the two-dimensional electron gas channel, the turn-off leakage is reduced, and meanwhile, the depletion region of the two-dimensional electron gas is easier to expand into the first ion injection region below the bottom surface of the two-dimensional electron gas channel, so that the withstand voltage of the device is improved.
In addition, it should be noted that the technical solution of the present invention is not limited to stacking the transition layer 201, the buffer layer 202, the barrier layer 203, the cap layer 204, and the contact layer 205 on the substrate 200, and in other embodiments of the present invention, corresponding film layers may be appropriately inserted or omitted according to device design requirements, for example, another semiconductor layer may be inserted between the barrier layer and the cap layer, or another semiconductor layer may be inserted between the substrate and the transition layer, and so on.
Based on the same inventive concept, the present embodiment further provides a high electron mobility transistor, which is formed by using the method for manufacturing the high electron mobility transistor provided in the present embodiment. Referring to fig. 7 to 10, the hemt includes a substrate 200, a source 209s, a drain 209d, a barrier layer 203, a gate stack structure, a buffer layer 202 having a first conductivity type (e.g., N-type), a first ion implantation region 202a doped with dopant ions of a second conductivity type (e.g., P-type), and a second ion implantation region 202b doped with dopant ions of the second conductivity type (e.g., P-type).
The substrate 200 may be any suitable semiconductor substrate, such as a gallium nitride (GaN) substrate, a silicon (Si) substrate, a silicon carbide (SiC) substrate, or sapphire (Al) substrate2O3) A substrate, etc.
The buffer layer 202 is formed on the substrate 200, and may be made of one or more of gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), gallium arsenide (GaAs), indium aluminum nitride (InAlN), or the like. The buffer layer 202 may be a single-layer film structure, or may be a composite structure in which multiple films are stacked in sequence from bottom to top, for example, a composite material layer in which Al composition gradually decreases along the growth direction of the buffer layer.
Optionally, a transition layer 201 is further sandwiched between the buffer layer 202 and the substrate 200, and a material of the transition layer 201 may include one or more of aluminum gallium nitride (AlGaN), aluminum nitride (AlN), silicon nitride (SiN), indium nitride (InN), indium aluminum nitride (InAlN), indium gallium nitride (InGaN), and the like.
The barrier layer 203 is formed on the buffer layer 202, and the barrier layer 203 and the buffer layer 202 are made of different materials, and the barrier layer 203 and the buffer layer 202 can constitute a semiconductor heterojunction of the device. Upon application of a gate voltage, a two-dimensional electron gas (2 DEG) of high electron mobility can be formed at and near the interface between the barrier layer 203 and the buffer layer 202, i.e., a two-dimensional electron gas channel 202c for transporting current can be formed between the source and drain electrodes. The conductivity type of the barrier layer 203 is N-type, and the material thereof includes one or more of AlGaN, InAlN, AlN, InN, and InGaN.
The gate stack structure is formed in a region D where a gate is to be formed, and includes a patterned cap layer 204a and a gate electrode 209g sequentially stacked on the barrier layer 203. The patterned cap layer 204a has a second conductivity type, and the material thereof includes one or more of P-type ion doped GaN (denoted as P-GaN), P-type ion doped InGaN (denoted as P-InGaN), P-type ion doped AlGaN (denoted as P-AlGaN), P-AlGaN with a gradually changed Al composition, or P-InGaN with a gradually changed In composition. The gate electrode 209g is a metal gate electrode, and the material thereof can be selected from conventional materials for manufacturing metal gate electrodes, such as at least one of TiN, TaN, Ni, Au, W, Cu, Pt, or Pd. Optionally, the gate stack structure further includes a patterned contact layer 205a sandwiched between the patterned cap layer 204a and the gate electrode 209g, the patterned contact layer 205a realizes schottky contact between the gate electrode 209g and the patterned cap layer 205a, and the patterned contact layer 205a has the same conductivity type as the patterned cap layer 204a but different material from the patterned cap layer 204 a. Optionally, the material of the patterned contact layer 205a includes one or more of P-type ion-doped GaN (denoted as P-GaN), P-type ion-doped InGaN (denoted as P-InGaN), P-type ion-doped AlGaN (denoted as P-AlGaN), P-AlGaN with graded Al composition, or P-InGaN with graded In composition.
The first ion implantation region 202a is formed in the buffer layer 202 covered at the bottom of the gate stack structure. The second ion implantation regions 202b are formed in a plurality of local regions covered by the bottom of the gate stack structure, and extend from the first ion implantation regions 202a to the sidewalls of the patterned cap layer 204a from bottom to top in at least a partial thickness of each of the local regions, and the doping concentration of the second conductivity type dopant ions in the second ion implantation regions 202b is higher than that of the second conductivity type dopant ions in the first ion implantation regions 202 a.
The source 209s and the drain 209d are formed on two sides of the gate stack structure and the bottom of the gate stack structure is in electrical contact with the buffer layer 202. The material of the source 209s and the drain 209d includes, for example, at least one of TiN, TaN, Ni, Au, W, Cu, Pt, Pd, or the like. After the gate voltage is applied, a two-dimensional electron gas channel 202c is formed at and near the interface between the buffer layer 202 and the barrier layer 203 between the source 209s and the drain 209d, the first ion implantation region 202a, the second ion implantation region 202b, and the patterned cap layer 204a can be connected to each other to form a surrounding gate that can surround the top surface, the bottom surface, and the side walls of the two-dimensional electron gas channel 202c, wherein the patterned cap layer 204a covers the top surface of the two-dimensional electron gas channel 202c, the first ion implantation region 202a covers the bottom surface of the two-dimensional electron gas channel 202c, and the second ion implantation region 202b is located at two sides of the two-dimensional electron gas channel 202c to cover the side walls of the two-dimensional electron gas channel 202c perpendicular to the source 209s and the drain 209 d. The surrounding gate has a second conductivity type.
Optionally, the doped ions of the second conductivity type doped in the first ion implantation region 202a, the second ion implantation region 202b and the patterned cap layer 204a respectively include at least one of magnesium ions, aluminum ions, fluorine ions and carbon ions.
In the high electron mobility transistor of this embodiment, under an applied gate voltage and a polarization effect, a two-dimensional electron gas channel can be formed at and near the interface between the buffer layer and the barrier layer below the gate electrode and between the source and the drain, and because the first ion implantation region, the second ion implantation region, and the patterned cap layer can be connected to each other, a surrounding gate capable of surrounding the top surface and the bottom surface of the two-dimensional electron gas channel and the sidewall perpendicular to the source and the drain is formed, so that the control capability of the gate electrode on the two-dimensional electron gas channel can be improved by the surrounding gate, and the threshold voltage of the device can be further improved. In addition, when the device is turned off, the surrounding gate can help to exhaust two-dimensional electron gas in the two-dimensional electron gas channel, the turn-off leakage is reduced, and meanwhile, the depletion region of the two-dimensional electron gas is easier to expand into the first ion injection region below the bottom surface of the two-dimensional electron gas channel, so that the withstand voltage of the device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
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