JP2008243881A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device as a hetero-junction field effect transistor that copes with high output and high breakdown voltage, and also to provide its manufacturing method. <P>SOLUTION: The semiconductor device is a hetero-junction field effect transistor, and it is provided with: an Al<SB>x</SB>Ga<SB>1-x</SB>N channel layer 3 that is formed on a substrate at composition ratio x (0<x<1) of Al; an Al<SB>y</SB>Ga<SB>1-y</SB>N barrier layer 4 that is formed on the channel layer 3 at composition ratio y (0<y≤1) of Al; and a source/drain electrode 6 and a gate electrode 7 that are formed on the barrier layer 4. The composition ratio y is larger than the composition x. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device of a heterojunction field effect transistor and a manufacturing method thereof.

  In a conventional heterojunction field effect transistor of a semiconductor device containing nitride, a GaN layer is used as a channel layer. A specific configuration is disclosed in Non-Patent Document 1. Non-Patent Document 1 discloses an L-band high-power AlGaN / GaN heterojunction FET on a SiC substrate, which is a heterojunction field effect transistor made of a nitride semiconductor using a GaN layer as a channel layer.

Yasuhiro Okamoto, 5 others, "L-band high-power AlGaN / GaN heterojunction FET on SiC substrate", IEICE Technical Report, IEICE, 2002, ED2002-94, pp.85-88

  However, in the conventional heterojunction field effect transistor made of a nitride semiconductor, a desired output cannot be obtained and a high output is required. In order to increase the output of the heterojunction field effect transistor, increasing the breakdown voltage of the device has been one effective means.

  Accordingly, an object of the present invention is to provide a semiconductor device of a heterojunction field effect transistor capable of increasing the output and the withstand voltage, and a method for manufacturing the same.

The solution according to the present invention includes an Al _x Ga _1-x N channel layer having an Al composition ratio x (0 <x <1) formed on a substrate and an Al composition formed on the channel layer. A heterojunction field effect transistor semiconductor device comprising an Al _y Ga _1-y N barrier layer having a ratio y (0 <y ≦ 1), and source / drain electrodes and a gate electrode formed on the barrier layer. The composition ratio y is larger than the composition ratio x.

Since the semiconductor device described in the present invention uses Al _x Ga _1-x N (0 <x <1) having a larger band gap than GaN and a larger breakdown electric field for the channel layer, higher output and higher breakdown voltage are achieved. It is possible to provide a heterojunction field-effect transistor semiconductor device capable of achieving the above.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the structure of a heterojunction field effect transistor according to the present embodiment. In the heterojunction field effect transistor shown in FIG. 1, a semi-insulating SiC substrate 1 is provided in the lowermost layer, and a channel layer 3 having a thickness of 1 μm made of Al _0.6 Ga _0.4 N is provided thereon via a buffer layer 2. ing. Further, in the heterojunction field effect transistor shown in FIG. 1, a barrier layer 4 made of AlN and heterojunction with the channel layer 3 is provided. Further, the heterojunction field effect transistor shown in FIG. 1 is provided with element isolation regions 5 in the regions on both sides in the drawing, source / drain electrodes 6 made of Ti / Al on the barrier layer 4, and made of Ni / Au. Gate electrode 7 is provided.

  The off breakdown voltage of the heterojunction field effect transistor depends on the breakdown electric field of the channel layer 3. Therefore, in order to increase the withstand voltage of the heterojunction field effect transistor, it is necessary to use a material having a large breakdown field for the channel layer 3. The off breakdown voltage of the heterojunction field effect transistor will be described in detail below.

  First, when the channel layer 3 immediately below the gate electrode 7 is depleted and then the depletion layer is assumed to extend only in the lateral direction (drain electrode side) of the channel layer 3, the generated electric field forms the channel layer 3. The voltage at which the breakdown electric field of the material to be reached can be calculated as the off breakdown voltage of the field effect transistor. The calculation method is shown below. When the length of the depletion layer is x and the carrier concentration of the channel layer 3 is Nd, the electric field E (x) and the potential difference V (x) generated when the length of the depletion layer is x are expressed by the following formula 1. It can be solved using Poisson's equation.

  When the depletion layer is not extended (x = 0), neither the electric field E (0) nor the potential difference V (0) is generated (E (0) = 0, V (0) = 0). When Equation 1 is solved with 境界 as the boundary condition, the electric fields E (x) and V (x) are obtained as Equations 2 and 3.

Since the off-state breakdown occurs when the generated electric field E (x) reaches the dielectric breakdown electric field (Ea) of the material constituting the channel layer 3, the voltage (off breakdown voltage) V _{BD at} that time is Is calculated as follows.

According to Equation 4, the off breakdown voltage is proportional to the square of the dielectric breakdown electric field of the material constituting the channel layer 3. The breakdown electric field of a semiconductor material depends on the band gap, and the breakdown electric field is higher as the band gap is larger. Therefore, the breakdown electric field of AlN is higher than that of GaN, and the breakdown electric field of GaN is 5.0 × 10 ⁶ (V / cm), whereas the breakdown electric field of AlN is 1.2 × 10 6. ⁷ (V / cm) and high.

Generally, the breakdown electric field of AlGaN is obtained by linearly interpolating the breakdown electric field of GaN and the breakdown electric field of AlN with an Al composition ratio. Accordingly, the breakdown electric field of AlGaN increases as the Al composition ratio increases, and the off breakdown voltage of the heterojunction field effect transistor using the AlGaN as the channel layer 3 increases. For example, when AlGaN having an Al composition ratio of 0.8 is used for the channel layer 3 shown in FIG. 1, the breakdown electric field is 9.2 × 10 ⁶ (V / cm), which is about twice that of GaN. It becomes. Therefore, it is considered that the off breakdown voltage of the heterojunction field effect transistor is about four times that in the case where GaN is used for the channel layer 3.

  The heterojunction field effect transistor according to the present invention is not limited to the heterojunction field effect transistor shown in FIG. 1, and the same effect can be obtained even with the structure described below. First, instead of the SiC substrate 1 shown in FIG. 1, Si, sapphire, GaN, AlN or the like may be used for the substrate. Further, the channel layer 3 and the barrier layer 4 shown in FIG. 1 are not necessarily limited to the Al composition ratio described above. If the Al composition ratio of AlGaN constituting the channel layer 3 is x and the Al composition ratio of AlGaN constituting the barrier layer 4 is y, the heterojunction according to the present invention can be configured so that x <y is satisfied. The field effect transistor may have any composition ratio. However, the composition ratio x is 0 <x <1, and the composition ratio y is 0 <y ≦ 1.

  As described above, the higher the Al composition ratio x of the channel layer 3 is, the higher the dielectric breakdown electric field is, and accordingly the off breakdown voltage is improved. Therefore, the higher the Al composition ratio x of the channel layer 3 is preferable. . In addition, since AlGaN forming the barrier layer 4 also has a higher band gap when the Al composition ratio y is higher, leakage current flowing from the gate electrode 7 to the drain electrode 6 can be suppressed. It should be noted that the band gap is the largest in AlN having the largest A composition ratio y. Therefore, the Al composition ratio y of the barrier layer 4 is preferably higher than the Al composition ratio x of the channel layer 3. These layers are not necessarily composed of one layer having the same composition, and may be composed of multilayer films having different Al composition ratios. Further, these layers may contain n-type or p-type impurities.

  Furthermore, the thickness of the barrier layer 4 shown in FIG. 1 is not necessarily 10 nm as long as the two-dimensional electron gas is generated. The thickness of the barrier layer 4 for generating the two-dimensional electron gas will be described in detail in the second embodiment. Further, the thickness of the channel layer 3 shown in FIG. 1 is not necessarily 1 μm, and may be 0.005 μm to 4 μm.

  Further, the source / drain electrode 6 shown in FIG. 1 is not necessarily formed of Ti / Al. If ohmic characteristics can be obtained, metals such as Ti, Al, Ni, Ta, Au, Mo, W, Or you may form with the multilayer film comprised from these.

Further, the gate electrode 7 shown in FIG. 1 is not necessarily formed of Ni / Au, but a metal such as Al, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi ₂ , or TiN, WN, etc. The nitride metal may be used.

  Next, as a modification of the heterojunction field effect transistor shown in FIG. 1, the heterojunction field effect transistor shown in FIG. 2 is shown. In the heterojunction field effect transistor shown in FIG. 2, a spacer layer 10 made of GaN or AlN having a thickness of 0.1 nm to 5 nm is formed between the channel layer 3 and the barrier layer 4. As shown in FIG. 2, by inserting a binary semiconductor (spacer layer 10), the electron mobility at the heterointerface can be improved and a large drain current can flow.

  Next, as a modification of the heterojunction field effect transistor shown in FIG. 1, the heterojunction field effect transistor shown in FIG. 3 is shown. In the heterojunction field effect transistor shown in FIG. 3, a cap layer 11 made of GaN having a film thickness of 0.1 nm to 5 nm is formed on the barrier layer 4. By providing the cap layer 11 as shown in FIG. 3, the Schottky barrier of the gate electrode 7 is increased, and the off breakdown voltage can be increased.

  Next, as a modification of the heterojunction field effect transistor shown in FIG. 1, the heterojunction field effect transistor of FIG. 4 is shown. In the heterojunction field effect transistor shown in FIG. 4, a region 12 containing a high concentration of an n-type impurity such as Si is formed in part of the barrier layer 4 and the channel layer 3 immediately below the source / drain electrode 6. ing. By forming the region 12 shown in FIG. 5, the contact resistance can be lowered.

  Next, the heterojunction field effect transistor of FIG. 5 is shown as a modification of the heterojunction field effect transistor shown in FIG. The heterojunction field effect transistor shown in FIG. 5 has a configuration in which part or all of the barrier layer 4 immediately below the source / drain electrode 6 is removed. Furthermore, in this modification, a configuration in which all of the barrier layer 4 immediately below the source / drain electrode 6 and a part of the channel layer 3 are removed may be employed. In the example shown in FIG. 5, a part of the barrier layer 4 directly under the source / drain electrode 6 is removed. With the configuration shown in FIG. 5, the contact resistance can be lowered.

  Next, as a modification of the heterojunction field effect transistor shown in FIG. 1, the heterojunction field effect transistor shown in FIG. 6 is shown. In the heterojunction field effect transistor shown in FIG. 6, an insulating film layer 13 such as AlOx, SiNx, SiOx, HfOx, TiOx or the like is formed on the barrier layer 4 including just below the gate electrode 7. In the example shown in FIG. 6, an insulating film layer 13 is formed on a portion other than the barrier layer 4 where the source / drain electrodes 6 are formed and on the element isolation region 5. As shown in FIG. 6, by providing the insulating film layer 13, the gate leakage current can be reduced and the breakdown voltage between the gate and the drain can be improved.

  Next, the heterojunction field effect transistor of FIG. 7 is shown as a modification of the heterojunction field effect transistor of FIG. In the heterojunction field effect transistor shown in FIG. 7, the gate electrode structure is not a planar structure, but a recess gate structure in which the gate electrode 7 is formed inside a region where a part of the barrier layer 4 between the source / drain electrodes 6 is etched. Adopted. As shown in FIG. 7, when the gate electrode structure is a recess gate structure, the source resistance can be reduced as compared with the planar structure.

  Next, as a modified example of the heterojunction field effect transistor shown in FIG. 1, the heterojunction field effect transistor of FIG. 8 is shown. In the heterojunction field effect transistor shown in FIG. 8, the gate electrode structure is not a planar structure, and a buried gate in which the gate electrode 7 is formed so as to cover a region where a part of the barrier layer 4 between the source / drain electrodes 6 is etched. The structure is adopted. As shown in FIG. 8, when the gate electrode structure is a buried gate structure, the source resistance can be reduced as compared with the planar structure. In addition, the electric field concentrated on the edge portion of the gate electrode 7 on the drain electrode side during high voltage operation can be relaxed, and the withstand voltage can be increased.

  Note that the configurations of the above-described modifications are not necessarily employed separately, and a heterojunction field effect transistor may be configured by combining them.

(Embodiment 2)
FIG. 9 shows the energy band structure (Energy (eV)) and carrier concentration (Carrier concentration) in the depth direction (depth (nm)) of the barrier layer 4 and the channel layer 3 of the heterojunction field effect transistor shown in FIG. The calculation result of cm ^<-3> )) is shown. The calculation result is a self-consistent solution of the Poisson equation and the Schrodinger equation. In addition, generally used values are used as the physical property values used in the above calculation.

In the graph shown in FIG. 9, the integrated value of the carrier concentration in the depth direction and the sheet carrier concentration (Ns), the sheet carrier concentration of 1.6 × 10 ¹³ heterojunction field effect transistor shown in FIG. 1 (cm ^{- 2} ).

Similarly, when the Al composition ratio x of the channel layer 3 and the Al composition ratio y of the barrier layer 4 are combined, the sheet carrier concentration (Ns) (Sheet carrier density (cm ⁻² )) and the film thickness of the barrier layer 4 are obtained. The relationship with (t) (Barrier layer thickness (nm)) is shown in FIGS. FIG. 10 is a graph in which the Al composition ratio x of the channel layer 3 is fixed to 0 and the Al composition ratio y of the barrier layer 4 is changed from 0.2 to 1.0. FIG. 11 is a graph in which the Al composition ratio x of the channel layer 3 is fixed to 0.2 and the Al composition ratio y of the barrier layer 4 is changed from 0.4 to 1.0. FIG. 12 is a graph in which the Al composition ratio x of the channel layer 3 is fixed to 0.4 and the Al composition ratio y of the barrier layer 4 is changed from 0.6 to 1.0. FIG. 13 is a graph in which the Al composition ratio x of the channel layer 3 is fixed to 0.6 and the Al composition ratio y of the barrier layer 4 is changed from 0.8 to 1.0. FIG. 14 is a graph in which the Al composition ratio x of the channel layer 3 is 0.8 and the Al composition ratio y of the barrier layer 4 is 1.0.

  As can be seen from the graphs of FIGS. 10 to 14, when the barrier layer 4 reaches a certain film thickness, the sheet carrier concentration starts to increase rapidly. Table 1 shows the results of the film thickness of the barrier layer 4 in which the sheet carrier concentration rapidly increases for each combination of the Al composition ratio x and the Al composition ratio y.

  In Table 1, for example, when the Al composition ratio x of the channel layer 3 is 0.2 and the Al composition ratio y of the barrier layer 4 is 0.4, the thickness of the barrier layer 4 may be 5 nm or more. I understand that. When the barrier layer 4 has a thickness not less than the value shown in Table 1 (5 nm in the above example), a sufficiently high sheet carrier concentration can be obtained, and a sufficiently high drain current can be obtained when a field effect transistor is manufactured. can get.

  In the present embodiment, the film thickness of the barrier layer 4 is determined from the values based on Table 1, but for the portions of the Al composition ratio x, y not shown in Table 1, values adjacent to the portions are set. Find by dividing up. That is, when an Al composition ratio x is between x1 and x2 and an Al composition ratio y is between y1 and y2, first, t (x1, y1) and t (x1, y2) are internally divided, t (x2, y1) and t (x2, y2) are internally divided. Then, the thickness of the barrier layer 4 equal to or larger than the value of t (x, y) obtained by further internally dividing t (x1, y) and t (x2, y) obtained by the above internal division is formed. .

  More specifically, when the Al composition ratio x and the Al composition ratio y are listed in Table 1, the thickness t (nm) of the barrier layer is determined from the value of t (x, y) in Table 1. Also thicken. For example, when the Al composition ratio x is 0.1 and the Al composition ratio y is 0.2, it can be seen from Table 1 that the thickness t of the barrier layer should be 8 nm or more.

  Further, when the Al composition ratio x and the Al composition ratio y are not described in Table 1 and have a relationship of x + 0.05 ≦ y <x + 0.1, 0.05 step of the Al composition ratio x or less The maximum value described in Table 1 is x1, the value obtained by adding 0.05 to x1 is x2, and the maximum value described in Table 1 is y1 within the 0.05 step range below the Al composition ratio y. , Y1 plus 0.05 is y2. Then, from the values of t (x1, y1) and t (x1, y2) in Table 1, y2 × t (x1, y1) −y1 × t (x1, y2) + {t (x1, y2) −t ( x1, y1)} × y] /0.05=t (x1, y) is obtained. Further, from the value of t (x2, y2) in Table 1 and the value of t (x1, y), [x2 × t (x1, y) −x1 × t (x2, y2) + {t (x2, y2) −t (x1, y)} × x] /0.05=t (x, y) is obtained, and the thickness t (nm) of the barrier layer is equal to or greater than the value of t (x, y). Of thickness.

  For example, when the Al composition ratio x is 0.13 and the Al composition ratio y is 0.19, the above relationship is satisfied. Therefore, the maximum value described in Table 1 is 0.1 within the range of 0.05 step (0.13 to 0.08) below the Al composition ratio x of 0.13, and that value is x1. . And 0.15 which added 0.05 to 0.1 which is x1 becomes x2. Similarly, the maximum value described in Table 1 is 0.15 within the range of 0.05 step (0.19 to 0.14) below the Al composition ratio y of 0.19. To do. And 0.2 which added 0.05 to 0.15 which is y1 becomes y2.

  T (x1, y) is t (0.1,0.19) = [0.2 × t (0.1,0.15) −0.15 × t (0.1,0.2). ) + {T (0.1,0.2) -t (0.1,0.15)} × 0.19] /0.05= [0.2 × 15−0.15 × 8 + {8− 15} × 0.19] /0.05=9.4. Further, t (x, y) is t (0.13, 0.19) = [0.15 × t (0.1, 0.19) −0.1 × t (0.15, 0.2). ) + {T (0.15,0.2) -t (0.1,0.19)} × 0.13] /0.05= [0.15 × 9.4-0.1 × 16 + { 16−9.4} × 0.13] /0.05=13.36. As a result, the thickness t (nm) of the barrier layer is t (0.13, 0.19) = 13.36 nm or more.

  In addition, when the Al composition ratio x and the Al composition ratio y are not described in Table 1 and have a relationship of y ≧ x + 0.1, the Al composition ratio x and the Al composition ratio y are within a range 0.05 steps smaller than the Al composition ratio x. The maximum value described in 1 is x1, the value obtained by adding 0.05 to x1 is x2, the maximum value described in Table 1 is y1 within a range 0.05 steps smaller than the Al composition ratio y, and y1 is 0.05. Let y2 be the value obtained by adding. Then, from the values of t (x1, y1) and t (x2, y1) in Table 1, [x2 × t (x1, y1) −x1 × t (x2, y1) + {t (x2, y1) −t ( x1, y1)} × x] /0.05=t (x, y1) is obtained. From the values of t (x1, y2) and t (x2, y2) in Table 1, [x2 × t (x1, y2) −x1 × t (x2, y2) + {t (x2, y2) −t (x1, y2)} × x] /0.05=t (x, y2) is obtained. Further, [y2 × t (x, y1) −y1 × t (x, y2) + {t (x, y2)) obtained from the value of t (x, y1) and the value of t (x, y2). −t (x, y1)} × y] /0.05=t (x, y) is obtained, and the thickness t (nm) of the barrier layer is equal to or greater than the value of t (x, y). Say it.

  For example, when the Al composition ratio x is 0.22 and the Al composition ratio y is 0.42, the above relationship is satisfied. Therefore, the maximum value described in Table 1 is 0.2 within a range 0.05 steps smaller than the Al composition ratio x of 0.22 (0.22 to 0.17), and this value is x1. And 0.25 which added 0.05 to 0.2 which is x1 becomes x2. Similarly, in the range 0.05 steps smaller than the Al composition ratio y of 0.42 (0.42 to 0.37), the maximum value described in Table 1 is 0.4, and this value is y1. . And 0.45 which added 0.05 to y1 0.4 turns into y2.

  T (x, y1) is t (0.22,0.4) = [0.25 × t (0.2,0.4) −0.2 × t (0.25,0.4). ) + {T (0.25,0.4) -t (0.2,0.4)} × 0.22] /0.05= [0.25 × 5-0.2 × 8 + {8− 5} × 0.22] /0.05=6.2. t (x, y2) is t (0.22,0.45) = 0.25 × t (0.2,0.45) −0.2 × t (0.25,0.45) + { t (0.25,0.45) -t (0.2,0.45)} × 0.22] /0.05=0.25×4-0.2×6+ {6-4} × 0 .22] /0.05=4.8.

  Furthermore, t (x, y) is t (0.22,0.42) = [0.45 × t (0.22,0.4) −0.4 × t (0.22,0.45). ) + {T (0.22,0.45) -t (0.22,0.4)} × 0.42] /0.05= [0.45 × 6.2-0.4 × 4. 8+ {4.8−6.2} × 0.42] /0.05=5.64. As a result, the thickness t (nm) of the barrier layer is t (0.22, 0.42) = 5.64 nm or more.

  In addition, the method of calculating | requiring the part which is not described in Table 1 is not restricted to the above-mentioned method, The function applicable to the said part is calculated | required, The method of complementing the value of the film thickness t of a barrier layer using the said function etc. .

(Embodiment 3)
15 to 18 show a manufacturing process of the heterojunction field effect transistor shown in FIG. 15 to 18, the same components as those shown in FIG. 1 are denoted by the same reference numerals and detailed description thereof is omitted.

First, in FIG. 15, an epitaxial growth method such as MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy) method is applied to the SiC substrate 1 to form a buffer layer 2 and a channel layer 3 made of Al _0.6 Ga _0.4 N. And the barrier layer 4 made of AlN is epitaxially grown in order.

  Next, in FIG. 16, for example, a metal layer such as Ti, Al, Ni, Ta, Au, Mo, and W is deposited using a vapor deposition method or a sputtering method, and formed on the source / drain electrode 6 by a lift-off method or the like.

  Next, in FIG. 17, the element isolation region 5 is formed in the channel layer 3 and the barrier layer 4 outside the region for manufacturing the heterojunction field effect transistor by using an ion implantation method or an etching method. The element isolation region 5 shown in FIG. 17 was formed using an ion implantation method.

Next, in FIG. 18, a layer made of a metal such as Al, Pt, Au, Ni, Pd, a silicide such as IrSi, PtSi, NiSi ₂ or a nitride metal such as TiN, WN is deposited or sputtered. The gate electrode 7 is formed by a lift-off method or the like.

  By performing the manufacturing process described above, the heterojunction field effect transistor shown in FIG. 1 can be manufactured. Note that although the above-described manufacturing process describes only the minimum necessary process to operate as a transistor, the device is finally completed through a process of forming a protective film, a wiring, a via hole, and the like.

  Although typical conditions have been described above, a heterojunction field effect transistor capable of obtaining the effects of the present invention can be manufactured even under the following conditions.

  First, when the channel layer 3 and the barrier layer 4 shown in FIG. 15 are epitaxially grown, the flow rate, pressure, and temperature of trimethylammonium, trimethylgallium, ammonia, and the like, which are AlGaN source gases, are adjusted to obtain the desired channel layer 3 and barrier layer 4 Al composition ratio can be obtained. Thus, a heterojunction field effect transistor that satisfies the Al composition ratio condition described in Embodiment Mode 1 can be manufactured.

  Further, after the channel layer 3 shown in FIG. 15 is epitaxially grown, a thin layer (spacer layer 10) made of GaN or AlN having a thickness of 0.1 to 5 nm is epitaxially grown, and the barrier layer 4 is epitaxially grown on the spacer layer 10. May be. Accordingly, the heterojunction field effect transistor shown in FIG. 2 described in Embodiment Mode 1 can be manufactured, and the heterojunction field effect transistor capable of improving the electron mobility and flowing a large drain current can be obtained. Obtainable.

  Further, after the barrier layer 4 shown in FIG. 15 is epitaxially grown, a thin layer (cap layer 11) made of GaN having a thickness of 0.1 to 5 nm may be epitaxially grown. Thus, the heterojunction field effect transistor shown in FIG. 3 described in Embodiment Mode 1 can be manufactured, and the off breakdown voltage can be increased.

  Further, the formation of the source / drain electrode 6 shown in FIG. 16, the formation of the element isolation region 5 shown in FIG. 17, and the formation of the gate electrode 7 shown in FIG. 18 are not necessarily performed in the order described above. It may be replaced. For example, a manufacturing process in which the element isolation region 5 is formed before the source / drain electrode 6 is formed may be used.

  Further, in the formation of the source / drain electrode 6 shown in FIG. 16, a region 12 in which a semiconductor such as Si is doped with n-type ions at a high concentration using an ion implantation method or the like is formed, and the source 12 is formed on the region 12. / Drain electrode 6 may be formed. Thus, the heterojunction field effect transistor shown in FIG. 4 described in Embodiment Mode 1 can be manufactured, and the contact resistance can be reduced.

In the formation of the source / drain electrode 6 shown in FIG. 16, after removing a part or all of the barrier layer 4 immediately below the source / drain electrode 6 by using, for example, a dry etching method using Cl ₂ or the like, A source / drain electrode 6 may be formed. In addition to the above example, the source / drain electrode 6 may be formed after removing all of the barrier layer 4 immediately below the source / drain electrode 6 and removing a part of the channel layer 3. Thus, the heterojunction field effect transistor shown in FIG. 5 described in Embodiment 1 can be manufactured, and the contact resistance can be reduced.

  Further, in the formation of the gate electrode 7 shown in FIG. 17, an insulating film 13 such as AlOx, SiNx, SiOx, HfOx, TiOx or the like is deposited on the barrier layer 4 by using, for example, an evaporation method or a plasma CVD method, and the insulation A gate electrode 7 may be formed on the film 13. Thus, the heterojunction field effect transistor shown in FIG. 6 described in Embodiment 1 can be manufactured, the gate leakage current can be reduced, and the breakdown voltage between the gate and the drain can be improved. For final use as a device, a part of the source / drain electrode 6 covered with the insulating film 13 is removed by wet etching using, for example, hydrofluoric acid, and a wiring is formed in the part. There is a need to.

In the formation of the gate electrode 7 shown in FIG. 17, a part of the barrier layer 4 between the source / drain electrodes 6 is removed by using, for example, a dry etching method using Cl ₂ or the like, and a recess is formed in advance. Then, the gate electrode 7 may be formed. Thus, the heterojunction field effect transistor shown in FIGS. 7 and 8 described in Embodiment Mode 1 can be manufactured, and the source resistance can be reduced as compared with the planar structure.

It is sectional drawing of the heterojunction field effect transistor which concerns on Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is sectional drawing of the heterojunction field effect transistor which concerns on the modification of Embodiment 1 of this invention. It is a figure which shows the calculation result of the energy band structure and the carrier concentration in the depth direction of the barrier layer of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and a channel layer. It is a figure which shows the relationship between the sheet carrier density | concentration of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and the film thickness of a barrier layer. It is a figure which shows the relationship between the sheet carrier density | concentration of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and the film thickness of a barrier layer. It is a figure which shows the relationship between the sheet carrier density | concentration of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and the film thickness of a barrier layer. It is a figure which shows the relationship between the sheet carrier density | concentration of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and the film thickness of a barrier layer. It is a figure which shows the relationship between the sheet carrier density | concentration of the heterojunction field effect transistor which concerns on Embodiment 2 of this invention, and the film thickness of a barrier layer. It is a figure for demonstrating the manufacturing process of the heterojunction field effect transistor which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing process of the heterojunction field effect transistor which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing process of the heterojunction field effect transistor which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the manufacturing process of the heterojunction field effect transistor which concerns on Embodiment 1 of this invention.

Explanation of symbols

  1 SiC substrate, 2 buffer layer, 3 channel layer, 4 barrier layer, 5 element isolation region, 6 source / drain electrode, 7 gate electrode, 10 spacer layer, 11 cap layer, 12 region, 13 insulating film layer.

Claims (4)

An Al _x Ga _1-x N channel layer having an Al composition ratio x (0 <x <1) formed on the substrate;
A barrier layer of Al _y Ga _1-y N having an Al composition ratio y (0 <y ≦ 1) formed on the channel layer;
A heterojunction field effect transistor semiconductor device comprising a source / drain electrode and a gate electrode formed on the barrier layer,
The semiconductor device according to claim 1, wherein the composition ratio y is larger than the composition ratio x. The semiconductor device according to claim 1,
The semiconductor device, wherein the barrier layer is AlN. The semiconductor device according to claim 1,
The thickness t (nm) of the barrier layer is
(1) When the composition ratio x and the composition ratio y are listed in Table 1, the thickness is not less than the value of t (x, y) in Table 1.
(2) When the composition ratio x and the composition ratio y are not described in Table 1 and have a relationship of x + 0.05 ≦ y <x + 0.1,
Within the range of 0.05 steps below the composition ratio x, the maximum value described in Table 1 is x1, the value obtained by adding 0.05 to the x1 is x2, and 0.05 steps below the composition ratio y Within the range, the maximum value described in Table 1 is y1, the value obtained by adding 0.05 to the y1 is y2,
From the values of t (x1, y1) and t (x1, y2) in Table 1, y2 × t (x1, y1) −y1 × t (x1, y2) + {t (x1, y2) −t (x1 , Y1)} × y] /0.05=t (x1, y)
[X2 × t (x1, y) −x1 × t (x2, y2) + {t (x2) obtained from the value of t (x2, y2) in Table 1 and the value of t (x1, y) , Y2) −t (x1, y)} × x] /0.05=t (x, y) or more.
(3) When the composition ratio x and the composition ratio y are not described in Table 1 and y ≧ x + 0.1,
Within a range 0.05 steps smaller than the composition ratio x, the maximum value described in Table 1 is x1, and a value obtained by adding 0.05 to the x1 is x2, and within a range 0.05 steps smaller than the composition ratio y. In Table 1, the maximum value described in Table 1 is y1, the value obtained by adding 0.05 to y1 is y2,
From the values of t (x1, y1) and t (x2, y1) in Table 1, [x2 × t (x1, y1) −x1 × t (x2, y1) + {t (x2, y1) −t (x1) , Y1)} × x] /0.05=t (x, y1)
From the values of t (x1, y2) and t (x2, y2) in Table 1, [x2 × t (x1, y2) −x1 × t (x2, y2) + {t (x2, y2) −t (x1) , Y2)} × x] /0.05=t (x, y2)
[Y2 × t (x, y1) −y1 × t (x, y2) + {t (x, y2)) obtained from the value of t (x, y1) and the value of t (x, y2) -T (x, y1)} * y] /0.05=thickness equal to or greater than t (x, y).

Forming an Al _x Ga _1-x N channel layer having an Al composition ratio x (0 <x <1) on the substrate;
Forming an Al _y Ga _1-y N barrier layer having an Al composition ratio y (0 <y ≦ 1) and a composition ratio y larger than the composition ratio x on the channel layer;
Forming a source / drain electrode and a gate electrode on the barrier layer; and a method for manufacturing a semiconductor device of a heterojunction field effect transistor.

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