TWI685970B - Semiconductor structrue - Google Patents

Abstract

A semiconductor structure includes a substrate, a semiconductor layer, a lanthanum silicate layer and a gate electrode layer. The semiconductor layer is disposed on the substrate. The lanthanum silicate layer is disposed on the semiconductor layer, and the lanthanum silicate layer includes La₂O₃/SiO₂ composite oxide. The gate electrode layer is disposed on the lanthanum silicate layer.

Description

Semiconductor structure

The invention relates to a semiconductor structure and a manufacturing method thereof, and a semiconductor device.

In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high-power field effect transistors, high-frequency transistors, or high electron mobility transistors (HEMT), this III -Group V semiconductor compound transistors have the potential to replace traditional silicon transistors.

Traditional silicon transistors use silicon dioxide as the gate dielectric layer. Silicon dioxide has the advantages of lattice matching and excellent interface quality to silicon, which can enable silicon transistors to obtain larger capacitance values. However, III-V semiconductor transistors lack the native oxide like silicon dioxide to silicon as the gate dielectric layer. Therefore, as the demand for the unit capacitance of the integrated circuit device increases, it is necessary to develop a dielectric material with a higher dielectric coefficient as the gate dielectric layer of the group III-V semiconductor transistor.

According to various embodiments of the present invention, there is provided a semiconductor structure including a substrate, a semiconductor layer disposed on the substrate, a lanthanum silicate layer disposed on the semiconductor layer, and a gate electrode layer disposed on the lanthanum silicate layer. The lanthanum silicate layer contains lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide.

According to some embodiments of the present invention, the lanthanum silicate layer is formed by the solid state reaction of silicon dioxide and lanthanum oxide.

According to some embodiments of the invention, the lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide includes a composite oxide with the chemical formula LaSiO _x , where x is a value between 3 and 4.

According to some embodiments of the invention, the lanthanum silicate layer has a thickness of about 2 nanometers to about 50 nanometers.

According to some embodiments of the invention, the lanthanum silicate layer has a dielectric constant of about 12 to about 22.

According to some embodiments of the invention, the semiconductor layer includes a III-V semiconductor.

According to some embodiments of the present invention, the semiconductor layer includes indium gallium arsenide (InGaAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium phosphide (InP), gallium arsenide (GaAs), antimony Indium (InSb), Indium Gallium Antimonide (InGaSb), Gallium Nitride (GaN) or Aluminum Gallium Arsenide (AlGaAs).

According to various embodiments of the present invention, a method for manufacturing a semiconductor structure is provided, which includes forming a semiconductor layer on a substrate; forming a plurality of silicon dioxide layers and a plurality of lanthanum oxide layers on the semiconductor layer alternately; and rapidly annealing the silicon dioxide layer And a lanthanum oxide layer to form a lanthanum silicate layer; and a gate electrode layer is formed on the lanthanum silicate layer.

According to some embodiments of the invention, the lanthanum oxide layer has a thickness of about 0.3 nanometers to about 2 nanometers.

According to some embodiments of the invention, the silicon dioxide layer has a thickness of about 0.3 nm to about 2 nm.

According to some embodiments of the present invention, the rapid annealing step is performed at about 400°C to about 800°C.

According to some embodiments of the present invention, forming the lanthanum oxide layer and the silicon dioxide layer includes atomic layer deposition or molecular beam deposition.

According to various embodiments of the present invention, there is provided a semiconductor device including a substrate; a channel layer is disposed on the substrate; a barrier layer is disposed on the channel layer, the barrier layer has a groove, and the groove has a first side wall and a first The second side wall opposite to the side wall; the source electrode and the drain electrode are disposed on the barrier layer, and the source electrode is located at an end close to the first sidewall of the groove, and the drain electrode is located at an end close to the second sidewall of the groove; the gate dielectric The layer is disposed on the barrier layer and covers the groove, wherein the gate dielectric layer includes lanthanum silicate; and the gate is disposed on the gate dielectric layer, and the gate is filled into the groove, wherein the gate has the first The surface, the second surface opposite to the first surface, and the bottom surface between the first surface and the second surface.

According to some embodiments of the present invention, the gate dielectric layer has a thickness of about 2 nm to about 50 nm.

According to some embodiments of the invention, the bottom surface of the gate has a width of about 80 nanometers to about 3 microns.

According to some embodiments of the present invention, the distance between the first surface of the gate and the source is about 1 micrometer to about 5 micrometers.

According to some embodiments of the present invention, the distance between the second surface of the gate and the drain is about 2 microns to about 50 microns.

According to some embodiments of the present invention, it further includes a protective layer Placed on the gate dielectric layer.

According to some embodiments of the present invention, the channel layer and the barrier layer include III-V semiconductors.

10‧‧‧Method

12, 14, 16, 18‧‧‧Operation

100‧‧‧Semiconductor structure

110‧‧‧ substrate

120‧‧‧Semiconductor layer

130‧‧‧ Lanthanum silicate layer

132, 132a, 132b, 132c ‧‧‧ silicon dioxide layer

134, 134a, 134b, 134c ‧‧‧ Lanthanum oxide layer

140‧‧‧Gate electrode layer

200‧‧‧Semiconductor device

210‧‧‧ substrate

220‧‧‧channel layer

230‧‧‧Barrier layer

232‧‧‧groove

234‧‧‧Notch

236, 237‧‧‧Side

238‧‧‧Lower surface

240‧‧‧Source

250‧‧‧ Jiji

260‧‧‧Gate dielectric layer

262‧‧‧First surface

264‧‧‧Second surface

266‧‧‧Bottom

270‧‧‧Gate

T ₁ , T ₂ , T ₃ , T ₄ ‧‧‧ Thickness

D ₁ , D ₂ ‧‧‧Distance

S ₁ , S ₂ ‧‧‧ spacing

W ₁ ‧‧‧Width

FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments of the present invention.

2A-2D are cross-sectional views of various steps of the manufacturing process of the semiconductor structure according to some embodiments of the present invention.

3A-3E are cross-sectional views of various steps of the manufacturing process of the semiconductor device according to some embodiments of the present invention.

FIG. 4 is an electron microscope photograph of a lanthanum silicate layer of a semiconductor structure manufactured according to some embodiments of the present invention.

FIG. 5 is an I _D -V _GS characteristic curve of a semiconductor device according to some embodiments of the present invention.

FIG. 6 is a line graph of the gate voltage versus capacitance of the gate dielectric layer according to some embodiments of the present invention.

In the following, a plurality of embodiments of the present invention will be disclosed in the form of diagrams. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details The festival is not necessary. In addition, in order to simplify the illustration, some conventional structures and elements will be shown in a simple schematic manner in the illustration.

Relative spatial terms are used in this article, such as "below", "below", "above", "above", etc. This is to facilitate the description of the relative relationship between one element or feature and another element or feature, such as Shown in the figure. The true meaning of these spatial relative terms includes other orientations. For example, when the figure is turned upside down by 180 degrees, the relationship between one component and another component may change from "below" and "below" to "above" and "above". In addition, the relative spatial description used in this article should also be interpreted in the same way.

FIG. 1 is a flowchart of a method 10 of manufacturing a semiconductor structure according to various embodiments of the present invention. As shown in FIG. 1, the method 10 includes operation 12, operation 14, operation 16, and operation 18. 2A-2D are cross-sectional views of the semiconductor structure 100 manufactured according to the method 10 shown in FIG. 1 at various stages of the manufacturing process.

Referring to FIGS. 1 and 2A, in operation 12 of the method 10, a semiconductor layer 120 is formed on the substrate 110. According to some embodiments of the present invention, the semiconductor layer 120 includes a group III-V semiconductor. In some embodiments, the semiconductor layer 120 includes indium gallium arsenide (InGaAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium phosphide (InP), gallium arsenide (GaAs), antimonide Indium (InSb), indium gallium antimonide (InGaSb), gallium nitride (GaN), or aluminum gallium arsenide (AlGaAs), but not limited thereto. In some embodiments, the substrate 110 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN) The substrate, gallium phosphide (GaP) substrate, gallium arsenide (GaAs) substrate, or aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto.

Referring to FIGS. 1 and 2B, the method 10 proceeds to operation 14 to alternately form a plurality of silicon dioxide (SiO ₂ ) layers 132 and a plurality of lanthanum oxide (La ₂ O ₃ ) layers 134 on the semiconductor layer 120. According to some embodiments of the present invention, the method for forming the silicon dioxide layer 132 and the lanthanum oxide layer 134 includes atomic layer deposition (ALD) or molecular beam deposition (MBD), but is not limited thereto. The silicon dioxide layer 132 and the lanthanum oxide layer 134 can be formed on the semiconductor layer 120 by any suitable deposition method. In some embodiments, as shown in FIG. 2B, a silicon dioxide layer 132a may be formed on the semiconductor layer 120, and then a lanthanum oxide layer 134a may be formed on the silicon dioxide layer 132a. After that, the silicon dioxide layer 132b and the lanthanum oxide layer 134b are alternately formed on the lanthanum oxide layer 134a. In other embodiments, a lanthanum oxide layer 134a may be formed on the semiconductor layer 120, and then a silicon dioxide layer 132a may be formed on the lanthanum oxide layer 134a. After that, the lanthanum oxide layer 134b and the silicon dioxide layer 132b are alternately formed on the silicon dioxide layer 132a. In some embodiments, the same number of lanthanum oxide layer 134 and silicon dioxide layer 132 may be formed on the semiconductor layer 120. For example, in FIG. 2B, three silicon dioxide layers 132a, 132b, 132c and three lanthanum oxide layers 134a, 134b, 134c are alternately formed on the semiconductor layer 120. It should be understood that the semiconductor structure 100 shown in FIG. 2B is only one example of the present invention. In practice, any number of silicon dioxide layers 132 and any number of lanthanum oxide layers 134 may be alternately formed on the semiconductor layer 120. For example, ten silicon dioxide layers and ten lanthanum oxide layers may be alternately formed on the semiconductor layer 120.

According to some embodiments of the present invention, the thickness of each of the silicon dioxide layers 132 (eg, 132a, 132b, 132c) is about 0.3 nm to about 2 nm, such as about 0.4, 0.5, 0.7, 1, 1.5 or 1.7 nanometers. According to some embodiments of the present invention, the thickness of each of the above lanthanum oxide layers 134 (eg, 134a, 134b, 134c) is about 0.3 nm to about 2 nm, for example, about 0.4, 0.5, 0.7, 1, 1.5 Or 1.7 nanometers. In some embodiments, the thickness of any one of the silicon dioxide layers 132 is the same as the thickness of any one of the lanthanum oxide layers 134. For example, the thickness of the silicon dioxide layer 132a thickness T ₁ and lanthanum oxide layer 134a are all T ₂ of 0.5 nm. In some embodiments, each of the silicon dioxide layers 132 has the same thickness, and each of the lanthanum oxide layers 134 has the same thickness. For example, the silicon dioxide layers 132a, 132b, and 132c have the same thickness, and the lanthanum oxide layers 134a, 134b, and 134c have the same thickness.

Referring to FIGS. 1 and 2C, the method 10 proceeds to operation 16 to rapidly anneal the silicon dioxide layer 132 and the lanthanum oxide layer 134 to form a lanthanum silicate layer 130. According to some embodiments of the present invention, the rapid annealing may be performed at about 400°C to about 800°C. For example, the rapid annealing is performed at about 450, 500, 550, 600, 650, 700, or 750°C. The rapid annealing temperature will affect the dielectric constant of the subsequently formed lanthanum silicate layer 130. An appropriate annealing temperature can be selected according to the thicknesses of the silicon dioxide layer 132 and the lanthanum oxide layer 134 and the required dielectric constant of the lanthanum silicate layer 130. According to some embodiments of the present invention, the lanthanum silicate layer includes a lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide. In certain embodiments, the lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide includes a composite oxide having the chemical formula LaSiO _x , where x is a value between 3 and 4. For example, x may be about 3.3, 3.4, 3.5, 3.6, or 3.7. In some embodiments, the thickness T ₃ of the lanthanum silicate layer 130 is about 2 nanometers to about 50 nanometers. For example, about 3, 5, 6, 8, 10, 12, 15, 20, 25, 30, 35, 40 or 45 nanometers. The lanthanum silicate layer 130 within this thickness range can maintain low leakage current and a thin equivalent oxide thickness (EOT). In some embodiments, the dielectric constant of the lanthanum silicate layer 130 is about 12 to about 22. FIG. 4 is an electron microscope photograph of the lanthanum silicate layer 130 manufactured according to the method 10 shown in FIG. 1 according to an embodiment of the present invention. It can be seen from FIG. 4 that the lanthanum silicate layer 130 formed after the rapid annealing of the silicon dioxide layer 132 and the lanthanum oxide layer 134 is a uniformly mixed amorphous lanthanum silicate layer.

Referring to FIGS. 1 and 2D, the method 10 proceeds to operation 18 to form the gate electrode layer 140 on the lanthanum silicate layer 130. According to some embodiments of the present invention, the gate electrode layer 140 includes nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), copper (Cu), aluminum (Al), tantalum oxide (TaN) or The combination, but not limited to this. As shown in FIG. 2D, the semiconductor structure 100 includes a substrate 110, a semiconductor layer 120, a lanthanum silicate layer 130 and a gate electrode layer 140. The semiconductor layer 120 is disposed on the substrate 110. The lanthanum silicate layer 130 is disposed on the semiconductor layer 120, the lanthanum silicate layer 130 is disposed on the semiconductor layer 120, and the lanthanum silicate layer includes a lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide, wherein x is a value between 3 and 4. The gate electrode layer 140 is disposed on the lanthanum silicate layer 130.

3A-3E are cross-sectional views of various steps of a manufacturing process of a semiconductor device according to some embodiments of the present invention.

First, referring to FIG. 3A, the channel layer 220 and the barrier layer 230 are sequentially formed on the substrate 210. According to some embodiments of the present invention, the channel layer 220 and the barrier layer 230 include III-V semiconductors. In some embodiments, the channel layer 220 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or other suitable III-V Family semiconductor, but not limited to this. In some embodiments, the barrier layer 230 may include aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), gallium nitride (GaN), indium gallium nitride (InGaN) , Aluminum indium gallium nitride (AlInGaN) or other suitable III-V semiconductors, but not limited thereto. In some embodiments, the material of the channel layer 220 may be different from the barrier layer 230. For example, the barrier layer 230 may be aluminum gallium nitride (AlGaN), and the channel layer 220 may be gallium nitride (GaN). In some embodiments, the substrate 210 may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN) The substrate, gallium phosphide (GaP) substrate, gallium arsenide (GaAs) substrate, or aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto. The energy gap of the channel layer 220 is smaller than the energy gap of the barrier layer 230, and the combination and thickness of the channel layer 220 and the barrier layer 230 must be capable of generating two-dimensional electron gas.

Next, referring to FIG. 3B, the source electrode 240 and the drain electrode 250 are formed on the barrier layer 230. The source electrode 240 and the drain electrode 250 include nickel (Ni), silver (Ag), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), ruthenium (Ru), palladium ( Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), tungsten silicide (WSi), molybdenum nitride (MoN), titanium aluminide (TiAl), zirconium nitride (ZrN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN), silicide, or any combination thereof, but not limited thereto. The method of forming the source electrode 240 and the drain electrode 250 may include sputtering or any conventional process.

Next, referring to FIG. 3C, mesa isolation is performed, and then a groove 234 is formed in the barrier layer 230. In some embodiments, the platform isolation includes forming a mask layer (not shown) on the barrier layer 230, and then using an etching process to remove a portion of the channel layer 220 and a portion of the barrier layer 230 on both sides of the semiconductor device 200 to form The notch 232 defines the active area of the semiconductor device 200. The above etching process includes dry etching, which may be, for example, Inductively Coupled Plasma (ICP) etching, but it is not limited thereto. In some embodiments, the groove 234 may be formed in the barrier layer 230 by a patterning process. The patterning process includes forming a mask layer (not shown) on the barrier layer 230 and forming a pattern on the mask layer, and then using an etching process to transfer the pattern to the barrier layer 230 to form the groove 234. In some embodiments, the etching process may be reactive ion etching, plasma dry etching or other anisotropic etching methods, and the etching gas may use sulfur hexafluoride, silicon tetrachloride, octafluorocyclobutane, methane , Hydrogen, argon, or other known etching gases or combinations thereof. As shown in FIG. 3C, the groove 234 is located between the source 240 and the drain 250 and does not penetrate the barrier layer 230. The purpose of the groove 234 not penetrating the barrier layer 230 is to weaken the polarization phenomenon of the barrier layer 230 and eliminate the carrier of the two-dimensional electron gas channel, so that the critical voltage is greater than 0V. Since the thinner barrier layer 230 increases the conduction band energy level, reducing the thickness of the barrier layer 230 under the gate 270 region can deplete two-dimensional electron gas.

In some embodiments, the distance D ₁ from the source 240 to the side 236 of the groove 234 is not equal to the distance D ₂ from the drain 250 to the side 237 of the groove 234, that is, the groove 234 is not located at the source The center of the pole 240 and the drain pole 250. In some embodiments, the distance D ₂ between the side 237 of the groove 234 and the drain 250 is greater than the distance D ₁ between the side 236 of the groove 234 and the source 240. In some embodiments, after the groove 234 is formed in the barrier layer 230, the upper surface of the barrier layer 230 may be surface-treated to facilitate subsequent deposition of the gate dielectric layer 260. For example, the upper surface of the barrier layer 230 may be cleaned with a solution containing NH ₄ OH.

Referring to FIG. 3D, a gate dielectric layer 260 is formed on the barrier layer 230 and covers the groove 234, and the gate dielectric layer 260 includes lanthanum silicate. In some embodiments, the gate dielectric layer 260 includes a lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide. In some embodiments, the lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide includes lanthanum silicate with the chemical formula LaSiO _x , where x is a value between 3 and 4. The method of forming the gate dielectric layer 260 containing lanthanum silicate is the same as the method of forming the lanthanum silicate layer 130 in the semiconductor structure 100 described above, so the description will not be repeated. As shown in FIG. 3D, the gate dielectric layer 260 conformally covers the barrier layer 230 and covers the sides 236, 237 and the lower surface 238 of the groove 234. In some embodiments, the thickness T ₄ of the gate dielectric layer 260 is about 2 nm to about 50 nm. For example, about 5, 9, 10, 12, 15, 20, 25, 30, 35, 40 or 45 nanometers. The smaller the thickness T _{4 of the} gate dielectric layer 260, the greater the current of the semiconductor device and the poorer the stability. On the contrary, when the thickness T _{4 of} the gate dielectric layer 260 is larger, the current of the semiconductor device is smaller and the stability is better. The gate dielectric layer 260 with an appropriate thickness can be selected according to the desired semiconductor device properties.

Referring to FIG. 3E, a gate 270 is formed on the gate dielectric layer 260, and the gate 270 fills the groove 234. As shown in FIG. 3E, the semiconductor device 200 includes a substrate 210, a channel layer 220, a barrier layer 230, a source 240, a drain 250, a gate dielectric layer 260, and a gate 270. The channel layer 220 is disposed on the substrate 210. The barrier layer 230 is disposed on the channel layer 220 and has a groove 234. The source electrode 240 and the drain electrode 250 are disposed on the barrier layer 230 and located at two ends of the groove 234 respectively. The gate dielectric layer 260 is disposed on the barrier layer 230 and covers the groove 234. The gate electrode 270 is disposed on the gate dielectric layer 260, and a part of the gate electrode 270 is filled in the groove 234, and the other part of the gate electrode 270 not filled in the groove 234 protrudes from the upper surface of the barrier layer 230. The gate electrode 270 has a first surface 262, a second surface 264 opposite to the first surface 262, and a bottom surface 266 between the first surface 262 and the second surface 264. According to some embodiments of the present invention, the width W ₁ of the bottom surface 266 of the gate electrode 270 is about 80 nm to 3 μm. For example, it may be about 100, 180, 200, 230, 250, 270, 300, 350, 400, 450, 500, 600, 700, 800, 900 nanometers, 1 micrometer, or 2 micrometers nanometer. According to some embodiments of the present invention, the distance S ₁ between the first surface 262 of the gate electrode 270 and the source electrode 240 is about 1 micrometer to 5 micrometers. For example, about 2, 3, 3.5, or 4 microns. According to some embodiments of the invention, the spacing S ₂ between the second surface 264 of the gate 270 and the drain 250 is about 2 microns to about 50 microns. For example, about 5, 6, 8, 10, 12, 15, 18, 20, 25, 30, 35, 40 or 45 microns. The distance S ₂ between the second surface 264 of the gate 270 and the drain 250 will affect the current and breakdown voltage of the semiconductor device. In some embodiments, the spacing S _{2 is} greater than the spacing S ₁ . The purpose of the distance S _{2 being} greater than the distance S ₁ is that the bias voltage of the drain 250 is large, and when the distance S ₂ between the gate 270 and the drain 250 is large, it can withstand a relatively large voltage. In some embodiments, a protective layer (not shown) may be formed on the gate dielectric layer 260 to cover part of the gate dielectric layer 260. In some embodiments, the protective layer includes Si ₃ N ₄ .

FIG. 5 is an I _D -V _GS characteristic curve of a semiconductor device according to some embodiments of the present invention. It can be seen from FIG. 5 that the gate dielectric layer containing lanthanum silicate of the present invention can reduce the hysteresis effect caused by the poor interface between the gate dielectric layer and the channel layer underneath.

FIG. 6 is a line graph of the gate voltage versus capacitance of the gate dielectric layer according to some embodiments of the present invention. It can be seen from FIG. 6 that the gate dielectric layer containing lanthanum silicate according to some embodiments of the present invention has a higher capacitance value, indicating that its dielectric coefficient is higher, and when manufacturing a semiconductor device, the device may have a higher Many carriers.

As described above, according to the embodiments of the present invention, the lanthanum silicate layer is formed by rapid annealing multiple silicon dioxide layers and multiple lanthanum oxide layers stacked on the semiconductor layer alternately. The lanthanum silicate layer of the present invention contains uniformly mixed amorphous lanthanum silicate, the thickness of which can be controlled by the number of interleaved silicon dioxide layers and lanthanum oxide layers, and has a high dielectric constant and a high energy gap . Therefore, compared with using only a single lanthanum oxide (La ₂ O ₃ ) layer with a lower energy gap, diffusion of lanthanum oxide to the semiconductor layer can be avoided. In addition, the lanthanum silicate layer of the present invention can reduce the leakage current of the semiconductor device, and can also form a good interface with the group III-V semiconductor, and has a lower interface trap density (Dit).

The present invention will be described in more detail in conjunction with various embodiments below, but the present invention is not limited to the following embodiments.

Example 1: Forming a Lanthanum silicate layer

According to the order of the silicon dioxide layer, the lanthanum oxide layer, and the silicon dioxide layer, ten silicon dioxide layers and ten lanthanum oxide layers are alternately formed on the gallium nitride (GaN) semiconductor layer, each silicon dioxide layer and each The thickness of one lanthanum oxide layer is about 0.5 nm. Thereafter, the stack of the silicon dioxide layer and the lanthanum oxide layer is rapidly annealed at about 600°C to form a lanthanum silicate layer. The lanthanum silicate layer has a dielectric coefficient of about 17.6 and an interface defect density (Dit) of less than about 5×10 ¹¹ cm ^-2 eV ^-1 .

Although the present invention has been disclosed as above in an embodiment, it is not intended to limit the present invention. Anyone who is familiar with this art can make various modifications and retouching without departing from the spirit and scope of the present invention, so the protection of the present invention The scope shall be as defined in the appended patent application scope.

100‧‧‧Semiconductor structure

110‧‧‧ substrate

120‧‧‧Semiconductor layer

130‧‧‧ Lanthanum silicate layer

140‧‧‧Gate electrode layer

T ₃ ‧‧‧ Thickness

Claims (8)

A semiconductor structure includes: a substrate; a III-V semiconductor layer disposed on the substrate; a lanthanum silicate layer disposed on the III-V semiconductor layer, the lanthanum silicate layer having an interface layer contact The III-V group semiconductor layer, and the lanthanum silicate layer includes a lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide, wherein the lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) The composite oxide is formed by rapidly stacking a plurality of silicon dioxide layers and a plurality of lanthanum oxide layers through rapid annealing; and a gate electrode layer is provided on the lanthanum silicate layer. The semiconductor structure according to claim 1, wherein the lanthanum oxide/silicon dioxide (La ₂ O ₃ /SiO ₂ ) composite oxide includes a composite oxide with the chemical formula LaSiO _x , where x is between 3 and 4 Value. The semiconductor structure of claim 1, wherein the lanthanum silicate layer has a thickness of about 2 nm to about 50 nm. The semiconductor structure of claim 1, wherein the lanthanum silicate layer has a dielectric constant of about 12 to about 22. The semiconductor structure according to claim 1, wherein the semiconductor layer comprises indium gallium arsenide (InGaAs), indium arsenide (InAs), indium aluminum arsenide (InAlAs), indium phosphide (Inp), gallium arsenide (GaAs ), indium antimonide (InSb), Indium gallium antimonide (InGaSb), gallium nitride (GaN) or aluminum gallium arsenide (AlGaAs). The semiconductor structure of claim 1, wherein each of the silicon dioxide layer and each of the lanthanum oxide layers have the same thickness. The semiconductor structure of claim 6, wherein each of the silicon dioxide layer and the lanthanum oxide layer has a thickness of about 0.3 nm to about 2 nm. The semiconductor structure of claim 1, wherein the rapid annealing temperature is about 400°C to about 800°C.

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