TWI652820B - Method of manufacturing the semiconductor structrue and semiconductor device - Google Patents

Abstract

A semiconductor structure comprising a substrate, a semiconductor layer, a bismuth ruthenate layer, and a gate electrode layer. The semiconductor layer is disposed on the substrate. The bismuth ruthenate layer is disposed on the semiconductor layer, and the bismuth ruthenate layer includes a lanthanum oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide. The gate electrode layer is disposed on the bismuth ruthenate layer.

Description

Semiconductor structure manufacturing method and semiconductor package Set

The present invention relates to a method of fabricating a semiconductor structure, and to a semiconductor device.

In semiconductor technology, III-V semiconductor compounds can be used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high electron mobility transistors (HEMT). -V semiconductor compound crystals have the potential to replace conventional germanium crystals.

Conventional germanium transistors use erbium dioxide as the gate dielectric layer. Cerium oxide has the advantages of lattice matching and excellent interface quality, which enables the germanium crystal to obtain a larger capacitance value. However, the III-V semiconductor transistor lacks a native oxide such as cerium oxide to cerium as a gate dielectric layer. Therefore, as the demand for unit capacitance of an integrated circuit device increases, it is required to develop a dielectric material having a higher dielectric constant as a gate dielectric layer of a III-V semiconductor transistor.

According to various embodiments of the present invention, there is provided a semiconductor structure including a substrate, a semiconductor layer disposed on the substrate, a bismuth ruthenate layer disposed on the semiconductor layer, and a gate electrode layer disposed on the bismuth ruthenate layer. The bismuth ruthenate layer contains a cerium oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide.

According to some embodiments of the invention, the bismuth ruthenate layer is formed by solid state reaction of cerium oxide and cerium oxide.

According to some embodiments of the present invention, the cerium oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide comprises a composite oxide of the formula LaSiO _x , wherein x is a value between 3 and 4.

According to some embodiments of the invention, the bismuth ruthenate layer has a thickness of from about 2 nanometers to about 50 nanometers.

According to some embodiments of the invention, the bismuth ruthenate layer has a dielectric constant of from about 12 to about 22.

According to some embodiments of the invention, the semiconductor layer comprises a III-V semiconductor.

According to some embodiments of the present invention, the semiconductor layer comprises InGaAs, InAs, InAlAs, InP, InGaAs, GaAs Indium (InSb), InGaSb, InGaN (GaN) or AlGaAs.

According to various embodiments of the present invention, there is provided a method of fabricating a semiconductor structure, comprising: forming a semiconductor layer on a substrate; forming a plurality of ceria layers and a plurality of hafnium oxide layers on the semiconductor layer in a staggered manner; rapidly annealing the hafnium oxide layer And a ruthenium oxide layer to form a ruthenium ruthenate layer; and form a gate The electrode layer is on the bismuth ruthenate layer.

According to some embodiments of the invention, the cerium oxide layer has a thickness of from about 0.3 nm to about 2 nm.

According to some embodiments of the invention, the ceria layer has a thickness of from about 0.3 nm to about 2 nm.

According to some embodiments of the invention, the rapid annealing step is performed at a temperature of from about 400 °C to about 800 °C.

According to some embodiments of the invention, forming the hafnium oxide layer and the hafnium oxide layer comprises atomic layer deposition or molecular beam deposition.

According to various embodiments of the present invention, a semiconductor device includes a substrate; a channel layer is disposed on the substrate; a barrier layer is disposed on the channel layer, the barrier layer has a recess, and the recess has a first sidewall and the first a second sidewall opposite to the sidewall; a source and a drain are disposed on the barrier layer, and the source is located at an end of the first sidewall of the recess, and the drain is located at an end of the second sidewall of the recess; the gate is dielectrically The layer is disposed on the barrier layer and covers the recess, wherein the gate dielectric layer comprises bismuth ruthenate; and the gate is disposed on the gate dielectric layer, and the gate is filled in the recess, wherein the gate has the first a surface, a second surface opposite the first surface, and a bottom surface between the first surface and the second surface.

According to some embodiments of the invention, the gate dielectric layer has a thickness of from about 2 nanometers to about 50 nanometers.

According to some embodiments of the invention, the bottom surface of the gate has a width of from about 80 nanometers to about 3 microns.

According to some embodiments of the invention, the first surface of the gate has a pitch between about 1 micrometer and about 5 micrometers.

According to some embodiments of the invention, the second surface of the gate has a spacing between the gate and the drain of from about 2 microns to about 50 microns.

According to some embodiments of the invention, the protective layer is further disposed on the gate dielectric layer.

According to some embodiments of the invention, the channel layer and the barrier layer comprise a III-V semiconductor.

10‧‧‧ method

12, 14, 16, 18‧‧‧ operations

100‧‧‧Semiconductor structure

110‧‧‧Substrate

120‧‧‧Semiconductor layer

130‧‧‧ 矽 镧 layer

132, 132a, 132b, 132c‧‧‧ cerium oxide layer

134, 134a, 134b, 134c‧‧‧ yttrium oxide layer

140‧‧‧gate electrode layer

200‧‧‧Semiconductor device

210‧‧‧Substrate

220‧‧‧channel layer

230‧‧‧Barrier layer

232‧‧‧ Groove

234‧‧ ‧ gap

236, 237‧‧‧ side

238‧‧‧ lower surface

240‧‧‧ source

250‧‧‧汲polar

260‧‧‧ gate dielectric layer

262‧‧‧ first surface

264‧‧‧ second surface

266‧‧‧ bottom

270‧‧‧ gate

T ₁ , T ₂ , T ₃ , T ₄ ‧‧‧ thickness

D ₁ , D ₂ ‧‧‧ distance

S ₁ , S ₂ ‧‧‧ spacing

W ₁ ‧‧‧Width

1 is a flow chart of a method of fabricating a semiconductor structure in accordance with some embodiments of the present invention.

2A-2D are cross-sectional views showing various steps of a process for fabricating a semiconductor structure in accordance with some embodiments of the present invention.

3A-3E are cross-sectional views showing various steps of a process of a semiconductor device in accordance with some embodiments of the present invention.

Figure 4 is an electron micrograph of a bismuth ruthenate layer of a semiconductor structure fabricated in accordance with certain embodiments of the present invention.

Figure 5 is a plot of I _D -V _GS characteristics of a semiconductor device in accordance with certain embodiments of the present invention.

Figure 6 is a line graph of gate voltage versus capacitance for a gate dielectric layer in accordance with certain embodiments of the present invention.

In the following, a plurality of embodiments of the present invention will be disclosed in the drawings. For the sake of clarity, many practical details will be explained in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic representation for simplicity of illustration.

In this context, spatial relative terms such as "below", "below", "above", "above", etc. are used to facilitate the description of the relative relationship between one element or feature and another element or feature, such as It is shown in the figure. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is flipped up and down by 180 degrees, the relationship between one component and another component may change from "below" or "below" to "above" and "above". In addition, the spatially relative statements used herein should be interpreted the same.

1 is a flow chart showing a method 10 of fabricating a semiconductor structure in accordance with various embodiments of the present invention. As shown in FIG. 1, method 10 includes operation 12, operation 14, operation 16, and operation 18. 2A-2D are cross-sectional views of the semiconductor structure 100 fabricated in accordance with the method 10 of FIG. 1 at various stages of the process.

Referring to FIGS. 1 and 2A, in operation 12 of method 10, semiconductor layer 120 is formed on substrate 110. According to some embodiments of the invention, the semiconductor layer 120 comprises a III-V semiconductor. In some embodiments, the semiconductor layer 120 comprises InGaAs, InAs, InAlAs, InP, InGaAs, GaAs Indium (InSb), InGaSb, InGaN (GaN) or AlGaAs (AlGaAs), but is not limited to this. In some embodiments, the substrate 110 may be a germanium substrate, a tantalum carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN). A substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, or an aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto.

Referring to FIGS. 1 and 2B, the method 10 proceeds to operation 14 to form a plurality of cerium oxide (SiO ₂ ) layers 132 and a plurality of lanthanum oxide (La ₂ O ₃ ) layers 134 on the semiconductor layer 120 in a staggered manner. According to some embodiments of the present invention, the method of forming the ceria layer 132 and the hafnium oxide layer 134 includes, but is not limited to, Atomic Layer Deposition (ALD) or Molecular Beam Deposition (MBD). The ruthenium dioxide layer 132 and the ruthenium oxide layer 134 may be formed on the semiconductor layer 120 by any suitable deposition method. In some embodiments, as shown in FIG. 2B, a layer of ruthenium dioxide 132a may be formed on the semiconductor layer 120 to form a layer of ruthenium oxide 134a on the ruthenium dioxide layer 132a. Thereafter, the ceria layer 132b and the hafnium oxide layer 134b are continuously formed alternately over the hafnium oxide layer 134a. In other embodiments, a layer of yttrium oxide 134a may be formed on the semiconductor layer 120, and a layer of ruthenium dioxide 132a may be formed on the ruthenium oxide layer 134a. Thereafter, the hafnium oxide layer 134b and the hafnium oxide layer 132b are continuously formed alternately on the hafnium oxide layer 132a. In some embodiments, the same number of yttrium oxide layers 134 and yttria layer 132 can be formed on the semiconductor layer 120. For example, in FIG. 2B, three layers of ruthenium dioxide layers 132a, 132b, and 132c and three layers of ruthenium oxide layers 134a, 134b, and 134c are alternately formed on the semiconductor layer 120. It should be understood that the semiconductor structure 100 shown in FIG. 2B is only one example of the present invention, and virtually any number of the ceria layer 132 and any number of the hafnium oxide layer 134 may be alternately formed on the semiconductor layer 120. For example, a staggered ten-layer ceria layer and ten ten-layer hafnium oxide layers may be formed on the semiconductor layer 120.

According to some embodiments of the present invention, each of the layers (e.g., 132a, 132b, 132c) of the above-described ceria layer 132 has a thickness of from about 0.3 nm to about 2 nm, for example, about 0.4, 0.5, 0.7, 1, 1.5 or 1.7 nm. According to some embodiments of the present invention, each of the above layers (e.g., 134a, 134b, 134c) of the yttria layer 134 has a thickness of from about 0.3 nm to about 2 nm, for example, about 0.4, 0.5, 0.7, 1, 1.5. Or 1.7 nm. In some embodiments, the thickness of any of the layers of the ceria layer 132 is the same as the thickness of any of the layers of the hafnium oxide layer 134. For example, the thickness of the silicon dioxide layer 132a thickness T ₁ and lanthanum oxide layer 134a are all T ₂ of 0.5 nm. In some embodiments, each of the ceria layers 132 has the same thickness, and each of the ceria layers 134 has the same thickness. For example, the thicknesses of the ceria layers 132a, 132b, and 132c are the same, and the thicknesses of the hafnium oxide layers 134a, 134b, and 134c are the same.

Referring to FIGS. 1 and 2C, method 10 proceeds to operation 16 to rapidly anneal the ruthenium dioxide layer 132 and the ruthenium oxide layer 134 to form a Lanthanum silicate layer 130. According to some embodiments of the invention, rapid annealing may be performed at about 400 °C to about 800 °C. For example, rapid annealing is performed at about 450, 500, 550, 600, 650, 700, or 750 °C. The rapid annealing temperature will affect the dielectric constant of the subsequently formed tantalum ruthenate layer 130. The appropriate annealing temperature can be selected depending on the thickness of the ruthenium oxide layer 132 and the ruthenium oxide layer 134 and the dielectric constant required for the ruthenium ruthenate layer 130. According to some embodiments of the invention, the bismuth ruthenate layer comprises a cerium oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide. In certain embodiments, the cerium oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide comprises a composite oxide of the formula LaSiO _x wherein x is a value between 3 and 4. For example, x can be about 3.3, 3.4, 3.5, 3.6, or 3.7. In certain embodiments, the thickness of the lanthanum silicate layer 130 T ₃ is from about 2 nm to about 50 nm. For example, it is about 3, 5, 6, 8, 10, 12, 15, 20, 25, 30, 35, 40 or 45 nm. The bismuth ruthenate layer 130 within this thickness range can maintain low leakage current and a thin equivalent oxide thickness (EOT). In certain embodiments, the bismuth ruthenate layer 130 has a dielectric constant of from about 12 to about 22. Figure 4 is an electron micrograph of a ruthenium ruthenate layer 130 produced in accordance with the method 10 of Figure 1 in accordance with one embodiment of the present invention. As can be seen from FIG. 4, the ruthenium ruthenate layer 130 formed after the rapid annealing of the ruthenium dioxide layer 132 and the ruthenium oxide layer 134 is a uniformly mixed amorphous bismuth ruthenate layer.

Referring to FIGS. 1 and 2D, the method 10 proceeds to operation 18 to form a gate electrode layer 140 on the bismuth ruthenate layer 130. According to some embodiments of the present invention, the gate electrode layer 140 comprises nickel (Ni), gold (Au), titanium (Ti), platinum (Pt), copper (Cu), aluminum (Al), tantalum oxide (TaN) or The combination thereof is not limited thereto. As shown in FIG. 2D, the semiconductor structure 100 includes a substrate 110, a semiconductor layer 120, a bismuth ruthenate layer 130, and a gate electrode layer 140. The semiconductor layer 120 is disposed on the substrate 110. The bismuth ruthenate layer 130 is disposed on the semiconductor layer 120, the bismuth ruthenate layer 130 is disposed on the semiconductor layer 120, and the bismuth ruthenate layer comprises a lanthanum oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide, wherein x is a value between 3 and 4. The gate electrode layer 140 is disposed on the bismuth ruthenate layer 130.

3A-3E are cross-sectional views showing various steps of a process for fabricating a semiconductor device in accordance with some embodiments of the present invention.

Referring first to FIG. 3A, the channel layer 220 and the barrier layer 230 are sequentially formed on the substrate 210. According to some embodiments of the invention, channel layer 220 and barrier layer 230 comprise a III-V semiconductor. In some embodiments, the channel layer 220 can comprise gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or other suitable III-V. Family semiconductors, but are not limited to this. In some embodiments, the barrier layer 230 may comprise aluminum gallium nitride (AlGaN), aluminum nitride (AlN), aluminum indium nitride (AlInN), gallium nitride (GaN), indium gallium nitride (InGaN). Aluminum indium gallium nitride (AlInGaN) or other suitable III-V semiconductor, but is not limited thereto. In some embodiments, the material of the channel layer 220 can be different than the barrier layer 230. For example, the barrier layer 230 may be aluminum gallium nitride (AlGaN), and the channel layer 220 may be gallium nitride (GaN). In some embodiments, the substrate 210 may be a germanium substrate, a tantalum carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum gallium nitride (AlGaN) substrate, or aluminum nitride (AlN). A substrate, a gallium phosphide (GaP) substrate, a gallium arsenide (GaAs) substrate, or an aluminum gallium arsenide (AlGaAs) substrate, but is not limited thereto. The energy gap of the channel layer 220 is smaller than the energy gap of the barrier layer 230, and the combination and thickness of the channel layer 220 and the barrier layer 230 must be capable of generating two-dimensional electron gas.

Next, referring to FIG. 3B, the source 240 and the drain 250 are formed on the barrier layer 230. The source 240 and the drain 250 include nickel (Ni), silver (Ag), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), tantalum (Ta), ruthenium (Ru), palladium. (Pd), platinum (Pt), manganese (Mn), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN), tungsten germanium (WSi), nitride Molybdenum (MoN), titanium aluminide (TiAl), zirconium nitride (ZrN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum nitride (TaSiN), titanium aluminum nitride (TiAlN), bismuth Or any combination thereof, but is not limited thereto. The method of forming source 240 and drain 250 can include sputtering or any conventional process.

Next, referring to FIG. 3C, mesa isolation is performed, and then a recess 234 is formed in the barrier layer 230. In some embodiments, the platform isolation includes forming a mask layer (not shown) on the barrier layer 230, and then removing a portion of the channel layer 220 and a portion of the barrier layer 230 on both sides of the semiconductor device 200 by an etching process to form The gap 232 defines an active region of the semiconductor device 200. The etching process includes dry etching, and may be, for example, Inductively Coupled Plasma (ICP) etching, but is not limited thereto. In some embodiments, the recess 234 can be formed in the barrier layer 230 by a patterning process. The patterning process includes forming a mask layer (not shown) on the barrier layer 230, forming a pattern on the mask layer, and transferring the pattern to the barrier layer 230 by an etching process to form the recess 234. In some embodiments, the etching process may be reactive ion etching, plasma dry etching or other anisotropic etching, and the etching gas may use sulfur hexafluoride, antimony tetrachloride, octafluorocyclobutane, methane. , hydrogen, argon or other known etching gases or combinations thereof. As shown in FIG. 3C, the recess 234 is located between the source 240 and the drain 250 and does not penetrate the barrier layer 230. The recess 234 does not penetrate the barrier layer 230 in order to weaken the polarization phenomenon of the barrier layer 230 and eliminate the carrier of the two-dimensional electron gas channel to have a threshold voltage greater than 0V. Because the thin barrier layer 230 will mention The riser has an energy level, so reducing the thickness of the barrier layer 230 under the gate 270 region can deplete the two-dimensional electron gas.

In some embodiments, the distance D _{1 of the} source 240 to the side 236 of the recess 234 is not equal to the distance D _{2 of the} drain 250 to the side 237 of the recess 234, that is, the recess 234 is not located at the source. The center of the pole 240 and the drain 250. In some embodiments, the distance D _{2 of the} side 237 of the recess 234 from the drain 250 is greater than the distance D _{1 of the} side 236 of the recess 234 from the source 240. In some embodiments, after the recess 234 is formed in the barrier layer 230, the upper surface of the barrier layer 230 may be surface treated to facilitate deposition of the subsequent gate dielectric layer 260. For example, the upper surface of the barrier layer 230 may be cleaned with a solution containing NH ₄ OH.

Referring to FIG. 3D, a gate dielectric layer 260 is formed on the barrier layer 230 and covers the recess 234, and the gate dielectric layer 260 includes tantalum ruthenate. In some embodiments, the gate dielectric layer 260 comprises a lanthanum oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide. In certain embodiments, the cerium oxide/cerium oxide (La ₂ O ₃ /SiO ₂ ) composite oxide comprises lanthanum strontium hydride having the formula LaSiO _x , wherein x is a value between 3 and 4. The method of forming the gate dielectric layer 260 comprising bismuth ruthenate is the same as the method of forming the ruthenium ruthenate layer 130 in the semiconductor structure 100, and therefore will not be described again. As shown in FIG. 3D, the gate dielectric layer 260 conformally overlies the barrier layer 230 and covers the sides 236, 237 and the lower surface 238 of the recess 234. In certain embodiments, the thickness of the dielectric gate layer ₄ is T 260 is from about 2 nm to about 50 nm. For example, it is about 5, 9, 10, 12, 15, 20, 25, 30, 35, 40 or 45 nm. The smaller the thickness T _{4 of the} gate dielectric layer 260 is, the larger the current of the semiconductor device is and the stability is poor. On the contrary, when the thickness T _{4 of} the gate dielectric layer 260 is larger, the current of the semiconductor device is smaller and the stability is better. A suitable thickness of the gate dielectric layer 260 can be selected depending on the desired semiconductor device properties.

Referring to FIG. 3E, a gate 270 is formed on the gate dielectric layer 260, and the gate 270 fills the recess 234. As shown in FIG. 3E, the semiconductor device 200 includes a substrate 210, a channel layer 220, a barrier layer 230, a source 240, a drain 250, a gate dielectric layer 260, and a gate 270. The channel layer 220 is disposed on the substrate 210. The barrier layer 230 is disposed on the channel layer 220 and has a recess 234. The source 240 and the drain 250 are disposed on the barrier layer 230 at opposite ends of the recess 234. The gate dielectric layer 260 is disposed on the barrier layer 230 and covers the recess 234. The gate 270 is disposed on the gate dielectric layer 260, and a portion of the gate 270 is filled in the recess 234, and another portion of the gate 270 not filled in the recess 234 protrudes from the upper surface of the barrier layer 230. Gate 270 has a first surface 262, a second surface 264 opposite first surface 262, and a bottom surface 266 between first surface 262 and second surface 264. According to some embodiments of the present invention, a gate width W 266 of the bottom surface 270 of about 80 nm to ₁ m 3. For example, it can be about 100, 180, 200, 230, 250, 270, 300, 350, 400, 450, 500, 600, 700, 800, 900 nanometers, 1 micron or 2 micron nanometers. According to some embodiments of the invention, the spacing S ₁ between the first surface 262 of the gate 270 and the source 240 is between about 1 micron and 5 microns. For example, it is about 2, 3, 3.5 or 4 microns. According to some embodiments of the invention, the spacing S ₂ between the second surface 264 of the gate 270 and the drain 250 is from about 2 microns to about 50 microns. For example, it is about 5, 6, 8, 10, 12, 15, 18, 20, 25, 30, 35, 40 or 45 microns. The spacing S ₂ between the second surface 264 of the gate 270 and the drain 250 will affect the current and breakdown voltage of the semiconductor device. In some embodiments, the spacing S _{2 is} greater than the spacing S ₁ . The purpose of the spacing S _{2 being} greater than the spacing S ₁ is that the bias voltage of the drain 250 is large, and when the gate 270 and the drain 250 are larger than S ₂ , a larger voltage can be withstood. In some embodiments, a protective layer (not shown) may also be formed over the gate dielectric layer 260 to cover a portion of the gate dielectric layer 260. In certain embodiments, the protective layer comprises Si ₃ N ₄ .

Figure 5 is a plot of I _D -V _GS characteristics of a semiconductor device in accordance with certain embodiments of the present invention. As can be seen from FIG. 5, the gate dielectric layer comprising bismuth ruthenate of the present invention can reduce the hysteresis caused by poor interface between the gate dielectric layer and the underlying channel layer.

Figure 6 is a line graph of gate voltage versus capacitance for a gate dielectric layer in accordance with certain embodiments of the present invention. As can be seen from FIG. 6, the gate dielectric layer comprising bismuth ruthenate citrate according to some embodiments of the present invention has a higher capacitance value, indicating a higher dielectric constant, and the device may have a higher ratio when fabricating a semiconductor device. More carriers.

As described above, according to an embodiment of the present invention, a bismuth ruthenate layer is formed by rapidly annealing a plurality of ruthenium dioxide layers and a plurality of ruthenium oxide layers stacked on a semiconductor layer. The bismuth ruthenate layer of the present invention comprises uniformly mixed amorphous bismuth ruthenate, the thickness of which can be controlled by the number of staggered stacked ruthenium and ruthenium oxide layers, and has a high dielectric constant and a high energy gap. . Therefore, diffusion of yttrium oxide to the semiconductor layer can be avoided as compared with the use of only a single yttria (La ₂ O ₃ ) layer having a lower energy gap. In addition, the bismuth ruthenate layer of the present invention can reduce the leakage current of the semiconductor device, and can form a good interface with the III-V semiconductor, and has a low interface defect density (Dit).

The invention will be described in more detail below with reference to various embodiments, but the invention is not limited to the following examples.

Example 1: Formation of a Lanthanum silicate layer

10 layers of ruthenium dioxide layer and 10 layers of ruthenium oxide layer are sequentially formed on the gallium nitride (GaN) semiconductor layer in the order of the ruthenium dioxide layer, the ruthenium oxide layer and the ruthenium dioxide layer, each layer of ruthenium dioxide layer and each layer The thickness of a layer of ruthenium oxide layer is about 0.5 nm. Thereafter, the above-mentioned laminate of the cerium oxide layer and the cerium oxide layer is rapidly annealed at about 600 ° C to form a bismuth ruthenate layer. The above ruthenium ruthenate layer has a dielectric constant of about 17.6 and an interface defect density (Dit) of less than about 5 x 10 ¹¹ cm ^-2 eV ^-1 .

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

Claims (12)

A method of fabricating a semiconductor structure, comprising: forming a semiconductor layer on a substrate; forming a plurality of ceria layers and a plurality of ruthenium oxide layers on the semiconductor layer in a staggered manner; rapidly annealing the ruthenium dioxide layers and the The ruthenium oxide layer is formed to form a ruthenium ruthenate layer; and a gate electrode layer is formed on the ruthenium ruthenate layer. The method of fabricating a semiconductor structure according to claim 1, wherein each of the ruthenium oxide layers has a thickness of from about 0.3 nm to about 2 nm. The method of fabricating a semiconductor structure according to claim 1, wherein each of the ceria layers has a thickness of from about 0.3 nm to about 2 nm. The method of fabricating a semiconductor structure according to claim 1, wherein the rapid annealing step is performed at about 400 ° C to about 800 ° C. The method of fabricating a semiconductor structure according to claim 1, wherein the ruthenium oxide layer and the ruthenium dioxide layer are formed by atomic layer deposition or molecular beam deposition. A semiconductor device comprising: a substrate; a channel layer is disposed on the substrate; a barrier layer is disposed on the channel layer, and the barrier layer has a recess, wherein the recess has a first sidewall and a surface opposite to the first sidewall a second sidewall; a source and a drain disposed on the barrier layer, wherein the source is located at an end of the first sidewall adjacent to the recess, the drain being located adjacent to the second sidewall of the recess a gate dielectric layer disposed on the barrier layer and covering the recess, wherein the gate dielectric layer comprises bismuth ruthenate; and a gate is disposed on the gate dielectric layer And the gate is filled in the recess, wherein the gate has a first surface, a second surface opposite the first surface, and a bottom surface between the first surface and the second surface. The semiconductor device of claim 6, wherein the gate dielectric layer has a thickness of from about 2 nm to about 50 nm. The semiconductor device of claim 6, wherein the bottom surface of the gate has a width of from about 80 nm to about 3 microns. The semiconductor device of claim 6, wherein the first surface of the gate and the source have a pitch of between about 1 micron and about 5 microns. The semiconductor device of claim 6, wherein the The second surface of the gate and the drain have a spacing of between about 2 microns and about 50 microns. The semiconductor device of claim 6, further comprising a protective layer disposed on the gate dielectric layer. The semiconductor device of claim 6, wherein the channel layer and the barrier layer comprise a III-V semiconductor.