TWI799127B - High electron mobility semiconductor structure and high electron mobility semiconductor device - Google Patents

Abstract

A high electron mobility semiconductor structure includes a substrate, a channel layer, a barrier layer, a conductive layer, a first dielectric layer, and a second dielectric layer. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The conductive layer is disposed over the barrier layer. The first dielectric layer is disposed between the barrier layer and the conductive layer, and has a first energy gap. The second dielectric layer is disposed between the first dielectric layer and the conductive layer, and has a second energy gap. The second energy gap is larger than the first energy gap.

Description

High electron mobility semiconductor structure and high electron mobility semiconductor device

The present disclosure relates to a high electron mobility semiconductor device, especially a high electron mobility semiconductor device having a high electron mobility semiconductor structure with a multi-layer gate dielectric layer.

Semiconductor integrated circuit (IC) technology has developed rapidly, and semiconductor devices have been widely used in various electronic products, such as personal computers, mobile phones, digital cameras and other electronic devices. In semiconductor devices, field effect transistors play an important role. With the development of semiconductor integrated circuit technology, various types of field effect transistors have been produced one after another. A high electron mobility transistor (HEMT) is a type of field effect transistor. A HEMT consists of two semiconductor materials with different energy gaps, forming a heterojunction (hetero junction), and can act as a conductive channel. Due to the advantages of low resistance, high breakdown voltage, and fast switching frequency, HEMTs are widely used in the field of high-power electronic components.

In recent years, high electron mobility transistor (HEMT) devices based on three-five (III-V) compound semiconductors have high breakdown voltage, large energy gap and excellent carrier mobility. At the same time, the two-dimensional electron gas generated by the polarization phenomenon can exhibit excellent low-impedance conduction characteristics, making the III-V compound semiconductor materials widely used in high-frequency and power components. The Metal-Insulator-Semiconductor High Electron Mobility Transistor (Metal-Insulator-Semiconductor HEMT; MIS-HEMT) is one of the HEMT devices. The MIS-HEMT device has a gate dielectric layer at the interface between the metal and the semiconductor, which can enhance device performance, such as high breakdown voltage, low gate leakage current, low device impedance, and wide gate operating range. However, although existing technologies for fabricating MIS-HEMTs are generally adequate for their intended purposes, they are not satisfactory in every respect.

The present disclosure provides a high electron mobility semiconductor structure. The high electron mobility semiconductor structure includes a substrate, a channel layer, a barrier layer, a conductive layer, a first dielectric layer, and a second dielectric layer. The channel layer is disposed over the substrate. The barrier layer is disposed above the channel layer. The conductive layer is disposed over the barrier layer. The first dielectric layer is disposed between the barrier layer and the conductive layer, and has a first energy gap. The second dielectric layer is disposed between the first dielectric layer and the conductive layer, and has a second energy gap. The second energy gap is larger than the first energy gap.

The present disclosure provides a high electron mobility semiconductor device. The high electron mobility semiconductor device includes a substrate, a III-V semiconductor layer, a barrier layer, a first gate dielectric layer, a second gate dielectric layer, a gate electrode, and a source electrode and a drain electrode. The III-V semiconductor layer is disposed above the substrate. The barrier layer is disposed on the III-V semiconductor layer. The first gate dielectric layer is disposed above the barrier layer and has a first energy gap. The second gate dielectric layer is disposed above the first gate dielectric layer and has a second energy gap. The second energy gap is larger than the first energy gap. The gate electrode is disposed above the second gate dielectric layer. The source electrode and the drain electrode are disposed on two sides of the gate electrode and extend through the barrier layer to be electrically connected to the III-V semiconductor layer.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of components and their arrangements for simplicity of illustration. Of course, these specific examples are not intended to be limiting. For example, if the disclosure describes that a first feature is formed on or above a second feature, it means that it may include embodiments in which the above-mentioned first feature is in direct contact with the above-mentioned second feature, and may also include Embodiments in which an additional feature is formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the same reference symbols and/or symbols may be reused in different examples in the following disclosure. These repetitions are for simplicity and clarity and are not intended to limit a particular relationship between the different embodiments and/or structures discussed.

For purposes of elaboration of this disclosure, unless specifically denied, words in the singular include the plural and vice versa. And the word "comprising" means "including without limitation". In addition, similar (approximation) terms such as "about", "almost", "equally", "approximately", etc., can be used in the embodiments of the present disclosure, and their meanings are such as "at, close to or close to" or " Within 3 to 5%" or "within acceptable manufacturing tolerances" or any logical combination.

Also, its terminology related to space. Words such as "below," "beneath," "lower," "above," "higher," and similar terms are used for convenience in describing one element or feature in relation to another element or feature in the drawings. The relationship between. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the illustrations is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. In this way, the model word "below" will cover the two ways of reading upwards and downwards. In addition, the device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related words used herein may also be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and does not limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. In addition, to the extent that terms "comprises", "comprises", "has", "has", "includes" or variations thereof are used in the detailed description and/or claims, these terms are intended to be similar Inclusive by way of "include".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms such as those defined in commonly used dictionaries should be construed to have the same meaning as they have in the context of the relevant field, and will not be construed as idealistic or overly formal, unless expressly so stated herein definition.

The present disclosure relates generally to high electron mobility semiconductor structures and devices, in particular high electron mobility transistors with metal-insulator-semiconductor structures (MIS-HEMTs). In a typical MIS-HEMT, there is an energy state between the dielectric layer used as the gate dielectric layer and the barrier layer (or capping layer if present). When the MIS-HEMT is in an off-state, the gate of the MIS-HEMT is applied with a negative voltage (lower than the threshold voltage (V _th )), and the drain is applied with a positive voltage. In this case, although the MIS-HEMT will be turned off, the electric field caused by the negative voltage applied to the gate and the voltage difference between the gate and the drain (V _GD ) may cause electrons to cross the gate from the gate The energy gap of the dielectric layer is trapped by the energy level between the gate dielectric layer and the barrier layer (or capping layer (if present)), and the trapped electrons will affect the electrical potential of the MIS-HEMT. sexual manipulation, resulting in a decrease in the performance of the MIS-HEMT. Therefore, MIS-HEMT needs to be improved to prevent electrons from the gate from crossing the energy gap of the gate dielectric layer when the MIS-HEMT is in the off state, and being trapped by the gate dielectric layer and the barrier layer (or capping layer (if present) )) between the energy levels captured.

Embodiments of the present invention provide several advantages over the prior art, and it should be understood that other embodiments may provide different advantages, not all advantages need to be discussed here, and all embodiments have no specific advantages. For example, embodiments discussed herein include high electron mobility semiconductor structures and devices having multiple dielectric layers for the gate dielectric layer to prevent electrons from the gate across the energy gap of the gate dielectric layer , and is trapped by the energy level between the gate dielectric and the barrier (or cap, if present).

FIG. 1A is a cross-sectional view of a high electron mobility semiconductor device 100 according to an embodiment of the disclosure. FIG. 1B is an energy band diagram along the line segment AA' of the high electron mobility semiconductor device 100 in FIG. 1A according to an embodiment of the present disclosure, wherein the high electron mobility semiconductor device 100 is in a steady state (gate electrode 120 The Fermi energy level (fermi level) E _fm of the channel layer 106 and the Fermi energy level E _fs of the barrier layer 108 are on the same horizontal line). As shown in FIG. 1A , a high electron mobility semiconductor device 100 includes a substrate 102 and a buffer layer 104 disposed above the substrate 102 . In one embodiment, the substrate 102 may be a silicon (Si) substrate. In some embodiments, the substrate 102 may include another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide ; Alloy semiconductors, such as silicon germanium (SiGe), silicon carbon phosphide (SiPC), or three five (III-V) semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs ), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), indium gallium arsenide (InGaAs), or combinations thereof.

The buffer layer 104 can avoid or reduce the defects caused by the difference in lattice constant and the difference in thermal expansion coefficient between the substrate 102 below it and the material layer above it (such as the subsequent channel layer 106), thereby improving the quality of the subsequently deposited material layer. quality. The buffer layer 104 may have a single-layer or multi-layer structure. The buffer layer 104 may include group III (III) nitrides, metal nitrides, metal carbides, metal nitride carbides, pure metals, metal alloys, silicon-containing materials, or the like. The buffer layer 104 may be formed by an epitaxy process, and the epitaxy process may include chemical vapor deposition (chemical vapor deposition; CVD), physical vapor deposition (physical vapor deposition; PVD), metal organic chemical vapor deposition (metal organic chemical vapor deposition) deposition; MOCVD), metal-organic vapor phase epitaxy (metal-organic vapor phase epitaxy; MOVPE), plasma-enhanced chemical vapor deposition (plasma-enhanced chemical vapor deposition; PECVD), remote plasma chemical vapor deposition ( remote plasma chemical vapor deposition (RPCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), chloride Vapor phase epitaxy (Chloride vapor phase epitaxy; Cl-VPE), other suitable processes or a combination thereof. In the embodiment of the present disclosure, the buffer layer 104 includes Group III nitride semiconductor, such as gallium nitride (GaN), but the present disclosure is not limited thereto. For example, in some embodiments, the material used to form the buffer layer 104 may include indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), Aluminum Indium Nitride (AlInN), Aluminum Indium Gallium Nitride (AlInGaN), other suitable Group III nitride semiconductors, or combinations thereof. In some embodiments, the buffer layer 104 may include a multi-layer structure in which a plurality of aluminum nitride (AlN) layers and a plurality of silicon-doped gallium nitride (GaN) layers are stacked in a staggered manner. In some embodiments, the buffer layer 104 can be doped with P-type or N-type dopant, or not doped, so that the buffer layer 104 is P-type, N-type or undoped.

The channel layer 106 is formed and disposed over the buffer layer 104 and the substrate 102 . The channel layer 106 may include a III-V semiconductor material, and thus the channel layer 106 may also be referred to as a semiconductor layer or a III-V semiconductor layer. In some embodiments, the semiconductor layer 106 may be an intrinsic III-V semiconductor. In the disclosed embodiment, the semiconductor layer 106 may be a group III nitride semiconductor, such as gallium nitride (GaN). The semiconductor layer 106 may be formed by performing an epitaxial process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD), metal organic chemical vapor epitaxy epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), other suitable processes or combinations thereof. In some embodiments, the channel layer 106 has a thickness in the range of 100 nm to 500 nm.

A barrier layer 108 is formed and disposed over the channel layer 106 . In some embodiments, the barrier layer 108 may have a binary or multi-component structure. In some embodiments, the barrier layer 108 may include Group III and V semiconductor materials, such as Group III nitride semiconductors. In the embodiment of the present disclosure, the barrier layer 108 may include aluminum gallium nitride (AlGaN), but the present disclosure is not limited thereto. For example, in other embodiments, the barrier layer 108 may include aluminum nitride, aluminum indium nitride (AlInN), aluminum gallium indium nitride (AlGaInN), other suitable Group III nitride semiconductors, or combinations thereof. In some embodiments, the barrier layer 108 may be formed by performing an epitaxial process, which may include chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD) , metal organic chemical vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), other suitable processes or combinations thereof. Furthermore, barrier layer 108 may be doped or undoped. In some embodiments, barrier layer 108 has a thickness in the range of 15 nm to 50 nm.

In some embodiments, the barrier layer 108 and the channel layer 106 are formed using suitable materials to generate two dimensional electron gas (TDE) with high electron mobility near the interface between the channel layer 106 and the barrier layer 108. gas; 2DEG). Specifically, as shown in FIG. 1B, the barrier layer 108 and the channel layer 106 are formed using appropriate materials such that the energy gap E _g2 of the barrier layer 108 (the conduction band E _c and the valence band E _v of the barrier layer 108 energy difference) is greater than the energy gap E _g1 of the channel layer 106 (the energy difference between the conduction band E _c and the valence band E _v of the channel layer 106). In this case, the difference in energy gap between the channel layer 106 and the barrier layer 108 leads to the formation of a heterojunction between the channel layer 104 and the barrier layer 106, so that in the region of the channel layer 104 close to the barrier layer 106 A two-dimensional electron gas 110 is formed, as shown in FIG. 1A. In some embodiments, channel layer 106 is formed of gallium nitride (GaN) and barrier layer 108 is formed of aluminum gallium nitride (AlGaN). In some embodiments, channel layer 106 has an energy gap of about 3.4 eV, and barrier layer 108 has an energy gap of about 4 eV.

Referring again to FIG. 1A , a capping layer 112 is formed and disposed over the barrier layer 108 . In some embodiments, the capping layer 112 can prevent or reduce oxidation of the barrier layer 108 . In some embodiments, the material of the capping layer 112 includes Group III and V semiconductor materials, such as Group III nitride semiconductors. For example, the material of the capping layer 112 may include gallium nitride (GaN), indium nitride (InN), indium gallium nitride (InGaN), other suitable Group III nitride semiconductors, or combinations thereof. In some embodiments, the capping layer 112 can be formed by performing an epitaxial process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), metal organic chemical vapor deposition (MOCVD), metal organic chemical gas Phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), other suitable processes or combinations thereof. Cap layer 112 is optional. In some embodiments, the high electron mobility semiconductor device 100 does not have the capping layer 112 .

Referring again to FIG. 1A, gate structure 114 is formed and disposed over channel layer 106, and barrier layer 108 (and capping layer 112, if present). The gate structure 114 includes a dielectric layer 116 , a dielectric layer 118 , and a gate electrode 120 .

Dielectric layer 116 is formed and disposed over barrier layer 108 (and cap layer 112 if present), and between barrier layer 108 and gate electrode 120 . Dielectric layer 118 is formed and disposed over dielectric layer 116 and between dielectric layer 116 and gate electrode 120 . In some embodiments, dielectric layers 116 and 118 may be referred to as gate dielectric layers. In some embodiments, dielectric layers 116 and 118 may include dielectric materials such as silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), magnesium oxide (MgO), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), oxide Hafnium-aluminum oxide (HfO ₂ -Al ₂ O ₃ ), titanium oxide (TiO ₂ ), cerium oxide (CeO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), lanthanum trioxide (La ₂ O ₃ ), Yttrium trioxide (Y ₂ O ₃ ), other suitable dielectric materials, or combinations thereof. Dielectric layers 116 and 118 may be formed by a deposition process, such as atomic layer deposition (ALD).

As mentioned above, when a typical MIS-HEMT is in the off state, electrons cross the energy gap of the gate dielectric layer from the gate and are trapped between the gate dielectric layer and the barrier layer (or capping layer (if present)). The energy levels in between are captured, resulting in a decrease in the performance of the MIS-HEMT. In the presently disclosed embodiment, in order to prevent electrons from the gate across the gate dielectric layer, dielectric layers 116 and 118 with different energy gaps are used, and the energy gap E _g3 of the dielectric layer 116 (of the dielectric layer 116 The energy difference between the conduction band _Ec and the valence band _Ev ) is greater than the energy gap _Eg2 of the barrier layer 108, and the energy gap _Eg4 of the dielectric layer 118 (the energy difference between the conduction band _Ec and the valence band _Ev of the dielectric layer 118 energy difference) is greater than the energy gap E _g3 of the dielectric layer 116 , as shown in FIG. 1B . As a result, electrons at the gate electrode 120 encounter a higher energy barrier and are less likely to cross the dielectric layers 116 and 118 . For example, the barrier layer 108 comprising aluminum gallium nitride (AlGaN) has an energy gap of about 4 eV, the dielectric layer 116 may comprise a dielectric material having an energy gap E _g3 greater than 4 eV, and the dielectric layer 116 may comprise A dielectric material having an energy gap E _g4 greater than E _g3 .

In addition, in order to fabricate MIS-HEMT with high transconductance (g _m ), it is possible to fabricate MIS-HEMT with high transconductance (g _m ) with high cut-off frequency (f _T ) and high maximum oscillation frequency (f _max ) For RF amplifier devices, the dielectric layer 116 may include a high-k (high dielectric constant) dielectric material, for example, the dielectric layer 116 may include a dielectric material with a dielectric constant greater than 15. In some embodiments, the dielectric constant of the dielectric layer 118 is smaller than that of the dielectric layer 116 to improve device performance. In some embodiments, the thickness of the dielectric layer 118 is smaller than that of the dielectric layer 116 to improve device performance. Thus, in some embodiments, dielectric layer 116 may comprise hafnium oxide (HfO ₂ ) (dielectric constant approximately 25, energy gap approximately 5.8 eV), and dielectric layer 118 may comprise aluminum oxide (Al ₂ O ₃ ) (dielectric constant is about 9, energy gap is about 8eV), and the thickness of the dielectric layer 118 is smaller than the thickness of the dielectric layer 116.

Gate electrode 120 is formed and disposed over barrier layer 108 , cap layer 112 , dielectric layer 116 and dielectric layer 118 . In some embodiments, the gate electrode 120 is formed of one or more conductive materials, and thus the gate electrode 120 may also be referred to as a conductive layer. Conductive materials may include metals or metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), titanium (Ti), tantalum (Ta), silver (Ag), Manganese (Mn), Zirconium (Zr), Palladium (Pd), Nickel (Ni), Gold (Au), Aluminum (Al), or combinations thereof. In some embodiments, the gate electrode 120 includes nickel (Ni) and gold (Au). In some embodiments, the forming method of the gate electrode 120 includes one or more of deposition process, lithography process and etching process. The deposition process may include atomic layer deposition (ALD), CVD, and/or other suitable processes. The lithography process may include photoresist coating (eg, spin-on coating), soft bake, mask alignment, exposure, post-exposure bake, developing photoresist, rinsing ), dry (e.g. hard bake). In other embodiments, the lithography process can be performed or replaced by other suitable methods, such as maskless photolithography, electron-beam writing, and ion-beam writing. ) bundle writes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

Referring again to FIG. 1A , an interlayer dielectric (ILD) layer 122 is formed and disposed above the gate structure 114 . The ILD layer 122 includes dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, oxides formed from tetraethylorthosilicate (TEOS), phosphosilicate glass (PSG), borophosphorous Borophosphosilicate glass (BPSG), boron doped silicon glass (BSG), low-k dielectric material, other suitable dielectric materials or combinations thereof. Exemplary low-k dielectric materials include fluoride-doped silicate glass (FSG), carbon-doped silicon oxide, BlackDiamond® (Applied Materials, Santa Clara, CA), dry solidified Xerogel, Aerogel, amorphous fluorocarbons, parylene, benzocyclobutene (BCB), SiLK® (Dow Corporation, Midland, Michigan chemical companies), polyimide (polyimide), other low-k dielectric materials, or combinations thereof. In some embodiments, ILD layer 122 is a dielectric layer comprising a low-k dielectric material (commonly referred to as a low-k dielectric layer). In some embodiments, low-k dielectric materials generally refer to materials having a dielectric constant less than three. In some embodiments, the ILD layer 122 is a multilayer structure that may include multiple dielectric materials. The ILD layer 122 can be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma chemical vapor deposition (high density plasma CVD; HDPCVD) , metal-organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (low-pressure CVD; LPCVD), atomic layer Chemical vapor deposition (Atomic Layer Chemical Vapor Deposition; ALCVD), atmospheric pressure chemical vapor deposition (Atmospheric Pressure CVD; APCVD), electroplating, other suitable methods or combinations thereof. In some embodiments, the ILD layer 122 is formed by flowable chemical vapor deposition (flowable CVD; FCVD), which involves depositing a flowable material (eg, a liquid compound) over the substrate 102 and applying it by a suitable technique (eg, thermal Annealing and/or UV radiation treatment) converts the flowable material into a solid material.

Referring again to FIG. 1A , a source electrode 124 and a drain electrode 126 are formed on both sides of the gate structure 114 (dielectric layer 116 , dielectric layer 118 , and gate electrode 120 ). In some embodiments, source electrode 124 and drain electrode 126 are formed through ILD layer 122 , dielectric layer 116 and dielectric layer 118 . In some embodiments, the source electrode 124 and the drain electrode 126 contact the cap layer 112 . In other embodiments, the source electrode 124 and the drain electrode 126 further pass through the cap layer 112 and the barrier layer 108 and contact the channel layer 106 . Similar to the gate electrode 120 , the source electrode 124 and the drain electrode 126 may include one or more conductive materials, and thus the source electrode 124 and the drain electrode 126 may also be referred to as conductive layers. The conductive material forming source electrode 124 and drain electrode 126 may be a conductive material as described above, and may be the same as or different from gate electrode 120 . Similarly, the forming method of the source electrode 124 and the drain electrode 126 may include the deposition process, the lithography process and the etching process for forming the gate electrode 120 as described above.

In some embodiments, the number of dielectric layers in the gate structure can be further increased. FIG. 2A is a cross-sectional view of a high electron mobility semiconductor device 200 according to an embodiment of the disclosure, wherein the gate structure has three dielectric layers. FIG. 2B shows an energy band diagram along line AA' of the high electron mobility semiconductor device 200 in FIG. 2B according to an embodiment of the present disclosure, wherein the high electron mobility semiconductor device 200 is in a steady state (gate electrode 120 The Fermi energy level E _fm of the channel layer 106 and the Fermi energy level E _fs of the barrier layer 108 are on the same horizontal line). The HEM semiconductor device 200 is similar to the HEM semiconductor device 100 of FIG. 1A , except that the gate structure 114 of the HEM semiconductor device 200 further includes a dielectric layer 202 .

As shown in FIG. 2B , a dielectric layer 202 is formed and disposed over the dielectric layer 118 and between the dielectric layer 118 and the gate electrode 120 . In some embodiments, dielectric layer 202 may be referred to as a gate dielectric layer. The dielectric layer 202 may include dielectric materials such as silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), magnesium oxide (MgO), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide-alumina oxide (HfO ₂ - Al ₂ O ₃ ), Titanium Oxide (TiO ₂ ), Cerium Oxide (CeO ₂ ), Tantalum Pentoxide (Ta ₂ O ₅ ), Dilanthanum Trioxide (La ₂ O ₃ ), Diyttrium Trioxide (Y ₂ O ₃ ), other suitable dielectric materials or combinations thereof. The dielectric layer 202 can be formed by a deposition process, such as atomic layer deposition (ALD).

As mentioned above, in order to prevent electrons from the gate from crossing the gate dielectric layer, the dielectric layer 202 may have a larger energy gap. Specifically, in the high electron mobility semiconductor device 200, the energy gap E _g3 of the dielectric layer 116 is greater than the energy gap E _g2 of the barrier layer 108, and the energy gap E _g4 of the dielectric layer 118 is greater than the energy gap E g4 of the dielectric layer 116. Gap E _g3 , and the energy gap E _g5 of the dielectric layer 202 (the energy difference between the conduction band E _c and the valence band E _v of the dielectric layer 202) is greater than the energy gap E _g4 of the dielectric layer 118, as shown in Figure 2B . Similarly, in some embodiments, the dielectric constant of dielectric layer 202 is less than that of dielectric layer 118, and the dielectric constant of dielectric layer 118 is less than that of dielectric layer 116 to improve device performance. . In some embodiments, the thickness of the dielectric layer 202 is smaller than the thickness of the dielectric layer 118 , and the thickness of the dielectric layer 118 is smaller than the thickness of the dielectric layer 116 to improve device performance. Thus, in some embodiments, dielectric layer 116 may include hafnium oxide (HfO ₂ ) (dielectric constant about 25, energy gap about 5.8 eV) and dielectric layer 118 may include aluminum oxide (Al ₂ O ₃ ). (dielectric constant is about 9, energy gap is about 8eV), dielectric layer 202 may include silicon oxide (SiO ₂ ) (dielectric constant is about 3.9, energy gap is about 9eV), and the thickness of dielectric layer 118 is less than The thickness of the dielectric layer 116 .

Embodiments of the present disclosure relate to high electron mobility semiconductor structures and devices, and more particularly to high electron mobility transistors (MIS-HEMT) having a metal-insulator-semiconductor structure, wherein the gate structure has multiple dielectric layers ( gate dielectric layer). Additionally, the present embodiments provide one or more of the following advantages. The energy gaps of multiple dielectric layers (gate dielectric layers) of the gate structure have a gradient, and the closer to the gate electrode, the larger the energy gap of the dielectric layer, which can effectively prevent electrons from crossing the gate dielectric layer from the gate. and is trapped by the energy level between the gate dielectric and the barrier layer (or capping layer, if present). In addition, the dielectric constants of the plurality of dielectric layers (gate dielectric layers) also have gradients, and the dielectric constants of the dielectric layers closer to the barrier layer are larger, so as to improve device performance.

The foregoing text summarizes features of many embodiments so that those skilled in the art may better understand the present disclosure in various aspects. Those skilled in the art should be able to understand, and can easily design or modify other processes and structures based on this disclosure, so as to achieve the same purpose and/or achieve the same as the embodiments introduced here advantages. Those skilled in the art should also appreciate that such equivalent structures do not depart from the spirit and scope of the disclosed invention. Various changes, substitutions, or modifications may be made to the present disclosure without departing from the inventive spirit and scope of the present disclosure.

100: high electron mobility semiconductor device 102: substrate 104: buffer layer 106: channel layer 108: barrier layer 110: two-dimensional electron gas 112: capping layer 114: gate structure 116: dielectric layer 118: dielectric layer 120 : gate electrode 122: interlayer dielectric layer 124: source electrode 126: drain electrode A-A': line segment E _c : conduction band E _v : valence band E _fm : Fermi energy level E _fs : Fermi energy level E _g1 : energy gap E _g2 : energy gap E _g3 : energy gap E _g4 : energy gap 200: high electron mobility semiconductor device 202: dielectric layer E _g5 : energy gap

In order to make the description of the present disclosure cover the above-mentioned examples and other advantages and features, the principle of the above-mentioned brief description will be described in more detail through specific examples in the drawings. It should be understood that the drawings shown here are only examples of the present disclosure, and should not limit the scope of the present disclosure. The principles of the present disclosure are described and explained with additional features and details through the accompanying drawings, in which: FIG. 1A shows a cross-sectional view of a high electron mobility semiconductor device in which a gate structure has two dielectric layers, according to an embodiment of the present disclosure. FIG. 1B shows an energy band diagram along the line segment A-A' of the high electron mobility semiconductor device of FIG. 1A according to an embodiment of the present disclosure. FIG. 2A shows a cross-sectional view of a high electron mobility semiconductor device in which the gate structure has three dielectric layers, according to an embodiment of the present disclosure. FIG. 2B shows an energy band diagram along line A-A' of the high electron mobility semiconductor device of FIG. 2B according to an embodiment of the present disclosure.

none.

100: High Electron Mobility Semiconductor Devices

102: Substrate

104: buffer layer

106: Channel layer

108: Barrier layer

110: Two-dimensional electron gas

112: cover layer

114:Gate structure

116: dielectric layer

118: dielectric layer

120: gate electrode

122: interlayer dielectric layer

124: source electrode

126: Drain electrode

A-A': line segment

Claims (10)

A high electron mobility semiconductor structure, comprising: a substrate; a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; a conductive layer disposed above the barrier layer; a first a dielectric layer, arranged between the barrier layer and the conductive layer, and has a first energy gap; a second dielectric layer, arranged between the first dielectric layer and the conductive layer, and has a second energy gap, wherein said second energy gap is greater than said first energy gap; and a third dielectric layer, between said second dielectric layer and said conductive layer, and has a third energy gap, wherein said The third energy gap is larger than the above-mentioned second energy gap. The high electron mobility semiconductor structure as claimed in claim 1, wherein the first dielectric layer comprises a high-k dielectric material. The high electron mobility semiconductor structure according to claim 1, wherein a dielectric constant of the first dielectric layer is greater than 15. The high electron mobility semiconductor structure according to claim 1, wherein a dielectric constant of the third dielectric layer is smaller than a dielectric constant of the second dielectric layer, and a dielectric constant of the second dielectric layer is smaller than A dielectric constant of the first dielectric layer. Such as the high electron mobility semiconductor structure of claim 3, wherein the above A thickness of the third dielectric layer is smaller than a thickness of the second dielectric layer, and a thickness of the second dielectric layer is smaller than a thickness of the first dielectric layer. A high electron mobility semiconductor device, comprising: a substrate; a Group III and V semiconductor layer disposed above the substrate; a barrier layer disposed above the Group III and V semiconductor layer; a first gate dielectric layer, disposed above the barrier layer and having a first energy gap; a second gate dielectric layer disposed above the first gate dielectric layer and having a second energy gap, wherein the second gate dielectric layer a gap greater than the first energy gap; a third gate dielectric layer above the second gate dielectric layer, and has a third energy gap, wherein the third energy gap is greater than the second energy gap; a a gate electrode disposed above the second gate dielectric layer and the third gate dielectric layer; and a source electrode and a drain electrode disposed on both sides of the gate electrode and extending through the The barrier layer is electrically connected to the III-V semiconductor layer. The high electron mobility semiconductor device according to claim 6, wherein the III-V semiconductor layer includes gallium nitride, and the barrier layer includes aluminum gallium nitride. The high electron mobility semiconductor device according to claim 6, further comprising: a third gate dielectric layer between the second gate dielectric layer and the gate electrode, and having a third energy gap, wherein The third energy gap is larger than the second energy gap. The high electron mobility semiconductor device according to claim 6, wherein a dielectric constant of the first gate dielectric layer is greater than 15. The high electron mobility semiconductor device according to claim 6, wherein a thickness of the third gate dielectric layer is less than a thickness of the second gate dielectric layer, and a thickness of the second gate dielectric layer is less than A thickness of the first gate dielectric layer.

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