CN111668302B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN111668302B
CN111668302B CN201910175488.4A CN201910175488A CN111668302B CN 111668302 B CN111668302 B CN 111668302B CN 201910175488 A CN201910175488 A CN 201910175488A CN 111668302 B CN111668302 B CN 111668302B
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layer
nitride
semiconductor device
barrier layer
compound semiconductor
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CN111668302A (en
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陈志谚
洪章响
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Vanguard International Semiconductor Corp
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Vanguard International Semiconductor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a via layer disposed over a substrate, a barrier layer disposed over the via layer, and a nitride layer disposed over the barrier layer. The semiconductor device also includes a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending over the nitride layer. In addition, the semiconductor device further includes a gate electrode disposed over the compound semiconductor layer, and a pair of source/drain electrodes disposed on both sides of the gate electrode. The source/drain electrode extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
Embodiments of the present invention relate to semiconductor devices, and more particularly, to high electron mobility transistors and methods of fabricating the same.
Background
A High Electron Mobility Transistor (HEMT), also known as a Heterostructure Field Effect Transistor (HFET) or a modulation-doped FET (MODFET), is a Field Effect Transistor (FET) composed of semiconductor materials with different energy gaps (energy gaps). A two-dimensional electron gas (2 DEG) layer is created adjacent to the formed interface of the different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor has the advantages of high breakdown voltage, high electron mobility, low on-resistance, low input capacitance and the like, and is suitable for high-power devices.
In designing high electron mobility transistors, a major consideration is low on-resistance (R) on ) And a high switching voltage (V) th ). However, the two-dimensional electron gas of gan hemts does not need to be doped, and the carrier sources are mainly surface states (surface states) and unintentional doping (indirect doping), which are essentially derived from carriers liberated by defects. The two-dimensional electron gas of the gan hemt is very sensitive to electric field variation and electromagnetic scattering (dispersion) occurs during the switching operation.
Thus, while existing gallium nitride high electron mobility transistors are generally desirable for their intended purposes, they are not entirely satisfactory in all respects. How to effectively solve the influence of electromagnetic scattering on the device performance is the key point of the current technical development.
Disclosure of Invention
The embodiment of the invention provides a semiconductor device. The semiconductor device includes a via layer disposed over a substrate, a barrier layer disposed over the via layer, and a nitride layer disposed over the barrier layer. The semiconductor device also includes a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending to the nitride layer. In addition, the semiconductor device further includes a gate electrode disposed over the compound semiconductor layer, and a pair of source/drain electrodes disposed on both sides of the gate electrode. The source/drain electrode extends through the spacer layer, the nitride layer and at least a portion of the barrier layer.
The embodiment of the invention provides a manufacturing method of a semiconductor device. The method includes forming a via layer over a substrate, forming a barrier layer over the via layer, forming a nitride layer over the barrier layer, recessing the nitride layer and the barrier layer to form a recess, wherein the recess penetrates the nitride layer and a portion of the barrier layer, conformably forming a spacer layer over the nitride layer and in the recess, and forming a compound semiconductor layer over the spacer layer. The compound semiconductor layer has an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer fills the recess. The method further includes forming a gate electrode over the compound semiconductor layer and forming a pair of source/drain electrodes on opposite sides of the gate electrode, wherein the source/drain electrodes extend through the spacer layer, the nitride layer, and at least a portion of the barrier layer.
The following embodiments and the accompanying reference drawings will provide detailed descriptions.
Drawings
Some embodiments of the present invention will be described in detail below with reference to the attached drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are merely illustrative. In fact, the dimensions of the devices may be arbitrarily increased or reduced to clearly illustrate the elements of the embodiments of the present invention.
FIGS. 1-5 depict cross-sectional views of various intermediate stages of an exemplary method for forming the semiconductor device of FIG. 6, in accordance with some embodiments;
FIG. 6 is a schematic view of a semiconductor device.
Description of the reference numerals
10-a semiconductor device;
100 to a substrate;
102-a nucleation layer;
104-a buffer layer;
106-channel layer;
108 barrier layers;
110-nitride layer;
112-notch;
114 to a spacer layer;
116-a compound semiconductor layer;
116a to upper portion;
116 b-lower part;
118 to a gate electrode;
120-source/drain electrodes;
w1, W2-thickness.
Detailed Description
The following disclosure provides many different embodiments, or examples, for illustrating different components of embodiments of the invention. Specific examples of components and arrangements thereof are disclosed below to simplify the present disclosure. Of course, these specific examples are not intended to be limiting of the invention. For example, the following summary of the present specification describes forming a first feature over or on a second feature, i.e., embodiments in which the formed first and second features are in direct contact, and embodiments in which additional features may be formed between the first and second features, i.e., the first and second features are not in direct contact. In addition, various examples of the present disclosure may use repeated reference characters and/or words. These repeated symbols or words are provided for simplicity and clarity and do not limit the relationship between the various embodiments and/or the configurations.
Furthermore, spatially relative terms, such as "under 823030971", "below", "lower", "above", "upper" and the like, may be used for convenience in describing the relationship of one device or component to another device(s) or component(s) in the figures. Spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (e.g., rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation. It should be understood that additional operations may be provided before, during, and/or after the methods described in embodiments of the invention, and that in other embodiments of the methods, some of the operations described may be replaced or omitted.
As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".
Some variations of the example methods and structures are described herein. Those of ordinary skill in the art will readily recognize that other modifications may be made within the scope of other embodiments. While some method embodiments are discussed as being performed in a particular order, various other method embodiments may be performed in another logical order and may include fewer or more steps than those discussed herein. In some of the drawings, reference numerals may be omitted where certain components or features are shown so as to avoid confusion with other components or features; this is for ease of depiction of these figures.
Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which are particularly suitable for a High Electron Mobility Transistor (HEMT). In some embodiments of the invention, the barrier layer is formed by disposing nitrogen on the barrier layerThe formation of notches by cutting the layers at the gate region eliminates the problem of electromagnetic scattering (dispersion) of the device, and allows the barrier layer outside the gate region to be thicker to reduce on-resistance and gate doping without reducing switching voltage. Thus, the on-resistance (R) can be released on ) Switching voltage (V) th ) And impasse of electromagnetic scattering triple-off.
Fig. 1-5 depict schematic cross-sectional views of various intermediate stages of an exemplary method for forming the semiconductor device 10 of fig. 6, in accordance with some embodiments.
Fig. 1 illustrates initial steps in a method of forming a semiconductor device 10 in accordance with an embodiment of the present invention. As shown in fig. 1, a substrate 100 is provided. Next, a buffer layer 104 is formed on the substrate 100, a channel layer 106 is formed on the buffer layer 104, and a barrier layer 108 is formed on the channel layer 106. In some embodiments, a nucleation layer (102) may be formed between the substrate 100 and the buffer layer 104, as shown in fig. 1.
The substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. Generally, semiconductor-on-insulator substrates include a film of semiconductor material formed on an insulator. For example, the insulating layer may be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a polysilicon (poly-silicon) layer, or a stacked combination thereof. The insulating layer is provided on a substrate, typically a silicon (silicon) or aluminum nitride (AlN) substrate. Other substrates, such as multi-layered or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include silicon including different crystal planes, including Si (111) or Si (110). In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Sapphire (Sapphire) substrate.
The nucleation layer 102 may mitigate lattice differences between the substrate 100 and overlying layers to improve crystal quality. The nucleation layer 102 is selective. In some embodiments, the material of the nucleation layer 102 may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or combinations thereof. For example, the nucleation layer 102 may have a thickness in a range from about 1 nanometer (nm) to about 500 nm, such as about 200 nm. In some embodiments, the nucleation Layer 102 may be formed by a Deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.
The buffer layer 104 may relieve strain (strain) in the channel layer 106 subsequently formed over the buffer layer 104 to prevent defects from forming in the channel layer 106 above, the strain being caused by a mismatch between the channel layer 106 and the substrate 102. In other embodiments, as mentioned above, the nucleation layer 102 may not be provided, and the buffer layer 104 may be formed directly on the substrate to simplify the process steps and achieve the improved effect. In some embodiments, the material of the buffer layer 104 may comprise a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 104 may be or include Gallium Nitride (GaN), aluminum Nitride (AlN), aluminum Gallium Nitride (AlGaN), aluminum indium Nitride (AlInN), other suitable materials, or combinations thereof. For example, the thickness of the buffer layer 104 may range from about 500 nanometers to about 50000 nanometers. In some embodiments, the buffer layer 104 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.
By means of piezoelectric polarization (piezoelectric polarization) effect and respective spontaneous polarization (spontaneous polarization) induced by different lattice constants between the channel layer 106 and the barrier layer 108, it is possible to achieve a heterogeneous interface between the channel layer 106 and the barrier layer 108A two-dimensional electron gas (2 DEG) is formed on the surface (not shown). The semiconductor device 10 shown in fig. 6 is a High Electron Mobility Transistor (HEMT) using a two-dimensional electron gas (2 DEG) as a conductive carrier. In some embodiments, the channel layer 106 and the barrier layer 108 are free of dopants. In some other embodiments, the channel layer 106 and the barrier layer 108 may have dopants, such as n-type dopants or p-type dopants. In a specific embodiment of the present invention, the channel layer 106 is a two-dimensional electron gas source by itself with non-intentional doping. The above-mentioned unintentional doping may be, for example, defects present in the background, free donors (donors), etc. In some embodiments, the non-intentionally doped dopant concentration is about 5x10 16 To about 5x10 17 cm -3 The range of (1).
In some embodiments, the material of the channel layer 106 may comprise one or more III-V compound semiconductor materials, such as a III-nitride. For example, the material of the channel layer 106 may be or include GaN, alGaN, alInN, inGaN, inAlGaN, other suitable materials, or combinations thereof. In some embodiments, the thickness of channel layer 106 may range between about 0.05 microns (μm) and about 1 micron, such as about 0.2 microns. According to some embodiments, the channel layer 106 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.
In some embodiments, the material of the barrier layer 108 may comprise a group III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 108 may be or include AlN, alGaN, alInN, alGaInN, other suitable materials, or combinations thereof. The barrier layer 108 may comprise a single layer or a multi-layer structure. Compared with the conventional high electron mobility transistor, the high electron mobility transistor of the embodiment of the invention has a thicker barrier layer, so that the on-resistance (R) of the device can be remarkably reduced on ). For example, the barrier layer 108 has a maximum thickness W1, and the maximum thickness W1 can be from about 10 nm to about 60 nmE.g., about 40 nanometers. In some embodiments, the barrier layer 108 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.
With continued reference to fig. 1, a nitride layer 110 is formed over the barrier layer 108. The nitride layer 110 protects the barrier layer 108 from oxidation during subsequent processing. In addition, the nitride layer 110 can also eliminate the electromagnetic scattering problem of the device, which will be described in detail later. In some embodiments, the material of the nitride layer 110 may be or include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlGaInN), indium gallium nitride (InGaN), other suitable materials, or combinations thereof. In some embodiments, the thickness of the nitride layer 110 may be in a range from about 1 nanometer to about 20 nanometers, such as about 5 nanometers. According to some embodiments, the nitride layer 110 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.
Next, as shown in fig. 2, the nitride layer 110 and the barrier layer 108 are etched back to form a recess 112, wherein the recess 112 penetrates the nitride layer 110 and a portion of the barrier layer 108. The recess 112 corresponds to a position where a gate electrode 118 (not shown in fig. 3, but refer to the description related to fig. 5) is to be formed. The formation of the recess 112 results in a portion of the barrier layer 108 located below the recess 112 having a reduced thickness W2. This reduced thickness W2 is located below the gate electrode 118 to be formed later (not shown in fig. 2, but see the description below with respect to fig. 5), which helps to increase the switching voltage (V) of the device th ). In some embodiments, this reduced thickness W2 may be in a range of about 5 nanometers to about 15 nanometers, such as about 10 nanometers.
Generally speaking, two main sources of two-dimensional electron gas of gan hemts are carriers liberated from surface states (surface states) and unintentional doping from a channel layer; the two-dimensional electron gas is generally the former due to the heterostructure and polarizing electric field between the barrier layer and the channel layer. Therefore, when the semiconductor device is in an off state, carriers in the channel layer are drawn by a high electric field at the surface and confined. When the semiconductor device is switched from the off state to the on state, the confined carriers in the channel layer 106 are not released in time (i.e., the relaxation time is too long), resulting in a decrease in current, which is an electromagnetic scattering problem. In the embodiment of the invention, because the nitride layer contains most of free carriers from surface states, the channel layer below the nitride layer is forced to extract the carriers from unintentional doping, and therefore the channel layer is prevented from being influenced by a high electric field in an off state. In addition, the nitride layer 110 is interrupted by the notch 112, so that the nitride layer 110 does not participate in current conduction in the on state of the semiconductor device 10, and thus, the electromagnetic scattering problem is avoided. In this way, the nitride layer 110 can replace the channel layer 116 to bear the high electric field of the surface state, so as to avoid the electromagnetic scattering problem of the semiconductor device 10.
In some embodiments, the nitride layer 110 and the barrier layer 108 may be recessed by a patterning process to form the recess 112. For example, the patterning process may include a photolithography process (e.g., photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist developing, other suitable processes, or combinations thereof), an etching process (e.g., wet etching, dry etching, other suitable processes, or combinations thereof), other suitable processes, or combinations thereof. In some embodiments, a patterned photoresist layer (not shown) having an opening corresponding to the recess 112 may be formed on the nitride layer 110 by a photolithography process, and then an etching process may be performed to remove portions of the nitride layer 110 and the barrier layer 108 exposed by the opening of the patterned photoresist layer, so as to form the recess 112 in the nitride layer 110 and the barrier layer 108. The patterned photoresist layer may then be removed by a process such as ashing or wet stripping.
Referring to fig. 3, a spacer layer 114 is conformally formed on the nitride layer 110 and in the recess 112, such that the spacer layer 114 is conformally formed on the bottom and sidewalls of the recess 112. In some embodiments, the energy gap (bandgap) of the spacer layer 114 is larger than that of the subsequently formed compound semiconductor layer 116 (not shown in fig. 3, but refer to the description below with respect to fig. 5). Therefore, the spacer layer 114 can prevent the dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10, thereby avoiding the increase of on-resistance and reducing the electromagnetic scattering problem of the device. In addition, the spacer layer 114 may also serve as an Etch Stop Layer (ESL) to stop the etching process during the subsequent etching process for forming the compound semiconductor layer 116.
The spacer layer 114 may be formed of a material having a different etch selectivity from that of an adjacent film layer or member (i.e., the compound semiconductor layer 116). In some embodiments, the spacer layer 114 is an aluminum-containing nitride. For example, the material of the spacer layer 114 may be or include AlN, alGaN, alInN, alGaInN, other suitable materials, or combinations thereof. In a specific embodiment, the spacer layer 114 is AlN. Further, in some embodiments, the thickness of the spacer layer 114 may be in a range from about 1 nanometer to about 7 nanometers, such as about 2 nanometers.
Fig. 4 illustrates the formation of compound semiconductor layer 116. In some embodiments, a compound semiconductor layer 116 is conformally formed over the spacer layer 114, and then patterned by photolithography and etching, wherein the compound semiconductor layer has an upper portion 116a and a lower portion 116b, and wherein the lower portion 116b of the compound semiconductor layer 116 is defined as the portion of the compound semiconductor layer 116 filling the recess 112, as shown in fig. 4. In other words, the compound semiconductor layer 116 corresponds to a position where a gate electrode 118 (not shown in fig. 3, but refer to the description about fig. 5 described below) is to be formed. The compound semiconductor layer 116 may suppress generation of a two-dimensional electron gas (2 DEG) under the gate electrode 118 to achieve a normally-off state of the semiconductor device.
In some embodiments, the material of the compound semiconductor layer 116 may be p-type doped or n-type doped gallium nitride (GaN). For example, the thickness of the upper portion 116a of the compound semiconductor layer 116 may be in a range of about 5 to about 100 nanometers, such as about 60 nanometers, and the thickness of the lower portion 116b of the compound semiconductor layer 116 may be in a range of about 7 to about 72 nanometers, such as about 40 nanometers. In some embodiments, the doping concentration of the upper portion 116a of the compound semiconductor layer 116 may be different from the doping concentration of the lower portion 116b of the compound semiconductor layer 116.
In some embodiments, the compound semiconductor layer 116 may be formed by a deposition process and a patterning process. For example, a deposited material layer may be formed on the spacer layer 114 by a deposition process, wherein a portion of the deposited material layer fills the recess 112. In some embodiments, the patterning process includes forming a patterned mask layer (not shown) on the deposited material layer, then etching a portion of the deposited material layer not covered by the patterned mask layer, and forming the compound semiconductor layer 116.
In some embodiments, the deposition process may include Metal Organic Chemical Vapor Deposition (MOCVD), atomic Layer Deposition (ALD), molecular Beam Epitaxy (MBE), liquid Phase Epitaxy (LPE), similar processes, or combinations thereof.
In some embodiments, the patterned mask layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned masking layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or combinations thereof. In some embodiments, the patterned mask layer may be formed by spin-on coating (spin-on coating), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), other suitable processes, or combinations thereof.
In some embodiments, the deposited material layer may be etched by a dry etch process, a wet etch process, or a combination of the foregoing. For example, the etching of the deposited material layer includes Reactive Ion Etching (RIE), inductively Coupled Plasma (ICP) etching, neutron Beam Etching (NBE), electron cyclotron resonance (ERC) etching, other suitable etching processes, or a combination thereof.
In some embodiments, the upper portion 116a of the compound semiconductor layer 116 may extend to the surface of the spacer layer 114 outside the recess, i.e., the compound semiconductor layer 116 has a T-shape in the cross-sectional view, as shown in fig. 4. In other embodiments, the upper portion 116a of the compound semiconductor layer 116 does not extend to the surface of the spacer layer 114 outside the recess, so that the compound semiconductor layer 116 has a rectangular shape (not shown) in the cross-sectional view. In some embodiments, the upper surface of the compound semiconductor layer 116 may be uneven. In some embodiments, the length of the upper portion 116a of the compound semiconductor layer 116 extending to the surface of the spacer layer 114 outside the recess may be asymmetric.
In some embodiments, the formation of the compound semiconductor layer 116 further comprises doping with dopants to increase the switching voltage (V) of the semiconductor device 10 th ). For example, for a compound semiconductor layer 116 of p-type doped gallium nitride, the dopant may comprise magnesium (Mg). Generally, during the fabrication of semiconductor devices, multiple heat treatments are typically performed, such that dopants thermally diffuse out of the compound semiconductor layer and into other components, thereby affecting the performance of the semiconductor device, such as increasing on-resistance and causing electromagnetic scattering problems in the device. However, in the embodiment of the invention, since the compound semiconductor layer 116 is separated from other elements by the spacer layer 114, the dopant in the compound semiconductor layer 116 can be prevented from thermally diffusing into other elements. Thus, the problems of the increase of the on-resistance and the electromagnetic scattering of the device can be avoided, and the performance of the semiconductor device 10 can be improved.
Furthermore, in the embodiment of the present invention, since the barrier layer 108 located under the predetermined position of the gate electrode 118 has the reduced thickness W2 (see fig. 5), the reduced thickness W2 helps to increase the switching voltage of the semiconductor device 10. In other words, the compound semiconductor layer 116 may have a smaller dopant concentration under the same switching voltage, reducing the influence of dopant thermal diffusion to other components, which also helps to reduce the electromagnetic scattering problem of the device.
Referring to fig. 5, a gate electrode 118 is formed on the compound semiconductor layer 116. In some embodiments, the material of the gate electrode 118 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), a similar material, an alloy thereof, a multi-layer structure thereof, or a combination thereof, and the semiconductor material may be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge). In some embodiments, the step of forming the gate electrode 118 may include comprehensively depositing a conductive material layer (not shown) for the gate electrode 118 over the substrate 100, and performing a patterning process on the conductive material layer to form the gate electrode 118 over the compound semiconductor layer 116. The deposition process to form the conductive material may be Atomic Layer Deposition (ALD), chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) (e.g., sputtering), combinations of the foregoing, or the like.
Next, referring to fig. 6, a pair of source/drain electrodes 120 are disposed on both sides of the gate electrode 118, wherein the pair of source/drain electrodes 120 extend through the spacer layer 114, the nitride layer 110, and a portion of the barrier layer 108. In some embodiments, the forming of the pair of source/drains 120 includes performing a patterning process to recess the spacer layer 114, the nitride layer 110, and a portion of the barrier layer 108 on both sides of the compound semiconductor layer 116, forming a pair of recesses through the spacer layer 114 and the nitride layer 110 and extending to the barrier layer 108, then depositing a conductive material over the pair of recesses, and performing a patterning process on the deposited conductive material to form the pair of source/drains 120 at desired locations. The deposition process and materials used to form the pair of source/drain electrodes 120 may be similar to the deposition process and materials of the gate electrode 118 and are not described in detail herein.
Although the source/drain 120 is located on the spacer 114, passes through the spacer 114 and the nitride layer 110, and extends to the barrier layer 108 in the embodiment shown in fig. 6, the invention is not limited thereto, and the depth of the source/drain 120 may be adjusted according to the characteristics required by the actual product. For example, the source/drain 120 may also extend through the barrier layer 108 and into the channel layer 106.
Although the source/drain electrodes 120 and the gate electrode 118 are described herein as being formed in different steps, the present invention is not limited thereto. For example, the source/drain electrodes 120 and the gate electrode 118 may be formed simultaneously by a deposition process and a patterning process after forming the recesses for the source/drain electrodes 120 before forming the gate electrode 118. Also, the formation of the source/drain electrodes 120 and the gate electrode 118 may independently comprise the same or different processes and materials. In addition, the shapes of the source/drain electrodes 120 and the gate electrode 118 are not limited to the vertical sidewalls in the drawings, and may be sloped sidewalls or have other features.
As shown in fig. 6, the semiconductor device 10 includes a channel layer 106 disposed over a substrate 100, a barrier layer 108 disposed over the channel layer 106, and a nitride layer 110 disposed over the barrier layer 108. In some embodiments, the barrier layer 108 has a maximum thickness W1 in a range from about 10 nanometers to about 60 nanometers. The semiconductor device 10 has a thicker barrier layer 108 than a typical hemt, thereby significantly reducing the on-resistance (R) on ). In addition, the nitride layer 110 can withstand a high electric field in a surface state instead of the channel layer 116, thereby avoiding the electromagnetic scattering problem of the semiconductor device 10.
The semiconductor device 10 also includes a compound semiconductor layer 116 having an upper portion 116a and a lower portion 116b, wherein the lower portion 116b passes through the nitride layer 110 and a portion of the barrier layer 108. In addition, the semiconductor device 10 also includes a spacer layer 114 conformally disposed on the lower portion 116b of the compound semiconductor layer 116 and extending to the nitride layer 110. The spacer layer 114 prevents dopants in the compound semiconductor layer 116 from diffusing into other components of the semiconductor device 10, thereby avoiding the problems of increased on-resistance and electromagnetic scattering of the device, and improving the performance of the semiconductor device 10.
The semiconductor device 10 further includes a gate electrode 118 disposed on the compound semiconductor layer 116, and a pair of source/drain electrodes 120 disposed on both sides of the gate electrode 118, the source/drain electrodes 120 extending through the spacer layer 114 and the nitride layer110 and at least a portion of barrier layer 108. The barrier layer 108 has a reduced thickness W2 (see fig. 5) below the gate electrode 118, which reduced thickness W2 helps to increase the switching voltage (V) of the semiconductor device 10 th ). In other words, the compound semiconductor layer 116 may have a smaller dopant concentration under the same switching voltage, reducing the influence of dopant thermal diffusion to other components, which also helps to reduce the electromagnetic scattering problem of the device. In some embodiments, this reduced thickness W2 ranges from about 5 nanometers to about 15 nanometers.
In some embodiments, the semiconductor device 10 further includes a buffer layer 104 between the substrate 100 and the via 106, wherein the buffer layer 104 relieves strain (strain) in the via layer 106 subsequently formed over the buffer layer 104 to prevent defects from forming in the overlying via layer 106.
In summary, the semiconductor device according to the embodiment of the invention includes the nitride layer disposed on the barrier layer, and the problem of electromagnetic scattering (dispersion) of the semiconductor device can be solved by the nitride layer. Thus, the on-resistance (R) can be released on ) Switching voltage (V) th ) And impasse of three-way exchange by electromagnetic scattering.
The foregoing has outlined rather broadly the features of several embodiments of the present invention so that those skilled in the art may better understand the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should be understood by those skilled in the art that the same structures or processes as described above may be adopted without departing from the spirit and scope of the present invention, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention.

Claims (22)

1. A semiconductor device, comprising:
a channel layer disposed on a substrate;
a barrier layer disposed on the channel layer;
a nitride layer disposed on the barrier layer;
a compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion passes through the nitride layer and only a portion of the barrier layer;
a spacer layer conformally disposed on a remaining portion of the barrier layer and extending to the nitride layer;
a gate electrode disposed on the compound semiconductor layer; and
a pair of source/drain electrodes disposed on either side of the gate electrode, wherein the pair of source/drain electrodes extend through the spacer layer, the nitride layer, and at least a portion of the barrier layer.
2. The semiconductor device according to claim 1, wherein the nitride layer comprises gallium nitride, aluminum indium gallium nitride, or any combination thereof.
3. The semiconductor device of claim 1, wherein the thickness of the nitride layer is in a range of 1 nm to 20 nm.
4. The semiconductor device according to claim 1, wherein the spacer layer has a larger energy gap than the compound semiconductor layer and the nitride layer.
5. The semiconductor device according to claim 4, wherein the spacer layer comprises aluminum nitride, aluminum gallium nitride, aluminum indium gallium nitride, or any combination thereof.
6. The semiconductor device of claim 1, wherein the spacer layer has a thickness in a range from 1 nm to 7 nm.
7. The semiconductor device of claim 1, wherein the pair of source/drain electrodes pass through the barrier layer and extend to the channel layer.
8. The semiconductor device of claim 1, wherein the barrier layer has a maximum thickness, wherein the maximum thickness is in a range from 10 nm to 60 nm.
9. The semiconductor device of claim 8, wherein the remaining portion of the barrier layer has a minimum thickness directly below the lower portion of the compound semiconductor layer, the minimum thickness being in a range from 5 nm to 15 nm.
10. The semiconductor device of claim 1, further comprising a buffer layer between the substrate and the channel layer.
11. The semiconductor device according to claim 1, wherein an upper portion and a lower portion of the compound semiconductor layer have different doping concentrations.
12. A method of manufacturing a semiconductor device, the method comprising:
forming a channel layer on a substrate;
forming a barrier layer over the channel layer;
forming a nitride layer on the barrier layer;
recessing the nitride layer and the barrier layer to form a recess, wherein the recess passes through the nitride layer and only a portion of the barrier layer;
conformably forming a spacer layer on said nitride layer and in said recess;
forming a compound semiconductor layer over the spacer layer, the compound semiconductor layer having an upper portion and a lower portion, wherein the lower portion of the compound semiconductor layer fills in the recess;
forming a gate electrode on the compound semiconductor layer; and
forming a pair of source/drain electrodes on both sides of the gate electrode, wherein the pair of source/drain electrodes extend through the spacer layer, the nitride layer, and at least a portion of the barrier layer.
13. The method of claim 12, wherein the nitride layer comprises gallium nitride, aluminum indium gallium nitride, or any combination thereof.
14. The method of manufacturing a semiconductor device according to claim 12, wherein a thickness of the nitride layer is in a range of 1 nm to 20 nm.
15. The method for manufacturing a semiconductor device according to claim 12, wherein the spacer layer has a larger energy gap than the compound semiconductor layer and the nitride layer.
16. The method of claim 15, wherein the spacer layer comprises aluminum nitride, aluminum gallium nitride, aluminum indium gallium nitride, or any combination thereof.
17. The method of manufacturing a semiconductor device according to claim 12, wherein a thickness of the spacer layer is in a range of 1 nm to 7 nm.
18. The method of manufacturing a semiconductor device according to claim 12, wherein the pair of source/drain electrodes pass through the barrier layer and extend to the channel layer.
19. The method of claim 12, wherein the barrier layer has a maximum thickness, and wherein the maximum thickness is in a range of 10 nm to 60 nm.
20. The method of claim 19, wherein the etched portion of the barrier layer has a minimum thickness directly below the recess, the minimum thickness being in a range of 5 nm to 15 nm.
21. The method of claim 12, further comprising forming a buffer layer between the substrate and the channel layer.
22. The method for manufacturing a semiconductor device according to claim 12, wherein an upper portion and a lower portion of the compound semiconductor layer have different doping concentrations.
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