TW202010125A - Semiconductor devices and methods for forming same - Google Patents

Abstract

A semiconductor device including a channel layer disposed over a substrate; a barrier layer disposed over the channel layer; a compound semiconductor layer and a dopant holding layer disposed over the barrier layer; and a pair of source/drain disposed over the substrate and on both sides of the compound semiconductor layer; and a gate disposed over the compound semiconductor layer.

Description

Semiconductor device and its manufacturing method

The embodiments of the present invention relate to semiconductor manufacturing technologies, and in particular, to semiconductor devices and manufacturing methods thereof.

High electron mobility transistor (HEMT), also known as heterostructure field effect transistor (HFET) or modulation-doped field effect transistor (MODFET), is a kind of A field effect transistor (FET) is composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2 DEG) layer is generated at the formed interface adjacent to different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have the advantages of high breakdown voltage, high electron mobility, low on-resistance and low input capacitance, and is therefore suitable for high power components.

In order to improve efficiency, high electron mobility transistors are usually doped. However, this doping process may be accompanied by defects and may even damage high electron mobility transistors. Therefore, it is necessary to continue to develop improved high electron mobility transistors to improve yield, improve yield, and have wider applications.

According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; a compound semiconductor layer and a doped retention layer disposed above the barrier layer; a pair of source/drain electrodes disposed above the substrate And located on both sides of the compound semiconductor layer; and the gate electrode is provided on the compound semiconductor layer.

In some embodiments, the dopant content within the dopant retention layer is greater than the dopant content outside the dopant retention layer.

In some embodiments, the doped retention layer includes aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination of the foregoing.

In some embodiments, the thickness of the doped retention layer is in the range of 0.5 nm to 5 nm.

In some embodiments, the dopant retention layer includes a first dopant retention layer disposed on top, inside, or bottom of the compound semiconductor layer; and/or a second dopant retention layer covering the sidewall of the compound semiconductor layer and facing the source here The pole/drain extends between the barrier layer.

In some embodiments, the semiconductor device further includes the pair of source/drain electrodes passing through the barrier layer and extending into the channel layer, and the second doped retention layer extends between the pair of source/drain electrodes and the channel layer .

In some embodiments, the second holding layer has an opening, is disposed on the compound semiconductor layer, and the gate is disposed at the opening.

In some embodiments, the semiconductor device further includes a two-dimensional electron gas recovery layer covering the sidewalls of the compound semiconductor layer and extending between the source/drain pair and the barrier layer.

In some embodiments, the semiconductor device further includes the pair of source/drain electrodes passing through the barrier layer and extending into the channel layer, and the two-dimensional electron gas recovery layer extends between the pair of source/drain electrodes and the channel layer .

In some embodiments, the two-dimensional electron gas recovery layer includes a hexagonal binary semiconductor, graphene, or a combination of the foregoing.

According to other embodiments of the present invention, a method for manufacturing a semiconductor device is provided. This method includes forming a channel layer above the substrate; forming a barrier layer above the channel layer; forming a compound semiconductor layer and a doped retention layer above the barrier layer; forming a pair of source electrodes above the substrate and on both sides of the compound semiconductor layer /Drain; and forming a gate above the compound semiconductor layer

In some embodiments, the formation of the dopant retention layer includes using organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, or a combination of the foregoing.

In some embodiments, the doped retention layer includes aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination of the foregoing.

In some embodiments, the thickness of the doped retention layer is in the range of 0.5 nm to 5 nm.

In some embodiments, the formation of the dopant retention layer includes: during the formation of the compound semiconductor layer, forming a first dopant retention layer in situ on the top, inside, or bottom of the compound semiconductor layer; and/or on the sidewall of the compound semiconductor layer A second doped retention layer is formed thereon, and the second doped retention layer extends between the pair of source/drain and the channel layer.

In some embodiments, the pair of source/drain electrodes extends further into the channel layer, and the second dopant retention layer extends between the pair of source/drain electrodes and the channel layer.

In some embodiments, the second doped retention layer has an opening formed above the compound semiconductor layer, and the gate is disposed at the opening.

In some embodiments, the manufacturing method of the semiconductor device further includes forming a two-dimensional electron gas recovery layer on the sidewall of the compound semiconductor layer, and the two-dimensional electron gas recovery layer extends between the source/drain and the channel layer.

In some embodiments, the pair of source/drain electrodes further passes through the barrier layer and extends into the channel layer, and the two-dimensional electron gas recovery layer extends between the pair of source/drain and channel layers.

In some embodiments, the two-dimensional electron gas recovery layer includes a hexagonal binary semiconductor, graphene, or a combination of the foregoing.

100, 200, 300, 400 ‧‧‧ semiconductor device

110‧‧‧ base

120‧‧‧Nuclear layer

130‧‧‧buffer layer

140‧‧‧channel layer

150‧‧‧ barrier layer

160‧‧‧ Compound semiconductor layer

170‧‧‧ First doping retention layer

180‧‧‧ source/drain

190‧‧‧Gate

210‧‧‧Second doped retention layer

220, 420‧‧‧ opening

410‧‧‧Two-dimensional electronic gas recovery layer

T1, T2, T3 ‧‧‧ thickness

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to industry standard practices, various features are not drawn to scale and are for illustrative purposes only. In fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

1A-1C are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device according to some embodiments.

Figures 2-4 are schematic cross-sectional views of semiconductor devices according to some other embodiments.

Some embodiments are summarized below so that those with ordinary knowledge in the technical field to which the present invention belongs can more easily understand the present invention. However, these embodiments are only examples and are not intended to limit the present invention. It can be understood that those with ordinary knowledge in the technical field to which the present invention belongs can adjust the embodiments described below according to requirements, for example, changing the process sequence and/or including more or fewer steps than described herein.

In addition, other elements may be added on the basis of the embodiments described below. For example, the description of "forming a second element on a first element" may include an embodiment where the first element and the second element are in direct contact, or may include other elements between the first element and the second element, so that An embodiment in which an element does not directly contact the second element, and the up-down relationship of the first element and the second element may change as the device is operated or used in different orientations.

In the following, according to some embodiments of the present invention, a semiconductor device and a manufacturing method thereof will be described, and it is particularly suitable for a high electron mobility transistor (HEMT). In the present invention, a dopant retention layer is provided in the semiconductor device to prevent the dopant in the compound semiconductor layer from diffusing to surrounding components, and to avoid subsequent processes such as an etching process from affecting the area within the dopant retention layer and improve the yield of the semiconductor device.

1A-1C are schematic cross-sectional views illustrating various stages of manufacturing the semiconductor device 100 according to some embodiments. As shown in FIG. 1A, the semiconductor device 100 includes a substrate 110. Any base material suitable for semiconductor devices can be used. The substrate 110 may be a bulk semiconductor substrate or a composite substrate including different materials, and the substrate 110 may be doped (for example, using p-type or n-type dopants) or undoped. In some embodiments, the substrate 110 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon germanium substrate, silicon carbide (SiC), aluminum nitride (AlN) substrate, sapphire (Sapphire) ) Substrate, combinations of the foregoing, or similar materials. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) substrate, which is formed by disposing a semiconductor material on the insulating layer.

In some embodiments, a nucleation layer 120 is formed above the substrate 110 to alleviate the lattice difference between the substrate 110 and the film layer grown above and improve the crystalline quality. The formation of the nucleation layer 120 may include a deposition process, such as metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD), atomic layer deposition (Atomic Layer Deposition, ALD), molecular beam epitaxy (Molecular Beam Epitaxy, MBE) , Liquid Phase Epitaxy (LPE), a similar process, or a combination of the foregoing. In some embodiments, the thickness of the nucleation layer 120 may be in the range of about 1 nanometer (nm) to about 500 nm, such as about 200 nm.

In some embodiments, a buffer layer 130 is formed above the nucleation layer 120 to alleviate the lattice difference between different film layers and improve the crystal quality. The nucleation layer 120 is selective. In other embodiments, the nucleation layer 120 may not be provided, and the buffer layer 130 may be formed directly on the substrate, and the process steps may be reduced to achieve an improved effect. In some embodiments, the material of the buffer layer 130 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 130 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (AlInN), similar materials, or the foregoing combination. In some embodiments, the formation of the buffer layer 130 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination of the foregoing.

Next, a channel layer 140 is formed on the buffer layer 130. In some embodiments, the material of the channel layer 140 may include one or more group III-V compound semiconductor materials, such as group III nitride. In some embodiments, the material of the channel layer 140 is, for example, GaN, AlGaN, InGaN, InAlGaN, similar materials, or a combination of the foregoing. In addition, the channel layer 140 may be doped or undoped. According to some embodiments, the formation of the channel layer 140 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination of the foregoing. In some embodiments, the thickness of the channel layer 140 is in a range between about 0.05 microns (micrometer, μm) and about 1 μm, such as about 0.2 μm.

A barrier layer 150 is then formed over the channel layer 140 to generate two-dimensional electron gas at the interface between the channel layer 140 and the barrier layer 150. The formation of the barrier layer 150 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination of the foregoing. In some embodiments, the material of the barrier layer 150 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 150 may include AlN, AlGaN, AlInN, AlGaInN, similar materials, or a combination of the foregoing. The barrier layer 150 may include a single-layer or multi-layer structure, and the barrier layer 150 may be doped or undoped. In some embodiments, the thickness of the barrier layer 150 may be in a range between about 1 nm and about 30 nm, such as about 20 nm.

Next, as shown in FIG. 1B, according to some embodiments, a compound semiconductor layer 160 is provided above the barrier layer 150 to achieve a normally-off state of the semiconductor device with the two-dimensional electron gas under the depleted gate. In some embodiments, the compound semiconductor layer 160 includes u-type, n-type, or p-type doped gallium nitride. In some embodiments, the thickness of the compound semiconductor layer 160 may range between about 30 nm and about 150 nm, for example, about 80 nm.

In some embodiments, the formation of the compound semiconductor layer 160 may include a deposition process and a patterning process. For example, the deposition process includes organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination of the foregoing. In some embodiments, the patterning process includes forming a patterned mask layer (not shown) on the deposited material layer, then etching a portion of the deposited material layer that is not covered by the patterned mask layer, and forming a compound semiconductor layer 160. The position of the compound semiconductor layer 160 is adjusted according to a predetermined position of the gate.

In some embodiments, the patterned mask layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned mask layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, similar materials, or a combination of the foregoing. In some embodiments, the formation of the patterned mask layer may include spin-on coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), similar Process or a combination of the foregoing.

In some embodiments, the etching of the deposited material layer may use a dry etching process, a wet etching process, or a combination of the foregoing. For example, the etching of the deposited material layer includes reactive ion etching (Reactive Ion Etch, RIE), inductively coupled plasma (Inductively-Coupled Plasma, ICP) etching, neutron beam etching (Neutral Beam Etch, NBE), Electron Cyclotron Resonance (ERC) etching, similar etching process, or a combination of the foregoing.

In addition, although the compound semiconductor layer 160 in the figure has substantially vertical sidewalls and a flat upper surface, the present invention is not limited thereto, and the compound semiconductor layer 160 may also have other shapes, such as inclined sidewalls and/or uneven upper surfaces surface.

In some embodiments, the formation of the compound semiconductor layer 160 further includes doping using dopants. For example, for the compound semiconductor layer 160 whose material is p-type doped gallium nitride, the dopant may include magnesium. However, during the manufacturing process of the semiconductor device 100, multiple heat treatments are usually performed, so that the dopant thermally diffuses out of the compound semiconductor layer 160 and enters other components, affecting the performance of the semiconductor device 100, such as lowering the threshold voltage (Vththreshold voltage, Vth) ).

According to some embodiments, as shown in FIG. 1B, a first dopant holding layer 170 is provided in the compound semiconductor layer 160 to form a stable alloy with the dopant to prevent the dopant from diffusing out to other components. In some embodiments, the formation of the first doped retention layer 170 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination of the foregoing. And the first dopant holding layer 170 may be formed in situ during the formation of the compound semiconductor layer 160. In some embodiments, the thickness T1 of the first doped retention layer 170 is in the range of about 0.5 nm to about 5 nm, for example, about 4 nm.

In some embodiments, the material of the first doped retention layer 170 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), similar materials, or a combination of the foregoing. Since the material selected for the first dopant holding layer 170 can form an alloy with the dopant, for example, magnesium aluminum alloy, the dopant can be fixed at the position of the first dopant holding layer 170. Therefore, the dopant content in the first dopant holding layer 170 is greater than the dopant content outside the first dopant holding layer 170.

Although in the illustrated embodiment, the first doped retention layer 170 is located inside the compound semiconductor layer 160, the invention is not limited thereto, and the position of the first doped retention layer 170 can be adjusted, for example, the first doped retention layer 170 It may be provided on the top or bottom of the compound semiconductor layer 160. In some embodiments, the first doped retention layer 170 is disposed inside the compound semiconductor layer 160, compared to the first doped retention layer 170 located on the top or bottom of the compound semiconductor layer 160, because the first doped retention layer 170 is separated from other components (such as the barrier layer 150) by a distance, which can keep the dopant farther away from other components, and further reduce the possibility of the dopant affecting other components.

Next, as shown in FIG. 1C, according to some embodiments, a pair of source/drain 180 and gate 190 are provided to form the semiconductor device 100. The pair of source/drain electrodes 180 are respectively located on both sides of the compound semiconductor layer 160 above the substrate. In some embodiments, the formation of the source/drain 180 and the gate 190 includes performing a patterning process to etch the barrier layer 150 and the channel layer 140 on both sides of the compound semiconductor layer 160 to form a through resistance The barrier layer 150 extends to a pair of recesses in the channel layer 140, and then a conductive material is deposited on the recesses and the compound semiconductor layer 160, and a patterning process is performed on the deposited conductive material to form the pair of sources at the desired location Pole/drain 180 and gate 190.

In some embodiments, the deposition process of the conductive material may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination of the foregoing. In some embodiments, the conductive material may include metal, metal silicide, semiconductor material, similar materials, or a combination of the foregoing. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al ), copper (Cu), titanium nitride (TiN), similar materials, the aforementioned alloys, the aforementioned multilayer structure, or a combination of the aforementioned, and the semiconductor material may include poly-Si or poly-Ge ).

Although in the embodiment shown in FIG. 1C, the pair of source/drain 170 is located on the barrier layer 150 and extends into the barrier layer 150 and the channel layer 140, the present invention is not limited to this, and can be based on actual conditions The desired characteristics of the product adjust the depth to which this pair of source/drain 170 extends. For example, the pair of source/drain 170 may only extend into part of the barrier layer 150, or may not extend into the barrier layer 150, to prevent the pair of source/drain 170 from passing through the two-dimensional electron gas , Thereby maintaining the two-dimensional electron gas at the interface between the channel layer 140 and the barrier layer 150.

Although it is described here that the source/drain 180 and the gate 190 are formed in the same step, the present invention is not limited thereto. For example, the gate 190 may be formed after the source/drain 180 is formed. And, the formation of the source/drain 180 and the gate 190 may independently include the same or different processes and materials. In addition, the shapes of the source/drain 180 and the gate 190 are not limited to the vertical side walls in the drawings, but may be inclined side walls or have other shapes.

According to some embodiments of the present invention, the first dopant holding layer 170 is provided in the semiconductor device 100, in addition to forming a stable alloy with the dopant in the compound semiconductor layer 160, improving the thermal stability of the dopant to avoid doping The diffusion of surrounding components can also protect the area below it during subsequent processes, improving the yield of the semiconductor device 100. In addition, the first dopant holding layer 170 provided inside the compound semiconductor layer 160 can provide a gap between the alloy formed by the dopant and the first dopant holding layer 170 and other components, further reducing the possible adverse effects of doping.

FIG. 2 is a schematic cross-sectional view of a semiconductor device 200 according to other embodiments. In some embodiments, the second dopant holding layer 210 may be provided to cover the sidewalls of the compound semiconductor layer 160 and extend between the pair of source/drain 180 and the barrier layer 150 to prevent the dopant from diffusing out and Protect the components below it.

In some embodiments, the formation of the second dopant retention layer 210 may use the process and material of the first dopant retention layer 170 as described above. Since the material selected for the second dopant holding layer 210 can form a thermally stable alloy with the dopant, the dopant can be fixed at the position of the second dopant holding layer 210. Therefore, the dopant content in the second dopant holding layer 210 is greater than the dopant content outside the second dopant holding layer 210. In some embodiments, the thickness T2 of the second doped retention layer 210 is in the range of about 0.5 nm to about 5 nm, for example, about 4 nm.

After the second doped retention layer 210 is formed, an opening 220 is formed in the second doped retention layer 210, and the opening 420 is located above the compound semiconductor layer 160. The position of the opening 220 is adjusted according to the predetermined position of the gate electrode 190. In some embodiments, the opening 220 may be formed using a patterned mask layer (not shown), and a portion of the second doped retention layer 210 exposed by the patterned mask layer is etched to remove this portion of the second Doped retention layer 210. The materials and methods for forming the patterned mask layer are as described above and will not be repeated here.

In some embodiments, the etching of the second doped retention layer 210 may use a dry etching process, a wet etching process, or a combination of the foregoing. For example, the etching of the second doped retention layer 210 includes reactive ion etching (RIE), inductively coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron resonance (ERC) etching, and the like Etching process or a combination of the foregoing.

Next, a conductive material is deposited in the opening 220 and the pair of grooves to set a pair of source/drain 180 above the barrier layer 150, which are located on both sides of the compound semiconductor layer 160, and a gate in the opening 220 190, to form the semiconductor device 200. Although it is described here that the source/drain 180 and the gate 190 are simultaneously formed, the present invention is not limited thereto. For example, the opening 220 may be formed after the source/drain 180 is formed, and then the gate 190 may be formed using the same patterned mask layer as the opening 220. And, the formation of the source/drain 180 and the gate 190 may independently include the same or different processes and materials. In addition, the shapes of the source/drain 180 and the gate 190 are not limited to the vertical side walls in the drawings, but may be inclined side walls or have other shapes. Although in the embodiment shown in FIG. 2, the opening 220 and the bottom surface of the gate electrode 190 have substantially the same area, the invention is not limited thereto.

As described above, the depth of the source/drain 180 to the film layer can be adjusted, so the position of the second dopant holding layer 210 can also be adjusted accordingly. For example, in some embodiments, for the pair of source/drain 180 only extending into part of the barrier layer 150 or not extending into the barrier layer 150, the second doped retention layer 210 is set to extend Up to the source/drain pair 180 and the barrier layer 150. On the other hand, for the case where the pair of source/drain 180 further extends into the channel layer 140, the second doped retention layer 210 is further disposed between the pair of source/drain 180 and the channel layer 140.

According to some embodiments of the present invention, the second dopant-retaining layer 210 is provided on the semiconductor device 200 to cover the sidewalls of the compound semiconductor layer 160 and extends between the source/drain 180 and the barrier layer 150, which may be in contact with the compound semiconductor layer 160 The admixtures inside form a stable alloy, which improves the thermal stability of the admixtures to avoid the diffusion of the admixtures. In addition, the second doped retention layer 210 can protect the area under it and suppress leakage during subsequent processes, improving the yield and reliability of the semiconductor device 200.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 300 according to some embodiments. In some embodiments, as shown in FIG. 3, the first dopant holding layer 170 and the second dopant holding layer 210 may be provided at the same time to further improve the thermal stability of the dopant, and also protect the first doping more completely The region under the mass retention layer 170 and the second doped retention layer 210, and leakage can be reduced. The positions, materials, and processes of the first doped retention layer 170 and the second doped retention layer 210 are as described above, and the description will not be repeated here.

For ease of illustration, the thickness T1 of the first doped retention layer 170 and the thickness T2 of the second doped retention layer 210 are substantially the same, but the invention is not limited thereto, and the thickness T1 may be greater than, equal to, or less than the thickness T2. In addition, the formation of the first doped retention layer 170 and the second doped retention layer 210 may use the same or different processes and materials, and the positions of the first doped retention layer 170 and the second doped retention layer 210 may be adjusted.

FIG. 4 is a schematic cross-sectional view of a semiconductor device 400 according to some embodiments. In some embodiments, as shown in FIG. 4, the semiconductor device 400 further includes a two-dimensional electron gas recovery layer 410 covering the sidewall of the compound semiconductor layer 160 and extending between the source/drain 180 and the barrier layer 150, In order to restore the channel of the two-dimensional electron gas around the source/drain 180.

In some embodiments, the formation of the two-dimensional electron gas recovery layer 410 includes a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination of the foregoing. The material of the two-dimensional electron gas recovery layer 410 may include a binary compound semiconductor of hexagonal crystal, graphene, similar materials, or a combination of the foregoing. In some embodiments, the material of the two-dimensional electron gas recovery layer 410 may include aluminum nitride (AlN), zinc oxide (Zinc Oxide, ZnO), indium nitride (Indium Nitride, InN), similar materials, or a combination of the foregoing .

As mentioned above, the depth of the source/drain 180 extending to the film layer can be adjusted, so the position of the two-dimensional electron gas recovery layer 410 can also be adjusted accordingly. In addition, the two-dimensional electron gas recovery layer 410 may have an opening 420 in which a gate 190 is provided. The formation method of the opening 420 of the two-dimensional electron gas recovery layer 410 may be the formation method of the opening 220 of the second dopant-retaining layer 210 as described above, and the description will not be repeated here.

In addition, although the semiconductor device 400 is illustrated in FIG. 4 as having the first doped retention layer 170 and the two-dimensional electron gas recovery layer 410, the present invention is not limited to this. For example, only the two-dimensional electron gas recovery layer 410 may be provided.

In some embodiments, the thickness T3 of the two-dimensional electron gas recovery layer 410 is in the range of about 0.5 nm to about 5 nm, for example, about 4 nm. For ease of illustration, the thickness T1 of the first doped retention layer 170 and the thickness T3 of the two-dimensional electron gas recovery layer 610 are substantially the same, but the invention is not limited thereto, and the thickness T1 may be greater than, equal to, or less than the thickness T3. In addition, the positions of the first doped retention layer 170 and the two-dimensional electron gas recovery layer 410 are not limited to the illustrated patterns. For example, the first doped retention layer 170 may be disposed on the bottom of the compound semiconductor layer 160.

According to some embodiments of the present invention, the provision of the two-dimensional electron gas recovery layer 410 in the semiconductor device 400 can not only reduce the junction resistance (R _C ) and improve the on resistance (R _ON ), but also protect the underlying film layer from subsequent The influence of the manufacturing process improves the efficiency and yield of the semiconductor device 400.

According to some embodiments, the present invention provides one or more dopant retention layers on the top, inner, bottom and/or side walls of the compound semiconductor layer, the composition of which can form a stable alloy with the dopant, which can avoid the dopant in the compound semiconductor layer Spread outward. In addition, one or more doped retention layers can also provide protection to the area underneath, from subsequent processes such as the etching process, reduce defects and improve yield. In addition, according to some embodiments, the position of one or more doped retention layers can be adjusted to further reduce the influence of the dopants on other components, and the one or more doped retention layers provided in a specific area can also suppress leakage and improve semiconductor devices Reliability.

In addition, according to other embodiments of the present invention, a two-dimensional electron gas recovery layer is provided on the semiconductor device, which covers the sidewalls of the compound semiconductor layer and extends between the source/drain and the barrier layer to recover the source/drain The surrounding two-dimensional electron gas channel reduces the junction resistance (R _C ), thereby improving the on-resistance (R _ON ) of the semiconductor device, and at the same time provides protection for the area under the two-dimensional electron gas recovery layer.

Although the present invention has been described above with multiple embodiments, these embodiments are not intended to limit the present invention. Those of ordinary skill in the technical field to which the present invention belongs should understand that they can make various changes, substitutions, and replacements based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein And/or advantages. Those with ordinary knowledge in the technical field to which the present invention belongs can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

110‧‧‧ base

120‧‧‧Nuclear layer

130‧‧‧buffer layer

140‧‧‧channel layer

150‧‧‧ barrier layer

160‧‧‧ Compound semiconductor layer

170‧‧‧ First doping retention layer

180‧‧‧ source/drain

190‧‧‧Gate

210‧‧‧Second doped retention layer

220‧‧‧ opening

300‧‧‧Semiconductor device

T1, T2‧‧‧thickness

Claims (20)

A semiconductor device includes: a channel layer disposed above a substrate; a barrier layer disposed above the channel layer; a compound semiconductor layer and a doped retention layer disposed above the barrier layer; a pair of sources A pole/drain is disposed above the substrate and located on both sides of the compound semiconductor layer; and a gate is disposed on the compound semiconductor layer. The semiconductor device as described in item 1 of the patent application range, wherein the dopant content in the dopant holding layer is greater than the dopant content outside the dopant holding layer. The semiconductor device as described in item 1 of the patent application range, wherein the doped retention layer includes aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination of the foregoing. The semiconductor device as described in item 1 of the patent application range, wherein the thickness of the doped retention layer is in the range of 0.5 nm to 5 nm. The semiconductor device as described in item 1 of the patent application range, wherein the dopant holding layer includes: a first dopant holding layer disposed on top, inside, or bottom of the compound semiconductor layer; and/or a second dopant holding layer , Covering the sidewalls of the compound semiconductor layer and extending between the pair of source/drain and the barrier layer. The semiconductor device as described in item 5 of the patent application scope further includes the pair of source/drain electrodes passing through the barrier layer and extending into the channel layer, and the second doped retention layer is on the pair of source/ The drain electrode extends between the channel layer. The semiconductor device as described in item 5 of the patent application range, wherein the second holding layer has an opening provided on the compound semiconductor layer, and the gate is provided at the opening. The semiconductor device as described in item 1 of the patent application scope further includes a two-dimensional electron gas recovery layer covering the sidewall of the compound semiconductor layer and extending between the pair of source/drain electrodes and the barrier layer. The semiconductor device as described in item 8 of the patent application scope further includes the pair of source/drain electrodes passing through the barrier layer and extending into the channel layer, and the two-dimensional electron gas recovery layer is in the pair of source/ The drain electrode extends between the channel layer. The semiconductor device as described in item 8 of the patent application range, wherein the two-dimensional electron gas recovery layer includes a hexagonal crystal binary compound semiconductor, graphene, or a combination of the foregoing. A method for manufacturing a semiconductor device, comprising: forming a channel layer above a substrate; forming a barrier layer above the channel layer; forming a compound semiconductor layer and a doped retention layer above the barrier layer; on the substrate A pair of source/drain electrodes are formed above and on both sides of the compound semiconductor layer; and a gate electrode is formed above the compound semiconductor layer. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the formation of the dopant retention layer includes the use of organometallic chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, or a combination of the foregoing . The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the doped retention layer includes aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination of the foregoing. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the thickness of the doped retention layer is in the range of 0.5 nm to 5 nm. The method for manufacturing a semiconductor device as described in item 11 of the patent application range, wherein the formation of the dopant holding layer includes: during the formation of the compound semiconductor layer, forming a first dopant in situ on the top, inside or bottom of the compound semiconductor layer A mass-retaining layer; and/or a second dopant-retaining layer is formed on the sidewall of the compound semiconductor layer, and the second dopant-retaining layer extends between the pair of source/drain and the channel layer. The method for manufacturing a semiconductor device as described in item 15 of the patent application range, wherein the pair of source/drain electrodes further extends into the channel layer, and the second doped retention layer is between the pair of source/drain electrodes and the Channels extend between layers. The method for manufacturing a semiconductor device as described in item 15 of the patent application range, wherein the second doped retention layer has an opening formed above the compound semiconductor layer, and the gate is disposed at the opening. The method for manufacturing a semiconductor device as described in item 11 of the patent application scope further includes forming a two-dimensional electron gas recovery layer on the sidewall of the compound semiconductor layer, and the two-dimensional electron gas recovery layer is located on the pair of source/drain Between the pole and the channel layer. The method for manufacturing a semiconductor device as described in item 18 of the patent application range, wherein the pair of source/drain electrodes further passes through the barrier layer and extends into the channel layer, and the two-dimensional electron gas recovery layer is in the pair The source/drain extends between the channel layer. The method for manufacturing a semiconductor device as described in item 18 of the patent application range, wherein the two-dimensional electron gas recovery layer includes a hexagonal crystal (hexagonal crystal) binary compound semiconductor, graphene (graphene) or a combination of the foregoing.

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