TWI676293B - Semiconductor devices and methods for forming same - Google Patents

Abstract

A semiconductor device includes a channel layer disposed above a substrate; a barrier layer disposed above the channel layer; a compound semiconductor layer disposed above the barrier layer; a pair of source / drain electrodes disposed above the substrate and located respectively Both sides of the compound semiconductor layer; a fluorinated region is provided in the compound semiconductor layer; and a gate electrode is provided on the compound semiconductor layer.

Description

Semiconductor device and manufacturing method thereof

Embodiments of the present invention relate to semiconductor manufacturing technologies, and in particular, to semiconductor devices and manufacturing methods thereof.

High electron mobility transistor (HEMT), also known as heterostructure FET (HFET) or modulation-doped FET (MODFET), is a kind of Field effect transistor (FET), which is composed of semiconductor materials with different energy gaps. A two-dimensional electron gas (2 DEG) layer is generated near the formed interface adjacent to different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor can have advantages such as high breakdown voltage, high electron mobility, low on-resistance, and low input capacitance, and is therefore suitable for high power components.

However, although the existing high-electron mobility transistors generally meet the requirements, they are not satisfactory in every aspect, and further improvements are needed to improve performance and have wider applications.

According to some embodiments of the present invention, a semiconductor device is provided. this The semiconductor device includes a channel layer disposed above the substrate; a barrier layer disposed above the channel layer; a compound semiconductor layer disposed above the barrier layer; a pair of source / drain electrodes disposed above the substrate and respectively located on the compound semiconductor layer Two sides; a fluorinated region provided in the compound semiconductor layer; and a gate electrode provided on the compound semiconductor layer.

In some embodiments, the fluorinated region extends from the top of the compound semiconductor layer into the barrier layer.

In some embodiments, the semiconductor device further includes a fluorinated region disposed in a barrier layer around the compound semiconductor layer.

In some embodiments, the semiconductor device further includes a first fluorine holding layer disposed on the top, inside or bottom of the compound semiconductor layer; and / or a second fluorine holding layer covering a sidewall of the compound semiconductor layer and extending to the pair of source / Between the drain and the barrier layer.

In some embodiments, the pair of source / drain electrodes pass through the barrier layer and extend into the channel layer, and the second fluorine retention layer is further disposed between the pair of source / drain electrodes and the channel layer.

In some embodiments, the fluorine content in the first fluorine-retaining layer and the second fluorine-retaining layer is greater than the fluorine content outside the first fluorine-retaining layer and the second fluorine-retaining layer.

In some embodiments, the second fluorine-retaining layer has an opening, the area of the opening is smaller than or equal to the area of the fluorinated region on the top of the compound semiconductor layer, and the gate is disposed in the opening.

In some embodiments, the first fluorine-retaining layer and the second fluorine-retaining layer each independently include aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination thereof. Together.

In some embodiments, the thickness of the first fluorine-retaining layer and the thickness of the second fluorine-retaining layer are each independently in a range of 0.5 nm to 5 nm.

In some embodiments, the semiconductor device further includes a two-dimensional electron gas recovery layer covering the sidewall of the compound semiconductor layer and extending between the pair of source / drain and the barrier layer.

According to other embodiments of the present invention, a method for manufacturing a semiconductor device is provided. This method includes forming a channel layer over a substrate; forming a barrier layer over the channel layer; forming a compound semiconductor layer over the barrier layer; forming a pair of source / drain electrodes over the substrate and on both sides of the compound semiconductor layer; in Introducing fluorine into the compound semiconductor layer; and forming a gate electrode over the compound semiconductor layer.

In some embodiments, the introduction of fluorine includes the use of etching equipment.

In some embodiments, the introduction of fluorine includes using reactive ion etching, inductively coupled plasma etching, or a combination thereof.

In some embodiments, the range of fluorine introduction extends from the top of the compound semiconductor layer into the barrier layer.

In some embodiments, the method of manufacturing a semiconductor device further includes performing a first heat treatment after the fluorine is introduced and before the gate is formed.

In some embodiments, the method for manufacturing a semiconductor device further includes performing a second heat treatment after forming the gate.

In some embodiments, the method for manufacturing a semiconductor device further includes introducing fluorine into the barrier layer surrounding the compound semiconductor layer.

In some embodiments, the resistance of fluorine around the compound semiconductor layer The introduction of the barrier layer includes using a temperature increasing device, an etching device, or a combination thereof.

In some embodiments, the method for manufacturing a semiconductor device further includes forming the first fluorine-retaining layer in situ during the formation of the compound semiconductor layer; and / or after the compound semiconductor layer is formed and before the gate electrode is formed, A second fluorine holding layer is formed on the sidewall, and the second fluorine holding layer extends between the pair of source / drain and the channel layer.

In some embodiments, the method for manufacturing a semiconductor device further includes the pair of source / drain electrodes passing through the barrier layer and extending into the channel layer, and the second fluorine retention layer extending to the pair of source / drain electrodes and the barrier Between layers.

In some embodiments, the method for manufacturing a semiconductor device further includes forming an opening of the second fluorine holding layer above the compound semiconductor layer, introducing fluorine from the opening, and forming a gate at the opening.

In some embodiments, the method for manufacturing a semiconductor device further includes forming a two-dimensional electron gas recovery layer on a sidewall of the compound semiconductor layer, and the two-dimensional electron gas recovery layer extends between the pair of source / drain electrodes and the channel layer.

100, 200, 300, 400, 500, 600‧‧‧ semiconductor devices

110‧‧‧ substrate

120‧‧‧nucleation layer

130‧‧‧ buffer layer

140‧‧‧channel layer

150‧‧‧ barrier layer

160, 160a‧‧‧ compound semiconductor layer

170‧‧‧Source / Drain

180, 180 ’‧‧‧ fluoride zone

190‧‧‧Gate

310‧‧‧First fluorine holding layer

410‧‧‧Second fluorine retention layer

420‧‧‧ opening

610‧‧‧Two-dimensional electron gas recovery layer

T1, T2, T3‧‧‧thickness

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, according to industry standard practices, various features are not drawn to scale and are used for illustration only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the features of the present disclosure.

1A-1F are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device according to some embodiments.

FIG. 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

FIG. 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

4A-4D are schematic cross-sectional views illustrating various stages of manufacturing a semiconductor device according to some embodiments.

FIG. 5 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

FIG. 6 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

Some embodiments are summarized below so that those skilled in the art to which the present invention pertains can more easily understand the present invention. However, these examples are only examples and are not intended to limit the present invention. It can be understood that those with ordinary knowledge in the technical field to which the present invention pertains can adjust the embodiments described below, such as changing the process sequence and / or including more or fewer steps than those described herein.

In addition, other elements may be added to the embodiments described below. For example, the description of "forming a second element on a first element" may include an embodiment in which the first element is in direct contact with the second element, or may include other elements between the first element and the second element such that the first An embodiment in which one element is not in direct contact with the second element, and the up-down relationship between the first element and the second element may change as the device is operated or used in different orientations.

The following describes a semiconductor device and a manufacturing method thereof according to some embodiments of the present invention, and is particularly suitable for a high electron mobility transistor (HEMT). The present invention introduces fluorine into a compound semiconductor layer of a semiconductor device to form a fluorinated region to raise the surface potential and change the energy band, thereby improving threshold voltage (Vth) and gate swing.

1A-1F are schematic cross-sectional views illustrating various stages of manufacturing the semiconductor device 100 according to some embodiments. As shown in Figure 1A, the semiconductor device The device 100 includes a substrate 110. Any base material suitable for a semiconductor device can be used. The substrate 110 may be a bulk semiconductor substrate or a composite substrate including different materials, and the substrate 110 may be doped (eg, using a p-type or n-type dopant) or undoped. In some embodiments, the substrate 110 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire substrate. ) Substrate, a combination of the foregoing, or similar materials. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) substrate, which is formed by disposing a semiconductor material on an insulating layer.

In some embodiments, a nucleation layer 120 is formed above the substrate 110 to alleviate the lattice difference between the substrate 110 and the film layer grown above, and improve the crystal quality. The formation of the nucleation layer 120 may include a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), and Molecular Beam Epitaxy (MBE). , Liquid Phase Epitaxy (LPE), a similar process or a combination of the foregoing. In some embodiments, the thickness of the nucleation layer 120 may be in a range of about 1 nanometer (nm) to about 500 nm, such as about 200 nm.

In some embodiments, a buffer layer 130 is formed above the nucleation layer 120 to alleviate lattice differences between different film layers and improve crystal quality. The nucleation layer 120 is selective. In other embodiments, the core layer 120 may not be provided, and the buffer layer 130 may be formed directly on the substrate, and the improvement of the process may be achieved by reducing the process steps. In some embodiments, the material of the buffer layer 130 may include Group III-V compound semiconductor materials, such as group III nitrides. For example, the material of the buffer layer 130 may include Gallium Nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), similar materials, or the foregoing combination. In some embodiments, the formation of the buffer layer 130 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination thereof.

A channel layer 140 is then formed over the buffer layer 130. In some embodiments, the material of the channel layer 140 may include one or more group III-V compound semiconductor materials, such as a group III nitride. In some embodiments, the material of the channel layer 140 is, for example, GaN, AlGaN, InGaN, InAlGaN, a similar material, or a combination thereof. In addition, the channel layer 140 may be doped or undoped. According to some embodiments, the formation of the channel layer 140 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination thereof. In some embodiments, the thickness of the channel layer 140 is in a range between about 0.05 micrometers (μm) and about 1 μm, such as about 0.2 μm.

A barrier layer 150 is then formed over the channel layer 140 to generate a two-dimensional electron gas at the interface between the channel layer 140 and the barrier layer 150. The formation of the barrier layer 150 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination thereof. In some embodiments, the material of the barrier layer 150 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 150 may include AlN, AlGaN, AlInN, AlGaInN, similar materials, or a combination thereof. The barrier layer 150 may include a single-layer or multi-layer structure, and the barrier layer 150 may Doped or undoped. In some embodiments, the thickness of the barrier layer 150 may be in a range between about 1 nm and about 30 nm, such as about 20 nm.

Next, as shown in FIG. 1B, according to some embodiments, a compound semiconductor layer 160 is provided above the barrier layer 150 to achieve a normally-off state of the semiconductor device with a two-dimensional electron gas under the empty gate. In some embodiments, the compound semiconductor layer 160 includes u-type, n-type, or p-type doped gallium nitride. The formation of the compound semiconductor layer 160 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination thereof. In some embodiments, the thickness of the compound semiconductor layer 160 may be in a range between about 30 nm and about 150 nm, such as about 80 nm.

Next, as shown in FIG. 1C, according to some embodiments, a patterned masking layer (not shown) is formed on the compound semiconductor layer 160, and then the compound semiconductor layer 160 is etched to remove the compound semiconductor layer 160 without being patterned. A portion covered by the mask layer forms the compound semiconductor layer 160a. The position of the compound semiconductor layer 160a is adjusted in accordance with a position where a gate electrode is predetermined to be provided.

In some embodiments, the patterned masking layer may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned masking layer may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride carbide, similar materials, or a combination thereof. In some embodiments, the formation of the patterned masking layer may include spin-on coating, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), similar Process or a combination of the foregoing.

In some embodiments, the etching of the compound semiconductor layer 160 may use a dry etching process, a wet etching process, or a combination thereof. For example, the etching of the compound semiconductor layer 160 includes Reactive Ion Etch (RIE), Inductively-Coupled Plasma (ICP) etching, Neutron Beam Etch (NBE), Electron Cyclotron Resonance (ERC) etching, similar etching process, or a combination of the foregoing. In addition, although the compound semiconductor layer 160a has a substantially vertical sidewall and a flat upper surface in the figure, the present invention is not limited thereto, and the compound semiconductor layer 160a may have other shapes, such as an inclined sidewall and / or an uneven top surface. surface.

Next, as shown in FIG. 1D, according to some embodiments, a pair of source / drain electrodes 170 is disposed above the substrate, and the pair of source / drain electrodes 170 are located on both sides of the compound semiconductor layer 160 a, respectively. In some embodiments, the formation of the source / drain 170 pair includes performing a patterning process to etch the barrier layer 150 and the channel layer 140 on both sides of the compound semiconductor layer 160a to form a barrier layer 150 and Extending to a pair of recesses in the channel layer 140, a conductive material is deposited on the recesses, and a patterning process is performed on the deposited conductive materials to form the pair of source / drain electrodes 170.

In some embodiments, the deposition process of the conductive material may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or a combination thereof. In some embodiments, the conductive material may include a metal, a metal silicide, a semiconductor material, a similar material, or a combination of the foregoing. For example, the metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al) ),copper (Cu), titanium nitride (TiN), similar materials, the foregoing alloy, the foregoing multilayer structure, or a combination thereof, and the semiconductor material may include polycrystalline silicon or polycrystalline germanium. In addition, the shape of the pair of source / drain electrodes 170 is not limited to the vertical sidewalls in the drawings, and may be a tapered sidewall or have other contours.

Although in the embodiment shown in FIG. 1D, the pair of source / drain 170 is located on the barrier layer 150 and extends into the barrier layer 150 and the channel layer 140, the present invention is not limited thereto, and may be selected according to The process and equipment adjust the depth of the source / drain 170 extension. For example, the pair of source / drain electrodes 170 may also extend into part of the barrier layer 150 or not extend into the barrier layer 150 to prevent the pair of source / drain electrodes 170 from passing through the two-dimensional electron gas. Thus, the two-dimensional electron gas at the interface between the channel layer 140 and the barrier layer 150 is maintained.

Then, as shown in FIG. 1E, fluorine is introduced into the compound semiconductor layer 160 a to form a fluorinated region 180. The present invention introduces fluorine into the compound semiconductor layer 160a to form a fluorinated region 180, which can raise the surface potential and change the energy band. The increase of the surface potential can increase the work function of the gate metal contact, thereby improving the threshold voltage (Vth) and the gate swing. In addition, for n-type or p-type doped gallium nitride compound semiconductor layer 160a, since the introduced fluorine does not affect the conductivity type, a pn junction is not formed in the compound semiconductor layer 160a, which is beneficial to semiconductor devices. 100 switching performance. In addition, the bonding of fluorine ions in gallium nitride will increase the energy band distribution, which has the effect of vacant two-dimensional electron gas, and can also achieve the effect of increasing the threshold voltage.

In some embodiments, the formation of the fluorinated region 180 may include using a mask (not shown) to expose a portion of the compound semiconductor layer 160a, and then introducing fluorine to the exposed portion of the compound semiconductor layer 160a. The shape of the mask will determine the fluorine The extent of the area 180. In some embodiments, the mask may substantially cover a region other than the compound semiconductor layer 160a to form a uniform concentration of fluorine within the compound semiconductor layer 160a. In other embodiments, the mask may be meshed to divide the introduction of fluorine into a plurality of separate parts, to form a plurality of higher concentration parts in the compound semiconductor layer 160a, to avoid the fluorinated region 180 The fluorine content is too high.

In some embodiments, the fluorine may be introduced using an etching apparatus. In some embodiments, the etching equipment may include, for example, reactive ion etching (RIE), inductively coupled plasma etching (ICP), similar equipment, or a combination of the foregoing. The fluorine source may be Tetrafluoromethane (CF ₄ ), Trifluoromethane (CHF ₃ ), Sulfur hexafluoride (SF ₆ ), similar materials, or a combination thereof. In some embodiments, the amount of fluorine introduced is in a range between about 1 × 10 ¹² atoms / cm ² and about 5 × 10 ¹⁵ atoms / cm 2, for example, about 5 × 10 ¹⁴ atoms / The range between cm 2 and about 1 × 10 ¹⁵ atoms / cm 2 can improve the threshold voltage and minimize the possible impact on surrounding components.

In the embodiment where the etching equipment is used to introduce fluorine, since the etching equipment can achieve a relatively low ion acceleration voltage relative to the ion implantation, the bombardment damage to the element can be reduced, and a more stable ion concentration and distribution can be achieved.

The fluorinated region 180 is then optionally subjected to a heat treatment, such as a Rapid Thermal Process (RTP), to control the distribution of fluorine. The heat treatment in this step can repair the surface of the element bombarded by fluoride ions, and at the same time redistribute the fluoride ions to a stable value in the element, and improve the operating performance of the element And reliability. In some embodiments, the temperature of the heat treatment is in a range between about 300 ° C and about 500 ° C, and the time is in a range between about 5 minutes and about 15 minutes.

Although the fluorinated region 180 extends from the top of the compound semiconductor layer 160 a into the barrier layer 150 in the illustrated example, the present invention is not limited thereto. In some embodiments, the fluorinated region 180 can be further extended from the top of the compound semiconductor layer 160a into the channel layer 140, for example, by adjusting the parameters of the heat treatment or increasing the power of introducing fluorine. In other embodiments, the fluorinated region 180 may also be located only in the compound semiconductor layer 160 a and does not extend into the barrier layer 150 to adjust the threshold voltage (Vth).

Next, as shown in FIG. 1F, a gate electrode 190 is provided above the compound semiconductor layer 160 a to form a semiconductor device 100. In some embodiments, the formation of the gate electrode 190 includes depositing a conductive material over the compound semiconductor layer 160a, and then performing a patterning process on the deposited conductive material to form the gate electrode 190.

In some embodiments, the deposition process and the material of the conductive material may be the deposition process and the material of the conductive material forming the source / drain 170 as described above, which will not be repeated here, and the source / drain 170 and The formation of the gate 190 may independently include the same or different processes and materials. In addition, although it is described herein that the gate 190 is formed after the source / drain 170 is formed, the present invention is not limited thereto. For example, the source / drain 170 and the gate 190 may be formed in the same step.

In addition, the shape of the gate electrode 190 is not limited to the vertical sidewall in the figure, and may be an inclined sidewall or have other shapes. Although in the embodiment shown in FIG. 1F, the bottom surface of the gate electrode 190 and the top surface of the fluorinated region 180 are substantially They have the same area, but the present invention is not limited to this. The bottom surface of the gate electrode 190 may also be larger or smaller than the top surface of the fluorinated region 180.

A heat treatment, such as a Rapid Thermal Process (RTP), may then be performed to adjust the distribution of the fluorinated regions 180 and improve the contact characteristics of the gate metal. In some embodiments, the temperature of the heat treatment is in a range between about 300 ° C and about 400 ° C, and the time is in a range between about 5 minutes and about 10 minutes.

Although it is described herein that the heat treatment is performed twice, one or more heat treatments may be performed according to a predetermined distribution range of the fluorinated region 180 and a stability control ability of fluorine ion implantation. In some embodiments, only the heat treatment after the gate formation is performed, and the heat treatment before the gate formation is not performed to reduce the process steps. In other embodiments, a heat treatment may be performed once before and after the gate is formed to better control the distribution range of the fluorinated region 180.

FIG. 2 is a schematic cross-sectional view of a semiconductor device 200 according to some embodiments. In some embodiments, as shown in FIG. 2, the fluorinated regions 180 may be further distributed in the barrier layer 150 around the compound semiconductor layer 160 a to form fluorinated regions 180 ′ to suppress leakage.

In some embodiments, the formation of the fluorinated region 180 ′ may be that the method and the fluorine source for forming the fluorinated region 180 described above are used again after forming the fluorinated region 180 to introduce fluorine into the compound semiconductor layer 160 a. Around the barrier layer 150. Alternatively, in other embodiments, a mask that exposes the compound semiconductor layer 160a and the surrounding barrier layer 150 may be used to form the fluorinated region 180 'in the same step. Alternatively, in still other embodiments, the one or more heat treatments described above can be controlled to diffuse the fluorine in the fluorinated region 180 into the barrier layer 150. Forming a fluorinated region 180 'without introducing additional fluorine, reducing process steps and costs, and increasing productivity.

In the semiconductor device 200 shown in FIG. 2, a fluorinated region 180 ′ is provided in the barrier layer 150 around the compound semiconductor layer 160 a, which can suppress leakage and improve the yield of the semiconductor device 200.

FIG. 3 is a schematic cross-sectional view of a semiconductor device 300 according to some embodiments. In some embodiments, as shown in FIG. 3, a first fluorine-retaining layer 310 may be provided in the compound semiconductor layer 160 a to form a stable compound with the fluorine in the fluorinated region 180 to prevent fluorine from diffusing outward and affecting other element. The material of the first fluorine-retaining layer 310 may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (AlInN), a similar material, or a combination thereof. These materials may form fluorine with the introduced fluorine. Aluminium Fluoride (AlF). Since the formed aluminum fluoride is stable under the heat treatment of the subsequent process, the thermal stability of the fluoride region 180 can be increased. Therefore, the fluorine content in the first fluorine-retaining layer 310 is larger than the fluorine content outside the first fluorine-retaining layer 310.

In some embodiments, the formation of the first fluorine-retaining layer 310 may include a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination thereof. The first fluorine holding layer 310 may be formed in situ during the formation of the compound semiconductor layer 160a. Although the first fluorine-retaining layer 310 is located inside the compound semiconductor layer 160a in the illustrated embodiment, the present invention is not limited thereto. In some embodiments, the first fluorine-retaining layer 310 may also be disposed on the top or bottom of the compound semiconductor layer 160a. In some embodiments, the thickness T1 of the first fluorine-retaining layer 310 is in a range of about 0.5 nm to about 5 nm, such as about 4 nm.

According to some embodiments of the present invention, the first fluorine-retaining layer 310 is provided on the compound semiconductor layer 160a. In addition to improving the thermal stability of the fluorine, preventing the fluorine from diffusing outward, it can also protect the area below it, and prevent subsequent processes from affecting the underlying Area, improving the yield of the semiconductor device 300.

4A-4D are schematic cross-sectional views illustrating various stages of manufacturing the semiconductor device 400 according to some embodiments. FIG. 4A is a continuation of the description of FIG. 1C, and the same elements are described with the same symbols, and the formation methods and materials of these elements are as described above, and are not repeated here.

In some embodiments, as shown in FIG. 4A, a second fluorine-retaining layer 410 may be provided to cover the sidewall of the compound semiconductor layer 160 a and extend between the pair of source / drain 170 and barrier layer 150 to avoid fluorine. Diffusion and protect the components below it. In some embodiments, the formation and material of the second fluorine-retaining layer 410 may be selected from the processes and materials of the first fluorine-retaining layer 310 described above. In some embodiments, the thickness T2 of the second fluorine-retaining layer 410 ranges from about 0.5 nm to about 5 nm, such as about 4 nm.

As described above, the depth at which the pair of source / drain electrodes 170 extend to the film layer can be adjusted, so the position of the second fluorine-retaining layer 410 can also be adjusted accordingly. For example, in some embodiments, for the case where the pair of source / drain 170 extends only partially into the barrier layer 150, or does not extend into the barrier layer 150, the second fluorine retention layer 410 is provided to extend to The pair of source / drain 170 and barrier layer 150. On the other hand, for the case where the pair of source / drain 170 further extends into the channel layer 140, the second fluorine holding layer 410 is further disposed between the pair of source / drain 170 and the channel layer 140.

Then, as shown in FIG. 4B, a second fluorine-retaining layer 410 is formed. The opening 420 is located above the compound semiconductor layer 160a. The position of the opening 420 is adjusted according to the position where the gate electrode is predetermined. In some embodiments, the opening 420 may be formed using a patterned masking layer (not shown), and a portion of the second fluorine-retaining layer 410 exposed by the patterned masking layer is etched to remove this portion of the second fluorine. Holding layer 410. The materials and methods for forming the patterned masking layer are as described above, and are not repeated here.

In some embodiments, the etching of the second fluorine-retaining layer 410 may use a dry etching process, a wet etching process, or a combination thereof. For example, the etching of the second fluorine holding layer 410 includes reactive ion etching (RIE), inductively coupled plasma (ICP) etching, neutron beam etching (NBE), electron cyclotron resonance (ERC) etching, and the like Etching process or a combination of the foregoing.

Next, as shown in FIG. 4C, fluorine is introduced from the opening 420 to form a fluorinated region 180. The fluorinated region 180 can be formed using the processes and materials described above, and after the fluorinated region 180 is formed, a heat treatment can be selectively performed, and as shown in FIG. The fluorinated region 180 ′ of the barrier layer 150. In addition, since fluorine is introduced from the opening 420, the area of the opening 420 is substantially smaller than or equal to the top area of the compound semiconductor layer 160a of the fluorinated region 180/180 '. In addition, fluorine can be introduced using the same patterned mask layer as the opening 420 to reduce the number of process steps.

Next, as shown in FIG. 4D, a gate electrode 190 is provided in the opening 420 above the compound semiconductor layer 160 a to form a semiconductor device 400. The materials and processes for forming the gate electrode 190 are as described above, and are not repeated here. The gate electrode 190 can be formed using the same patterned mask layer as the opening 420 to reduce the number of process steps. In addition, although it is described herein that the gate 190 is formed after the source / drain 170 is formed, The invention is not limited to this. For example, the source / drain 170 and the gate 190 may be formed simultaneously.

Although in the embodiment shown in FIG. 4D, the bottom surface of the opening 420 and the gate electrode 190 and the top surface of the fluorinated region 180 have substantially the same area, the present invention is not limited thereto. In addition, the gate electrode 190 is not limited to the vertical sidewall shown in the figure, and the gate electrode 190 may have an inclined sidewall or a stepped sidewall of the second fluorine-retaining layer 410 covering the portion.

The semiconductor device 400 may then be subjected to a heat treatment, such as a rapid heat treatment, to adjust the range of the fluorinated region 180. The temperature, time and number of heat treatments are as described above, and will not be repeated here.

According to some embodiments of the present invention, a second fluorine-retaining layer 410 is provided on the semiconductor device 400 to cover the sidewall of the compound semiconductor layer 160a and extends between the pair of source / drain 170 and the barrier layer 150, except that it can be formed with fluorine. The stable compound improves the thermal stability of the fluorinated region 180 to prevent the fluorine in this region from diffusing outward. It can also protect the region below it during subsequent processes and improve the yield of the semiconductor device 400.

FIG. 5 is a schematic cross-sectional view of a semiconductor device 500 according to some embodiments. In some embodiments, as shown in FIG. 5, the first fluorine-retaining layer 310 and the second fluorine-retaining layer 410 may be provided at the same time to further improve the thermal stability of the fluorine-retaining layer 180 and more completely protect the first fluorine-retaining layer. The area under the layer 310 and the second fluorine-retaining layer 410 improves the yield of the semiconductor device 500. The positions, materials, and processes of the first fluorine-retaining layer 310 and the second fluorine-retaining layer 410 are as described above, and the description is not repeated here.

For the convenience of illustration, the thickness T1 and The thickness T2 of the difluoride-retaining layer 410 is substantially the same, but the present invention is not limited thereto, and the thickness T1 may be greater than, equal to, or less than the thickness T2. In addition, the first fluorine-retaining layer 310 and the second fluorine-retaining layer 410 can be formed using the same or different processes and materials, and the positions of the first fluorine-retaining layer 310 and the second fluorine-retaining layer 410 can also be adjusted.

FIG. 6 is a schematic cross-sectional view of a semiconductor device 600 according to some embodiments. In some embodiments, as shown in FIG. 6, the semiconductor device 600 further includes a two-dimensional electron gas recovery layer 610 covering the sidewall of the compound semiconductor layer 160 a and extending to the source / drain 170 and the barrier layer 150. In order to restore the two-dimensional electron gas channel around the source / drain 170.

In some embodiments, the formation of the two-dimensional electron gas recovery layer 610 includes a deposition process, such as organic metal chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, a similar process, or a combination thereof. The material of the two-dimensional electron gas recovery layer 610 may include a binary compound semiconductor of hexagonal crystal, graphene, a similar material, or a combination thereof. In some embodiments, the material of the two-dimensional electron gas recovery layer 610 includes aluminum nitride (AlN), zinc oxide (ZnO), indium nitride (Indium Nitride, InN), a similar material, or a combination thereof.

As described above, the depth at which the pair of source / drain electrodes 170 extend to the film layer can be adjusted, so the position of the two-dimensional electron gas recovery layer 610 can also be set according to requirements. In addition, the two-dimensional electron gas recovery layer 610 may have an opening in which the gate electrode 190 is provided, and fluorine is introduced from the opening, so the area of the opening is substantially smaller than or equal to the top area of the fluorinated region 180 on the compound semiconductor layer 160a. The method of forming the opening and the process of introducing fluorine are as described above, and will not be repeated here.

In addition, although the semiconductor device 600 is shown in FIG. 6 with the first fluorine holding layer 310 and the two-dimensional electron gas recovery layer 610, the present invention is not limited thereto. For example, only the two-dimensional electron gas recovery layer 610 may be provided.

In some embodiments, the thickness T3 of the two-dimensional electron gas recovery layer 610 ranges from about 0.5 nm to about 5 nm, such as about 4 nm. For ease of illustration, the thickness T1 of the first fluorine-retaining layer 310 and the thickness T3 of the two-dimensional electron gas recovery layer 610 are substantially the same, but the present invention is not limited thereto, and the thickness T1 may be greater than, equal to, or less than the thickness T3. In addition, the positions of the first fluorine-retaining layer 310 and the two-dimensional electron gas recovery layer 610 are not limited to the illustrations. For example, the first fluorine-retaining layer 310 may be provided on the bottom of the compound semiconductor layer 160a.

According to some embodiments of the present invention, in the two-dimensional electron gas 600 is provided a semiconductor device reply layer 610, in addition to reducing the surface resistance (R _C), to improve the on-resistance (R _ON), the protective layer may also not be below the subsequent The impact of the manufacturing process improves the efficiency and yield of the semiconductor device 600.

According to some embodiments, the present invention introduces fluorine into a compound semiconductor layer of a semiconductor device to form a fluorinated region in the compound semiconductor layer, which can raise the surface potential and change the energy band, thereby improving the threshold voltage and gate swing of the semiconductor device. Since the introduced fluorine does not form a p-n junction with the compound semiconductor layer, it is beneficial to the switching performance of the semiconductor device. In addition, by adjusting the distribution and content of fluorine, for example, fluorine can be allowed to enter the barrier layer around the compound semiconductor to suppress leakage. In addition, the use of etching equipment to introduce fluorine can reduce the damage to the element and achieve a more stable ion concentration and distribution.

According to other embodiments, a fluorine retention layer is provided on the top, the inside, the bottom and / or the sidewall of the compound semiconductor layer according to the present invention, which can prevent the fluorine in the fluorinated region from diffusing outward, and can also avoid the subsequent process from affecting the area within the fluorine retention layer To improve the yield of semiconductor devices. In addition, according to still other embodiments, a two-dimensional electron gas recovery layer is provided to cover the sidewall of the compound semiconductor layer and extends between the source / drain and the barrier layer, so as to recover the two-dimensional electron gas around the source / drain. the channels to reduce junction resistance (R _C), and to improve the on-resistance (R _oN), but also protect the area thereunder.

Although the present invention has been described above with a plurality of embodiments, these embodiments are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains should understand that they can make various changes, substitutions and replacements based on the embodiments of the present invention to achieve the same purpose as the multiple embodiments described herein. And / or advantages. Those skilled in the art to which the present invention pertains can also understand that such modifications or designs do not depart from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (22)

A semiconductor device includes: a channel layer disposed above a substrate; a barrier layer disposed above the channel layer; a compound semiconductor layer disposed above the barrier layer; a pair of source / drain electrodes, disposed Above the substrate and located on both sides of the compound semiconductor layer; a fluorinated region disposed in the compound semiconductor layer; a first fluorine retention layer disposed on the top, inside or bottom of the compound semiconductor layer; A pole is provided on the compound semiconductor layer. The semiconductor device according to item 1 of the application, wherein the fluorinated region extends from a top of the compound semiconductor layer into the barrier layer. According to the semiconductor device described in item 1 of the patent application scope, the fluorinated region is further disposed in the barrier layer around the compound semiconductor layer. The semiconductor device according to item 1 of the patent application scope further includes a second fluorine-retaining layer covering a sidewall of the compound semiconductor layer and extending between the pair of source / drain electrodes and the barrier layer. The semiconductor device according to item 4 of the application, wherein the pair of source / drain electrodes pass through the barrier layer and extend into the channel layer, and the second fluorine holding layer is further disposed on the pair of source / drain electrodes. Between the drain and the channel layer. The semiconductor device according to item 4 of the application, wherein the fluorine content in the first fluorine-retaining layer and the second fluorine-retaining layer is greater than the fluorine in the first fluorine-retaining layer and the second fluorine-retaining layer. content. The semiconductor device according to item 4 of the scope of patent application, wherein the second fluorine-retaining layer has an opening, an area of the opening is smaller than or equal to an area of the fluorinated region on the top of the compound semiconductor layer, and the gate electrode Set in the opening. The semiconductor device according to item 4 of the scope of patent application, wherein the first fluorine-retaining layer and the second fluorine-retaining layer each independently include aluminum nitride, aluminum gallium nitride, indium gallium nitride, or a combination thereof. The semiconductor device according to item 4 of the scope of patent application, wherein the thickness of the first fluorine-retaining layer and the thickness of the second fluorine-retaining layer are each independently in a range of 0.5 nm to 5 nm. The semiconductor device according to item 1 of the patent application scope further includes a two-dimensional electron gas recovery layer covering the sidewall of the compound semiconductor layer and extending between the pair of source / drain electrodes and the barrier layer. A method for manufacturing a semiconductor device includes: forming a channel layer over a substrate; forming a barrier layer over the channel layer; forming a compound semiconductor layer over the barrier layer; during the formation of the compound semiconductor layer, Forming a first fluorine retention layer; forming a pair of source / drain electrodes above the substrate and on both sides of the compound semiconductor layer; introducing fluorine into the compound semiconductor layer; and forming a gate above the compound semiconductor layer pole. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, wherein the introduction of the fluorine includes using an etching device. The method for manufacturing a semiconductor device according to item 11 of the application, wherein the introduction of fluorine includes using reactive ion etching, inductively coupled plasma etching, or a combination thereof. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, wherein the range for introducing the fluorine extends from a top of the compound semiconductor layer into the barrier layer. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further includes performing a first heat treatment after introducing the fluorine and before forming the gate electrode. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising performing a second heat treatment after forming the gate electrode. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising introducing the fluorine into the barrier layer around the compound semiconductor layer. The method for manufacturing a semiconductor device according to item 17 of the scope of patent application, wherein the introduction of the barrier layer of the fluorine around the compound semiconductor layer includes using a temperature rising device, an etching device, or a combination thereof. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising: after forming the compound semiconductor layer and before forming the gate electrode, forming a second fluorine holding layer on a sidewall of the compound semiconductor layer, And the second fluorine holding layer extends between the pair of source / drain electrodes and the channel layer. The method for manufacturing a semiconductor device according to item 19 of the scope of patent application, further comprising the pair of source / drain electrodes passing through the barrier layer and extending into the channel layer, and the second fluorine-retaining layer extending to the pair Between the source / drain and the barrier layer. The method for manufacturing a semiconductor device according to item 19 of the scope of patent application, further comprising: forming an opening of the second fluorine-retaining layer above the compound semiconductor layer, introducing the fluorine through the opening; and forming the opening at the opening. Gate. The method for manufacturing a semiconductor device according to item 11 of the scope of patent application, further comprising forming a two-dimensional electron gas recovery layer on the sidewall of the compound semiconductor layer, and the two-dimensional electron gas recovery layer extends to the pair of source / Between the drain and the channel layer.