CN111987141A

CN111987141A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN111987141A
Application number: CN201910427485.5A
Authority: CN
Inventors: 吴俊仪; 陈志谚; 洪章响; 黄嘉庆
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp; Vanguard International Semiconductor America
Priority date: 2019-05-22
Filing date: 2019-05-22
Publication date: 2020-11-24

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on both sides of the gate electrode. The source electrode and the drain electrode pass through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through the source contact, wherein the source field plate has an edge. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge. The invention can increase the breakdown voltage of the semiconductor device, thereby improving the reliability of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

A High Electron Mobility Transistor (HEMT), also known as a Heterostructure Field Effect Transistor (HFET) or a modulation-doped field effect transistor (MODFET), is a Field Effect Transistor (FET) composed of semiconductor materials with different energy gaps (energy gaps). A two-dimensional electron gas (2 DEG) layer is created adjacent to the formed interface of the different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, the high electron mobility transistor has the advantages of high breakdown voltage, high electron mobility, low on-resistance, low input capacitance and the like, and is suitable for high-power elements.

A field plate (field plate) is generally disposed in a high electric field region of a semiconductor device, which serves to reduce a peak electric field (peak electric field) of the high electric field region. One of the field plates is a field plate connected to the gate (i.e., a gate field plate), which can reduce the electric field strength of the gate on the drain side. Therefore, the gate field plate can increase the breakdown voltage (breakdown voltage) of the semiconductor device, allowing the semiconductor device to be applied to high voltage operation. Another type of field plate is a field plate connected to the source electrode (i.e., a source field plate), which can reduce the gate-to-drain capacitance (Cgd) because the voltage of the source field plate can be independent of the voltage of the gate. Therefore, the source field plate can improve the operation speed of the semiconductor device. However, the trigger cause for the breakdown of the semiconductor device still remains.

Thus, while existing high electron mobility transistors are generally desirable for their intended purposes, they are not entirely satisfactory in all respects. How to effectively solve the influence of high electric field on the reliability of the element is the key point of the current technical development.

Disclosure of Invention

The embodiment of the invention provides a semiconductor device. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on both sides of the gate electrode. The source and drain electrodes extend through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through the source contact, wherein the source field plate has an edge. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge.

The embodiment of the invention provides a manufacturing method of a semiconductor device. The method includes forming a channel layer over a substrate, forming a barrier layer over the channel layer, forming a compound semiconductor layer over the barrier layer, forming a gate electrode over the compound semiconductor layer, forming a source electrode and a drain electrode on both sides of the gate electrode, and forming a source field plate, wherein the source field plate is connected to the source electrode through a source contact. The source and drain electrodes extend through at least a portion of the barrier layer. The source field plate has an edge near the drain electrode, and the first electric field redistribution pattern is located directly below the edge.

The invention can increase the breakdown voltage of the semiconductor device, thereby improving the reliability of the semiconductor device.

The following embodiments and the accompanying reference drawings will provide detailed descriptions.

Drawings

Some embodiments of the invention will be described in detail below with reference to the attached drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the present invention.

Fig. 1-7 are cross-sectional schematic diagrams depicting various intermediate stages of an exemplary method for forming the semiconductor device of fig. 7, in accordance with some embodiments.

FIG. 8 is a cross-sectional view of a semiconductor device including an electric field redistribution pattern, according to some embodiments.

Fig. 9, 10A, 10B, and 11 are cross-sectional schematic diagrams illustrating intermediate stages of exemplary methods for forming the semiconductor device of fig. 11, in accordance with further embodiments.

FIG. 12 is a schematic cross-sectional view illustrating a semiconductor device including an electric field redistribution pattern according to further embodiments.

FIG. 13 is a schematic cross-sectional view illustrating a semiconductor device including an electric field redistribution pattern according to further embodiments.

Fig. 14A is a schematic top view illustrating a semiconductor device including an electric field redistribution pattern according to some embodiments.

FIG. 14B is a schematic diagram illustrating a top view of a semiconductor device including an electric field redistribution pattern, in accordance with further embodiments.

Reference numerals

10. 20, 30, 40, 50-semiconductor device

100 to the substrate

102-nucleation layer

104 buffer layer

106 channel layer

108-barrier layer

110. 115-patterned mask layer

112. 112' -Compound semiconductor layer

114A, 114B, 114C, 114D, 114E-groove

116A, 116B, 116C, 116D-semiconductor bump

120 protective layer

122 interlayer dielectric layer

202-gate electrode

204 source electrode

206-drain electrode

212-Gate contact

214 source contact

216-drain contact

222-gate field plate

224A, 224B, 224C source field plate

222', 224A', 224B ', 224C' -edge

Detailed Description

The following disclosure provides many different embodiments, or examples, for illustrating different components of embodiments of the invention. Specific examples of components and arrangements thereof are disclosed below to simplify the present disclosure. Of course, these specific examples are not intended to be limiting of the disclosure. For example, the following summary of the present specification describes forming a first feature over or on a second feature, i.e., embodiments in which the formed first and second features are in direct contact, and embodiments in which additional features may be formed between the first and second features, i.e., the first and second features are not in direct contact. Moreover, various examples of the present disclosure may use repeated reference characters and/or words. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the described configurations.

Also, spatially relative terms, such as "under … …," "below," "lower," "above," "upper," and the like, may be used for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (e.g., rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation. It should be understood that additional operations may be provided before, during, and/or after the methods described in embodiments of the invention, and that in other embodiments of the methods, some of the operations described may be replaced or omitted.

As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are approximate amounts, i.e., the meanings of "about", "about" and "about" may be implied without specific recitation of "about", "about" and "about".

Some variations of the example methods and structures are described herein. Those skilled in the art will readily recognize other modifications that may be made within the scope of the other embodiments. While some method embodiments are discussed as being performed in a particular order, various other method embodiments may be performed in another logical order and may include fewer or more steps than those discussed herein. In some of the drawings, reference numerals may be omitted where certain components or parts are shown so as not to obscure the other components or parts; this is to facilitate the depiction of such figures.

Embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, which are particularly suitable for a High Electron Mobility Transistor (HEMT). Since an electric field exceeding a critical strength (critical strength) may exist just below an edge of a field plate (e.g., a source field plate and/or a gate field plate), a material layer is broken down (punch through), thereby affecting the performance of the semiconductor device. In order to reduce the electric field strength directly below the edge of the field plate, the embodiment of the invention reduces the two-dimensional electron gas (2 DEG) by disposing an electric field redistribution pattern (electric field redistribution pattern) directly below the edge of the field plate, thereby reducing the electric field. Therefore, the breakdown voltage of the semiconductor device can be increased, and the reliability of the semiconductor device is further improved.

Fig. 1-7 are cross-sectional schematic diagrams depicting various intermediate stages of an exemplary method for forming the semiconductor device 10 of fig. 7, in accordance with some embodiments. In the embodiment shown in fig. 1-7, the electric field redistribution pattern is a compound semiconductor bump (bump).

FIG. 1 illustrates an initial step of a method for forming an electric field redistribution pattern according to an embodiment of the present invention. As shown in fig. 1, a substrate 100 is provided. Next, a buffer layer 104 is formed over the substrate 100, a channel layer 106 is formed over the buffer layer 104, and a barrier layer 108 is formed over the channel layer 106. In some embodiments, a nucleation layer (102) may be formed between the substrate 100 and the buffer layer 104, as shown in fig. 1.

The substrate 100 may be or include a bulk semiconductor (bulk semiconductor) substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. Generally, semiconductor-on-insulator substrates include a film of semiconductor material formed on an insulator. For example, the insulating layer may be a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer, a polysilicon (poly-silicon) layer, or a stacked combination thereof. The insulating layer is provided on a substrate, typically a silicon (silicon) or aluminum nitride (AlN) substrate. Other substrates, such as multi-layered or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate may include silicon having different crystal planes, including Si (111) or Si (110). In some embodiments, the substrate 100 may be a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a Sapphire (Sapphire) substrate.

The nucleation layer 102 may mitigate lattice differences between the substrate 100 and overlying layers to improve crystal quality. The nucleation layer 102 is selective. In some embodiments, the material of the nucleation layer 102 may be or include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), other suitable materials, or combinations thereof. For example, the nucleation layer 102 may have a thickness in a range from about 1 nanometer (nm) to about 500 nm, such as about 200 nm. In some embodiments, the nucleation Layer 102 may be formed by a Deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.

The buffer layer 104 may relieve strain (strain) in the channel layer 106 subsequently formed over the buffer layer 104 to prevent defects from forming in the channel layer 106 above, the strain being caused by a mismatch between the channel layer 106 and the substrate 102. In other embodiments, as mentioned above, the buffer layer 104 may be formed directly on the substrate without providing the nucleation layer 102, so as to simplify the process steps and achieve the improved effect. In some embodiments, the material of the buffer layer 104 may comprise a group III-V compound semiconductor material, such as a group III nitride. For example, the material of the buffer layer 104 may be or include Gallium Nitride (GaN), aluminum Nitride (AlN), aluminum Gallium Nitride (AlGaN), aluminum indium Nitride (AlInN), other suitable materials, or combinations thereof. For example, the thickness of the buffer layer 104 may range from about 500 nanometers to about 50000 nanometers. In some embodiments, the buffer layer 104 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.

Two-dimensional electron gas (2DEG) may be formed at the hetero-interface between the channel layer 106 and the barrier layer 108 by piezoelectric polarization (piezo polarization) effect induced by different lattice constants between the channel layer 106 and the barrier layer 108 and spontaneous polarization (spontaneous polarization) respectively (not shown). The two-dimensional electron gas (2DEG) serves as a conductive carrier of a High Electron Mobility Transistor (HEMT). In some embodiments, the channel layer 106 and the barrier layer 108 are free of dopants. In some other embodiments, the channel layer 106 and the barrier layer 108 may have dopants, such as n-type dopants or p-type dopants.

In some embodiments, the material of the channel layer 106 may comprise one or more group III-V compound semiconductor materials, such as a group III nitride. For example, the material of the channel layer 106 may be or include GaN, AlGaN, AlInN, InGaN, InAlGaN, other suitable materials, or combinations thereof. In some embodiments, the thickness of channel layer 106 may range between about 0.05 microns (μm) and about 1 micron, such as about 0.4 microns. According to some embodiments, the channel layer 106 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or combinations thereof.

In some embodiments, the material of the barrier layer 108 may comprise a group III-V compound semiconductor material, such as a group III nitride. For example, the barrier layer 108 may be or include AlN, AlGaN, AlInN, AlGaInN, other suitable materials, or combinations thereof. The barrier layer 108 may comprise a single layer or a multi-layer structure. In some embodiments, the thickness of the barrier layer 108 may be in a range from about 3 nanometers to about 100 nanometers, such as about 12 nanometers. In some embodiments, the barrier layer 108 may be formed by a deposition process, such as Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), other suitable processes, or a combination of the foregoing.

Fig. 2 illustrates the formation of the compound semiconductor layer 112 and the compound semiconductor layer 112'. A gate electrode 202 (not shown in fig. 2, but described below with reference to fig. 4) is subsequently formed over the compound semiconductor layer 112. The compound semiconductor layer 112 can suppress generation of a two-dimensional electron gas (2DEG) under the gate electrode 202 to achieve a normally-off (normal-off) state of the semiconductor device. The compound semiconductor layer 112 'corresponds to a position of a first edge 224A' (not shown in fig. 2 but described below with reference to fig. 7) of a first source field plate 224A to be formed later, and will be referred to as a compound semiconductor bump (bump)116A in a subsequent process as an electric field redistribution pattern (electric field redistribution pattern) for reducing an electric field of the semiconductor device 10.

In some embodiments, the compound semiconductor layer 112 and the compound semiconductor layer 112' may be p-type doped or n-type doped gallium nitride (GaN). For example, the thickness of the compound semiconductor layer 112 may be in a range of about 50 nanometers to about 100 nanometers, such as about 80 nanometers, and the width of the compound semiconductor layer 112 may be in a range of about 0.1 micrometers to about 3 micrometers, such as about 1.5 micrometers. In some embodiments, the compound semiconductor layer 112 and the compound semiconductor layer 112' have the same thickness and width. In other embodiments, the compound semiconductor layer 112' has a width smaller than that of the compound semiconductor layer 112. For example, the width of the compound semiconductor layer 112' may be in a range of about 0.1 microns to about 3 microns, such as about 0.5 microns.

In some embodiments, the compound semiconductor layer 112 and the compound semiconductor layer 112' may be formed through a deposition process and a patterning process. For example, a layer of compound semiconductor material may be formed on the barrier layer 108 by a deposition process. In some embodiments, the patterning process includes forming a patterned mask layer 110 on the compound semiconductor material layer, and then etching a portion of the compound semiconductor material layer not covered by the patterned mask layer 110, thereby forming a compound semiconductor layer 112 and a compound semiconductor layer 112'. In some embodiments, the compound semiconductor layer 112 and the compound semiconductor layer 112' may have a rectangular cross section as shown, or may have other shapes, such as a trapezoidal cross section. In some embodiments, the upper surfaces of the compound semiconductor layer 112 and the compound semiconductor layer 112' may be uneven.

In some embodiments, the deposition process may comprise Metal Organic Chemical Vapor Deposition (MOCVD), Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), similar processes, or combinations of the foregoing.

In some embodiments, the patterned masking layer 110 may be a photoresist, such as a positive photoresist or a negative photoresist. In other embodiments, the patterned masking layer 110 may be a hard mask, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or combinations thereof. In some embodiments, the patterned mask layer 110 may be formed by spin-on coating (spin-on coating), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), other suitable processes, or a combination thereof.

In some embodiments, the deposited material layer may be etched by a dry etch process, a wet etch process, or a combination of the foregoing. For example, etching of the deposited material layer includes Reactive Ion Etching (RIE), Inductively Coupled Plasma (ICP) etching, Neutron Beam Etching (NBE), electron cyclotron resonance (ERC) etching, other suitable etching processes, or a combination thereof.

Next, referring to fig. 3, a thin-down process is performed on the compound semiconductor layer 112 'to form a first compound semiconductor bump 116A directly under a first edge 224A' (not shown in fig. 3, but refer to the description below with respect to fig. 7) of a first source field plate 224A to be formed later. For example, the thinning process includes forming a patterned mask layer 115 having an opening corresponding to the compound semiconductor layer 112 'on the barrier layer, wherein the patterned mask layer 115 covers the compound semiconductor layer 112 but exposes a top surface of the compound semiconductor layer 112'. An etching process may then be performed to partially etch the compound semiconductor layer 112 'exposed by the opening of the patterned mask layer 115 to reduce the thickness of the compound semiconductor layer 112', thereby forming the first compound semiconductor bump 116A. In other words, the thickness of the first compound semiconductor bump 116A is smaller than the thickness of the compound semiconductor layer 112. Since the first compound semiconductor bump 116A has a smaller thickness, the first compound semiconductor bump 116A may function as an electric field redistribution pattern, which may consume the two-dimensional electron gas thereunder without interrupting the conductive path of the two-dimensional electron gas, thereby reducing the electric field.

In some embodiments, the thickness of the first compound semiconductor bump 116A is about 1/8 a of the thickness of the compound semiconductor layer 112. For example, the thickness of the first compound semiconductor bump 116A may be in a range from about 1 nanometer to about 80 nanometers, such as about 10 nanometers.

In some embodiments, the material and formation process of the patterned mask layer 115 may be similar to those of the patterned mask 110 described above with respect to fig. 2, and thus are not described herein again. In some embodiments, the etching process may be similar to the etching process described above with respect to fig. 2, and thus will not be described herein.

Referring to fig. 4, a gate electrode 202 is formed on the compound semiconductor layer 112. In some embodiments, the material of the gate electrode 202 may be or include a conductive material, such as a metal, a metal silicide, a semiconductor material, or a combination thereof. For example, the metal may be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), similar materials, alloys thereof, multi-layered structures thereof, or combinations thereof, and the semiconductor material may be polycrystalline silicon (poly-Si) or polycrystalline germanium (poly-Ge). In some embodiments, the step of forming the gate electrode 202 may include comprehensively depositing a conductive material layer (not shown) for the gate electrode 202 over the substrate 100, and performing a patterning process on the conductive material layer to form the gate electrode 202 over the compound semiconductor layer 112. The deposition process to form the conductive material may be Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD) (e.g., sputtering), combinations of the foregoing, or the like.

Referring to fig. 5, the passivation layer 120 is conformally formed along the gate electrode 202, the compound semiconductor layer 112, the first compound semiconductor bump 116A, and the barrier layer 108. Since the sidewalls of the compound semiconductor layer 112 may have lattice defects generated due to the aforementioned etching process, the protective layer 120 formed on the sidewalls of the compound semiconductor layer 112 may repair the lattice defects on the sidewalls of the compound semiconductor layer 112 to reduce the gate leakage current of the formed semiconductor device. Furthermore, the protective layer 120 formed on the upper surface of the barrier layer 108 may be used to prevent oxidation of the surface of the barrier layer 108, thereby enhancing the performance of the formed semiconductor device.

In some embodiments, the material of the protective layer 120 may comprise or be an insulating material or a dielectric material, such as silicon oxide (SiO)₂) Silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Aluminum nitride (AlN), magnesium oxide (MgO), magnesium nitride (Mg)₃N₂) Zinc oxide (ZnO), titanium oxide (TiO)₂) Combinations of the foregoing, or the like. In some embodiments, the material of the protection layer 120 is a nitride or an oxide, such as silicon nitride, aluminum oxide, other suitable materials, or combinations thereof, which can be preferably repaired Lattice defects of the sidewalls of the compound semiconductor layer 112. In some embodiments, the thickness of the protective layer 120 may be in a range from about 0.5 nanometers to about 500 nanometers. In some embodiments, the protection layer 120 may be formed globally over the substrate 100 by Chemical Vapor Deposition (CVD), such as Plasma Enhanced CVD (PECVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), such as sputtering (sputtering), or the like.

Next, referring to fig. 6, a source electrode 204 and a drain electrode 206 are disposed on two sides of the gate electrode 202, wherein the source electrode 204 and the drain electrode 206 extend through the passivation layer 120 and a portion of the barrier layer 108. In some embodiments, the forming of the source electrode 204 and the drain electrode 206 includes performing a patterning process to recess the protective layer 120 and a portion of the barrier layer 108 on both sides of the compound semiconductor layer 112, forming a pair of recesses through the protective layer 120 and extending to the barrier layer 108, then depositing a conductive material over the pair of recesses, and performing a patterning process on the deposited conductive material to form the source electrode 204 and the drain electrode 206 at desired locations. The deposition process and materials used to form the source electrode 204 and the drain electrode 206 may be similar to those of the gate electrode 202, and thus are not described in detail herein.

Although the source electrode 204 and the drain electrode 206 are disposed on the passivation layer 120, penetrate through the passivation layer 120 and extend to the barrier layer 108 in the embodiment shown in fig. 6, the invention is not limited thereto, and the extending depth of the source electrode 204 and the drain electrode 206 can be adjusted according to the characteristics required by the actual product. For example, the source electrode 204 and the drain electrode 206 may also pass through the barrier layer 108 and extend into the channel layer 106.

Although the source and drain

electrodes

204, 206 and the gate electrode 202 are described as being formed in different steps, the invention is not limited thereto. For example, the source electrode 204 and the drain electrode 206 may be formed simultaneously with the gate electrode 202 by a deposition process and a patterning process after forming the recesses for the source electrode 204 and the drain electrode 206 before forming the gate electrode 202. It should be noted that in some embodiments in which the source and drain

electrodes

204, 206 and the gate electrode 202 are formed simultaneously, the protective layer 120 is also conformally formed along the source and drain

electrodes

204, 206. In some embodiments, the formation of the source and drain

electrodes

204, 206 and the gate electrode 202 may independently comprise the same or different processes and materials. In addition, the shapes of the source electrode 204, the drain electrode 206 and the gate electrode 202 are not limited to the vertical sidewalls in the drawings, and may be sloped sidewalls or have other shapes.

Referring to fig. 7, an interlayer dielectric (ILD) layer 122 is formed on the passivation layer 120, covering the compound semiconductor layer 112, the first compound semiconductor bump 116A, the gate electrode 202, and the source and drain

electrodes

204 and 206. A source contact 214 connected to the source electrode 204 and a drain contact 216 connected to the drain electrode 206 are formed in the interlayer dielectric layer 122. A first source field plate 224A is formed on the interlayer dielectric layer 122, and the first source field plate 224A is connected to the source electrode 204 through the source contact 214. The first source field plate 224A has a first edge 224A' between the gate electrode 202 and the drain electrode 206. As previously discussed, due to the possibility of an electric field exceeding a critical strength being present directly below the edge (e.g., first edge 224A') of a field plate (e.g., first source field plate 224A), the material layer is broken down, thereby affecting the performance of the semiconductor device. Providing an electric field redistribution pattern (e.g., the first compound semiconductor bump 116A) directly below the edge of the field plate may reduce the two-dimensional electron gas, thereby reducing the electric field. Thus, the breakdown voltage of the semiconductor device 10 can be increased, thereby improving the reliability of the semiconductor device 10.

In some embodiments, the interlayer dielectric layer 122 may comprise or be one or more layers of silicon dioxide, low-k dielectric materials such as silicon oxynitride, phosphosilicate Glass (PSG), borosilicate Glass (BSG), borophosphosilicate Glass (BPSG), Undoped Silicate Glass (USG), fluorine-doped silicate Glass (FSG), organosilicate Glass (OSG), SiOxCy, Spin-On-Glass (Spin-On-polymer), carbon-silicon materials, compounds thereof (composites thereof), similar materials, or combinations thereof. The interlayer dielectric layer 122 may be deposited by any suitable process, such as Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), the like, or combinations thereof.

In some embodiments, the material of the source contact 214, the drain contact 216, and the first source field plate 224A may be a metallic material, such as gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), combinations thereof, or multilayers thereof. The step of forming the source contact 214 and the drain contact 216 may include forming openings (not shown) corresponding to the source electrode 204 and the drain electrode 206, respectively, through the interlayer dielectric layer 122 and exposing the source electrode 204 and the drain electrode 206, respectively, by a patterning process, depositing a metal material (not shown) on the interlayer dielectric layer 122 and filling the openings, and performing a planarization process to remove portions of the metal material above the interlayer dielectric layer 122, thereby forming the source contact 214 and the drain contact 216. Next, a first source field plate 224A may be formed on the interlayer dielectric layer 122 by a deposition process and a patterning process, which is connected to the source electrode 204 through the source contact 214. In the embodiment where the passivation layer 120 is conformally disposed along the source electrode 204 and the drain electrode 206, the openings formed by the patterning process further penetrate the passivation layer 120 to expose the source electrode 204 and the drain electrode 206, respectively.

Fig. 14A and 14B are schematic top views illustrating a semiconductor device 10 including an electric field redistribution pattern. In some embodiments, the first compound semiconductor bump 116A may be a plurality of discontinuous bumps directly under the edge 224A' of the first source field plate 224A in a top view, that is, the electric field redistribution pattern may be discontinuous, as shown in fig. 14A. In other embodiments, in the top view, the first compound semiconductor bump 116A may be a stripe bump directly under the edge 224A' of the first source field plate 224A, i.e., the electric field redistribution pattern may be a stripe, as shown in fig. 14B.

As shown in fig. 7, the semiconductor device 10 includes a channel layer 106 disposed over a substrate, a barrier layer 108 disposed over the channel layer 106, a compound semiconductor layer 112 disposed over the barrier layer 108, a gate electrode 202 disposed over the compound semiconductor layer 112, and a source electrode 204 and a drain electrode 206 disposed on both sides of the gate electrode. The source electrode 204 and the drain electrode 206 extend through at least a portion of the barrier layer 108. The semiconductor device 10 also includes a first source field plate 224A connected to the source electrode 204 through the source contact 214, wherein the first source field plate 224A has a first edge 224A'. The semiconductor device 10 further includes a first compound semiconductor bump 116A disposed on the barrier layer 108 and directly under the first edge 224A'. The first compound semiconductor bump 116A may act as an electric field redistribution pattern that may consume the two-dimensional electron gas thereunder without interrupting the conductive path of the two-dimensional electron gas to mitigate the electric field strength directly under the first edge 224A' of the first source field plate 224A. Thus, the breakdown voltage of the semiconductor device 10 can be increased, thereby improving the reliability of the semiconductor device 10.

The semiconductor device 10 further includes a passivation layer 120 conformally disposed along the gate electrode 202, the compound semiconductor layer 112, and the first compound semiconductor bump 116A. The passivation layer 120 can repair lattice defects on the sidewalls of the compound semiconductor layer 112 due to the etching process to reduce the gate leakage current of the semiconductor device 10. In addition, the passivation layer 120 may also prevent oxidation of the surface of the barrier layer 108 to enhance the performance of the semiconductor device 10.

Although the embodiment shown in fig. 7 has only one field plate (e.g., the first source field plate 224A) in the semiconductor device 10, the present invention is not limited thereto, and the number of field plates may be adjusted according to the characteristics required by the actual product. For example, as shown in fig. 8, the semiconductor device 20 may have additional second source field plates 224B, third source field plates 224C, and gate field plates 222, wherein the second and third

source field plates

224B, 224C are connected to the source electrode 204 through the source contact 214, and the gate field plates 222 are connected to the gate electrode 202 through the gate contact 212. In this embodiment, the compound semiconductor bump may be disposed directly below the edge of the additional field plate. For example, as shown in fig. 8, the second compound semiconductor bump 116B is located directly below the second edge 224B ' of the second source field plate 224B, the third compound semiconductor bump 116C is located directly below the third edge 224C ' of the third source field plate 224C, and the fourth compound semiconductor bump 116D is located directly below the edge 222 ' of the gate field plate 222.

In some embodiments, the second source field plate 224B, the third source field plate 224C, the gate field plate 222 and the second compound semiconductor bump 116B, the third compound semiconductor bump 116C, and the fourth compound semiconductor bump 116D may be formed using processes and materials similar to those used for forming the first source field plate 224A and the first compound semiconductor bump 116A described above with respect to fig. 1-7, and thus, will not be described herein again. In some embodiments, the gate contact 212 corresponding to the gate electrode 202 may be formed using processes and materials similar to those used to form the source contact 214 described above with respect to fig. 7, and therefore will not be described in detail herein.

As shown in fig. 8, in some embodiments, the higher the field plates, the closer their edges are to the drain electrode 206, specifically, the first edge 224A 'of the first source field plate 224A is closer to the drain electrode 206 than the edge 222' of the gate field plate 222, the second edge 224B 'of the second source field plate 224B is closer to the drain electrode 206 than the first edge 224A' of the first source field plate 224A, and the third edge 224C 'of the third source field plate 224C is closer to the drain electrode 206 than the second edge 224B' of the second source field plate 224B. In some embodiments, the first semiconductor bump 116A, the second semiconductor bump 116B, the third semiconductor bump 116C, and the fourth semiconductor bump 116D may have the same thickness. Moreover, in other embodiments, the first semiconductor bump 116A, the second semiconductor bump 116B, the third semiconductor bump 116C, and the fourth semiconductor bump 116D may have different thicknesses, for example, the higher the field plate, the thinner the semiconductor bump directly below the edge thereof may be. Specifically, the thickness of the third semiconductor bump 116C is less than the thickness of the second semiconductor bump 116B, the thickness of the second semiconductor bump 116B is less than the thickness of the first semiconductor bump 116A, and the thickness of the first semiconductor bump 116A is less than the thickness of the fourth semiconductor bump 116D.

Fig. 9, 10A, 10B, and 11 are cross-sectional schematic diagrams illustrating intermediate stages of exemplary methods for forming the semiconductor device 30 of fig. 11, in accordance with further embodiments. For clarity, similar or identical elements and processes will be provided with the same reference signs. For the sake of brevity, the description of these processes and apparatus will not be repeated here.

Semiconductor device 30 is similar to semiconductor device 10, except that in the embodiments shown in fig. 9, 10A, 10B, and 11, the electric field redistribution pattern is a recess (stress).

Referring to fig. 9, the same or similar process as described above with respect to fig. 1-4 is performed to form the structure of fig. 9, except that the first compound semiconductor bump 116A is not formed over the barrier layer 108.

Next, as shown in fig. 10A, the barrier layer 108 is recessed to form a first recess 114A, wherein the first recess 114A extends from the upper surface of the barrier layer 108 to the lower surface of the barrier layer 108. The first recess 114A corresponds to a location of a first edge 224A' (not shown in fig. 10A, but see the description below with respect to fig. 11) of a first source field plate 224A to be subsequently formed. The formation of the first recess 114A provides a portion of the barrier layer 108 located below the first recess 114A with a reduced thickness, which helps to reduce the two-dimensional electron gas thereunder, thereby reducing the electric field. Accordingly, the first groove 114A may serve as an electric field redistribution pattern that reduces the electric field of the semiconductor device 30. In some embodiments, the depth of the first groove 114A may be in a range from about 1 nanometer to about 4 nanometers, such as about 2 nanometers.

In some embodiments, the barrier layer 108 may be recessed by a patterning process to form the first recess 114A. For example, the patterning process may include a photolithography process (e.g., photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist developing, other suitable processes, or combinations thereof), an etching process (e.g., wet etching, dry etching, other suitable processes, or combinations thereof), other suitable processes, or combinations thereof. In some embodiments, a patterned photoresist layer (not shown) having an opening corresponding to the first groove 114A may be formed on the barrier layer 108 through a photolithography process, and then an etching process may be performed to remove a portion of the barrier layer 108 exposed by the opening of the patterned photoresist layer, so as to form the first groove 114A in the barrier layer 108. The patterned photoresist layer may then be removed by a process such as ashing (ash) or wet strip (wet strip).

Although the embodiment shown in fig. 10A only penetrates a portion of the barrier layer 108, the invention is not limited thereto, and the extending depth of the first recess 114A may be adjusted according to the characteristics required by the actual product. For example, the first recess 114A may also pass through the barrier layer 108 and extend into the channel layer 106, as shown in fig. 10B.

The description of the process for forming the semiconductor device 30 continues with the structure of fig. 10A, although it is understood that the semiconductor device 30 may also be formed using the structure of fig. 10B. Next, a series of processes similar to those described in fig. 5 to 7 are performed on the structure shown in fig. 10A to complete the semiconductor device 30 shown in fig. 11.

As shown in fig. 11, the semiconductor device 30 includes a channel layer 106 disposed over a substrate, a barrier layer 108 disposed over the channel layer 106, a compound semiconductor layer 112 disposed over the barrier layer 108, a gate electrode 202 disposed over the compound semiconductor layer 112, and a source electrode 204 and a drain electrode 206 disposed on both sides of the gate electrode. The source electrode 204 and the drain electrode 206 extend through at least a portion of the barrier layer 108. The semiconductor device 30 also includes a first source field plate 224A connected to the source electrode 204 through the source contact 214, wherein the first source field plate 224A has a first edge 224A'. The semiconductor device 30 further includes a first recess 114A disposed on the barrier layer 108 and directly below the first edge 224A'. The first recess 114A extends from the upper surface of the barrier layer 108 to the lower surface of the barrier layer 108. The reduced thickness of the portion of the barrier layer 108 located under the recess 114A due to the formation of the first recess 114A helps to reduce the two-dimensional electron gas thereunder to mitigate the electric field strength directly under the first edge 224A' of the first source field plate 224A. Thus, the breakdown voltage of the semiconductor device 30 can be increased, and the reliability of the semiconductor device 30 can be improved.

The semiconductor device 30 further includes a passivation layer 120 conformally disposed along the gate electrode 202, the compound semiconductor layer 112, and the first recess 114A. The passivation layer 120 can repair lattice defects on sidewalls of the compound semiconductor layer 112 due to the etching process to reduce gate leakage current of the semiconductor device 30. In addition, the passivation layer 120 may also prevent oxidation of the surface of the barrier layer 108 to enhance the performance of the semiconductor device 30.

Fig. 14A and 14B also illustrate a top view of the semiconductor device 30 including the electric field redistribution pattern. In some embodiments, as shown in fig. 14A, in the top view, the first groove 114A may be a plurality of discontinuous grooves directly below the edge 224A' of the first source field plate 224A, that is, the electric field redistribution pattern may be discontinuous. In other embodiments, as shown in fig. 14B, in the top view, the first groove 114A may be a stripe groove directly below the edge 224A' of the first source field plate 224A, that is, the electric field redistribution pattern may be a stripe. It should be noted that in embodiments where the first recess 114A passes through the barrier layer 108 and extends into the channel layer 106, the electric field redistribution pattern is discontinuous in the top view schematic diagram in such embodiments, as shown in fig. 14A, since the first recess 114A blocks the conduction path of the two-dimensional electron gas.

As mentioned previously, the number of field plates in the semiconductor device 30 can be adjusted according to the characteristics required for the actual product. For example, as shown in fig. 12, the semiconductor device 40 may have additional second source field plates 224B, third source field plates 224C, and gate field plates 222, wherein the second and third

source field plates

224B, 224C are connected to the source electrode 204 through the source contact 214, and the gate field plates 222 are connected to the gate electrode 202 through the gate contact 212. In this embodiment, the grooves may be located directly below the edges of the additional field plates, for example, as shown in fig. 12, the second groove 114B is located directly below the second edge 224B ' of the second source field plate 224B, the third groove 114C is located directly below the third edge 224C ' of the third source field plate 224C, and the fourth groove 114D is located directly below the edge 222 ' of the gate field plate 222.

In some embodiments, the second source field plate 224B, the third source field plate 224C, and the gate field plate 222 may be formed using processes and materials similar to those previously used to form the first source field plate 224A with respect to fig. 7, and therefore will not be described again. In some embodiments, the gate contact 212 corresponding to the gate electrode 202 may be formed using processes and materials similar to those used to form the source contact 214 described above with respect to fig. 7, and therefore will not be described in detail herein. In some embodiments, the second recess 114B, the third recess 114C, and the fourth recess 114D may be formed using a process similar to that for forming the first recess 114A described above with respect to fig. 10A, and thus will not be described herein again.

As previously mentioned, referring to fig. 12, in some embodiments, the higher the field plates, the closer their edges are to the drain electrode 206, specifically, the first edge 224A 'of the first source field plate 224A is closer to the drain electrode 206 than the edge 222' of the gate field plate 222, the second edge 224B 'of the second source field plate 224B is closer to the drain electrode 206 than the first edge 224A' of the first source field plate 224A, and the third edge 224C 'of the third source field plate 224C is closer to the drain electrode 206 than the second edge 224B' of the second source field plate 224B. In some embodiments, the first, second, third and

fourth grooves

114A, 114B, 114C, 114D may have the same depth. In addition, in other embodiments, the first, second, third and

fourth grooves

114A, 114B, 114C, 114D may have different depths, for example, the higher the field plate, the shallower the groove directly below its edge. Specifically, the depth of the third groove 114C is smaller than the depth of the second groove 114B, the depth of the second groove 114B is smaller than the depth of the first groove 114A, and the depth of the first groove 114A is smaller than the depth of the fourth groove 114D.

Fig. 13 is a schematic cross-sectional view illustrating a semiconductor device 50 according to some other embodiments. For clarity, similar or identical elements and processes will be provided with the same reference signs. For the sake of brevity, the description of these processes and apparatus will not be repeated here. The semiconductor device 50 is similar to the semiconductor device 30 except that a fifth groove 114E is provided at the edge of the compound semiconductor layer 112.

Referring to fig. 13, in the step of forming the first groove 114A, a fifth groove 114E is simultaneously formed. The fifth recess 114E extends from the upper surface of the barrier layer 108 toward the lower surface of the barrier layer 108. The fifth recess 114E is located between the gate electrode 202 and the drain electrode 206 and adjacent to the edge of the compound semiconductor layer 112. Due to surface polarization, there is a strong polarization electric field at the edge of the compound semiconductor layer 112, which causes the material layer to break down, thereby affecting the performance of the semiconductor device. The provision of the recess 114E at the edge of the compound semiconductor layer 112 can reduce the surface polarization effect, thereby reducing the electric field and improving the reliability of the semiconductor device 50. In some embodiments, an additional groove may be optionally provided at the edge of the other side of the compound semiconductor layer 112. The fifth recess 114E may be formed using a process similar to that for forming the first recess 114A described above with respect to fig. 10A or 10B, and thus will not be described herein again.

Although the semiconductor devices 10/20/30/40/50 each have only a single type of electrical field redistribution pattern (e.g., compound semiconductor bumps or grooves) in the illustrated embodiment, the invention is not limited thereto, and two types of electrical field redistribution patterns may be integrated into the semiconductor devices according to the characteristics required by the actual product. For example, a groove-type electric field redistribution pattern (e.g., fifth groove 114E) may be disposed at an edge of the compound semiconductor layer, and a semiconductor bump-type electric field redistribution pattern (e.g., semiconductor bumps 116A, 116B, 116C, and/or 116D) may be disposed directly below an edge of the field plate.

In summary, the embodiments of the present invention reduce the two-dimensional electron gas by providing the electric field redistribution pattern including the compound semiconductor bump or groove directly under the edge of the field plate, thereby reducing the electric field. Therefore, the breakdown voltage of the semiconductor device can be increased, and the reliability of the semiconductor device is further improved. In addition, the embodiment of the invention also reduces the surface polarization effect by arranging the electric field redistribution pattern comprising the groove on the edge of the compound semiconductor layer, thereby reducing the electric field and further improving the reliability of the semiconductor device.

The foregoing has outlined rather broadly the features of the various embodiments of the present invention so that those skilled in the art may better understand the present disclosure. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or achieving the same advantages of the embodiments of the present disclosure. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising:

a channel layer disposed on a substrate;

a barrier layer disposed on the channel layer;

a compound semiconductor layer disposed on the barrier layer;

a gate electrode disposed on the compound semiconductor layer;

a source electrode and a drain electrode disposed on both sides of the gate electrode, wherein the source electrode and the drain electrode penetrate at least a portion of the barrier layer;

a source field plate connected to the source electrode by a source contact, wherein the source field plate has an edge; and

a first electric field redistribution pattern disposed on the barrier layer and directly below the edge.

2. The semiconductor device of claim 1, wherein the first electric field redistribution pattern comprises at least one compound semiconductor bump disposed on the barrier layer.

3. The semiconductor device of claim 2, wherein a thickness of the at least one compound semiconductor bump is less than a thickness of the compound semiconductor layer.

4. The semiconductor device of claim 2, wherein the at least one compound semiconductor bump and the compound semiconductor layer comprise the same material.

5. The semiconductor device of claim 1, wherein the first electric field redistribution pattern is at least one recess extending from an upper surface of the barrier layer to a lower surface of the barrier layer.

6. The semiconductor device of claim 5, wherein said at least one recess extends through said barrier layer and to said channel layer.

7. The semiconductor device of claim 1, further comprising an additional source field plate connected to said source electrode by said source contact, wherein an edge of said additional source field plate is closer to said drain electrode than an edge of said source field plate, and said first electric field redistribution pattern is disposed more directly below said edge of said additional source field plate.

8. The semiconductor device according to claim 1, wherein the first electric field redistribution pattern is discontinuous in a top view schematic view.

9. The semiconductor device according to claim 1, wherein the first electric field redistribution pattern is stripe-shaped in a top view.

10. The semiconductor device of claim 1, further comprising a second electric field redistribution pattern, the second electric field redistribution pattern being at least one groove extending from an upper surface of the barrier layer to a lower surface of the barrier layer, wherein the second electric field redistribution pattern is located between the gate electrode and the drain electrode and adjacent to an edge of the compound semiconductor layer.

11. The semiconductor device of claim 1, further comprising a passivation layer conformally disposed along said gate electrode, said compound semiconductor layer, and said first electric field redistribution pattern.

12. A method for manufacturing a semiconductor device, comprising:

forming a channel layer on a substrate;

forming a barrier layer on the channel layer;

forming a compound semiconductor layer over the barrier layer;

forming a gate electrode on the compound semiconductor layer;

forming a first electric field redistribution pattern on the barrier layer;

forming a source electrode and a drain electrode on both sides of the gate electrode, wherein the source electrode and the drain electrode penetrate at least a portion of the barrier layer;

forming a source field plate connected to the source electrode by a source contact, wherein the source field plate has an edge near the drain electrode, and wherein the first electric field redistribution pattern is located directly below the edge.

13. The method of claim 12, wherein said step of forming said first electric field redistribution pattern comprises forming at least one compound semiconductor bump on said barrier layer.

14. The method of claim 13, wherein a thickness of the at least one compound semiconductor bump is less than a thickness of the compound semiconductor layer.

15. The method of claim 13, wherein the at least one compound semiconductor bump and the compound semiconductor layer are formed of the same material.

16. The method of claim 12, wherein the step of forming the first electric field redistribution pattern comprises recessing the barrier layer to form at least one recess.

17. The method of claim 16, wherein said at least one recess extends through said barrier layer and to said channel layer.

18. The method of claim 12, further comprising forming an additional source field plate connected to said source electrode by said source contact, wherein an edge of said additional source field plate is closer to said drain electrode than an edge of said source field plate, and said first electric field redistribution pattern is disposed more directly below said edge of said additional source field plate.

19. The method of claim 12, wherein the first electric field redistribution pattern is discontinuous in a top view.

20. The method of claim 12, wherein the first field redistribution pattern is stripe-shaped in a top view.

21. The method of claim 12, further comprising recessing the barrier layer to form a second electric field redistribution pattern, wherein the second electric field redistribution pattern is between the gate electrode and the drain electrode and adjacent to an edge of the compound semiconductor layer.

22. The method of claim 12, further comprising conformally forming a passivation layer along the gate electrode, the compound semiconductor layer, and the first electric field redistribution pattern.