TWI769431B - Structure of enhanced gallium nitride transistor and packaging chip using the same - Google Patents

Structure of enhanced gallium nitride transistor and packaging chip using the same Download PDF

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TWI769431B
TWI769431B TW109102410A TW109102410A TWI769431B TW I769431 B TWI769431 B TW I769431B TW 109102410 A TW109102410 A TW 109102410A TW 109102410 A TW109102410 A TW 109102410A TW I769431 B TWI769431 B TW I769431B
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electrode
layer
gate electrode
nitride layer
group iii
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TW202129961A (en
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邱紹諺
林靖璋
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大陸商聚力成半導體(重慶)有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors

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Abstract

The invention discloses a structure of an enhanced gallium nitride transistor, including: a source electrode; a drain electrode; a gate electrode; a p-III group nitride layer disposed under the gate electrode; A group III nitride layer in contact with the lower surface of the p-III nitride layer, the lower surface of the drain electrode and the lower surface of the source electrode; a group III barrier layer disposed on the lower surface of the group III nitride; wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and there is a groove between at least one of the gate electrode and the source electrode, or between the gate electrode and the drain electrode. The bottom of the groove terminates in the group III barrier layer; one end of the gate electrode or the drain electrode is disposed in the groove.

Description

增強型氮化鎵電晶體之結構與使用該結構之封裝晶片 The structure of enhancement mode gallium nitride transistor and the package chip using the structure

本發明是一種氮化鎵電晶體之結構，尤指一種掘入式和原生長晶p型氮化鎵(in-situ p-GaN)的增強型氮化鎵電晶體之結構。 The present invention relates to a structure of a gallium nitride transistor, in particular to a structure of an enhancement type gallium nitride transistor of in-situ p-GaN (in-situ p-GaN).

氮化鎵高功率元件是由原本空乏型工作方式，轉而更有經濟效益的增強型模式。目前市場產品皆為p型氮化鎵作為閘極控制，但由於氮化鎵材料對於p型(p-GaN)活化不易(活化濃度<1×18cm-3)，導致氮化鎵與金屬-半導體介面(Metal-semiconductor interface)容易崩潰；導致整體閘極損壞而無法提升最佳化崩潰電壓和穩定性。另一方面，掘入式(recessed)閘極深度控制的缺點在於控制不易與介電層(dielectric layer)於過薄而易崩潰。兩種方法都屬於元件特性之臨限電壓(threshold voltage)；皆是由閘極負電壓轉為正電壓(即空乏型D-mode轉為增強型E-mode)。 Gallium nitride high-power components have changed from the original depletion mode to a more economical enhancement mode. At present, all products on the market use p-type GaN as gate control. However, due to the difficulty in activation of p-type (p-GaN) materials (activation concentration <1×18cm -3 ), GaN and metal-semiconductor The metal-semiconductor interface is prone to collapse; the overall gate is damaged and the optimized breakdown voltage and stability cannot be improved. On the other hand, the disadvantage of the recessed gate depth control is that the control is not easy to control and the dielectric layer is too thin and it is easy to collapse. Both methods belong to the threshold voltage of component characteristics; both are converted from negative gate voltage to positive voltage (ie, depletion D-mode to enhancement E-mode).

本發明目的之一是提升閘極的臨限電壓。 One of the objectives of the present invention is to increase the threshold voltage of the gate.

本發明目的之一是提升介電層的崩潰電壓。 One of the objectives of the present invention is to increase the breakdown voltage of the dielectric layer.

本發明揭露一種增強型氮化鎵電晶體之結構，包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電 極之下表面；一III族阻障層，設置於該III族氮化物層之下表面；以及其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中。 The invention discloses a structure of an enhancement mode gallium nitride transistor, comprising: a source electrode; a drain electrode; a gate electrode; a p-III nitride layer disposed under the gate electrode; Group III nitride layer, contacting the lower surface of the p-III nitride layer, the lower surface of the drain electrode, and the source electrode a lower surface of the electrode; a group III barrier layer disposed on the lower surface of the group III nitride layer; and wherein at least one of the gate electrode or the drain electrode is an L-shaped electrode, and the gate electrode There is a trench between at least one of the source electrode or the gate electrode and the drain electrode, and the bottom of the trench terminates in the group III barrier layer; the gate electrode or the drain electrode One end of the drain electrode is disposed in the trench.

本發明揭露一種封裝晶片，包含：至少一增強型氮化鎵電晶體之結構，該結構包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電極之下表面；以及一III族阻障層，設置於該III族氮化物層之下表面；其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中；以及該封裝晶片為該結構之組合。 The invention discloses a package chip, comprising: a structure of at least one enhancement mode gallium nitride transistor, the structure comprising: a source electrode; a drain electrode; a gate electrode; under the gate electrode; a group III nitride layer contacting the lower surface of the p-III nitride layer, the lower surface of the drain electrode, and the lower surface of the source electrode; and a group III resistor A barrier layer, disposed on the lower surface of the III-nitride layer; wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and between the gate electrode and the source electrode, or the A trench exists between at least one of the gate electrode and the drain electrode, and the bottom of the trench terminates in the group III barrier layer; one end of the gate electrode or the drain electrode is disposed in the trench among them; and the packaged chip is a combination of the structures.

100、200:增強型氮化鎵電晶體之結構 100, 200: Structure of enhancement mode gallium nitride transistor

source:源極電極 source: source electrode

drain:汲極電極 drain: drain electrode

gate:閘極電極 gate: gate electrode

101、201:p-III族氮化物層 101, 201: p-III nitride layer

102、202:III族氮化物層 102, 202: Group III nitride layer

103、203:III族阻障層 103, 203: Group III barrier layer

PL:場效電板 PL: Field Effect Panel

D:介電層 D: Dielectric layer

C:通道層 C: channel layer

B:緩衝層 B: buffer layer

S:基板 S: substrate

2DEG:二維電子氣 2DEG: two-dimensional electron gas

J、K:端 J, K: end

T:凸塊 T: bump

diode:二極體 diode: diode

300:封裝晶片 300: Package Chip

30:非掘入式的增強型氮化鎵電晶體之結構 30: Structure of non-digging enhancement mode gallium nitride transistors

R:溝槽 R: groove

圖1A顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。 FIG. 1A shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention.

圖1B顯示基板上表面之凸塊之側面示意圖。 FIG. 1B shows a schematic side view of the bumps on the upper surface of the substrate.

圖1C顯示基板上表面之凸塊之俯視示意圖。 FIG. 1C shows a schematic top view of the bumps on the upper surface of the substrate.

圖1D顯示濃度分佈圖。 Figure 1D shows a concentration profile.

圖1E顯示掘入式閘極的能帶圖。 Figure 1E shows the energy band diagram of the submerged gate.

圖1F顯示p型氮化鎵閘極的能帶圖。 Figure 1F shows the band diagram of the p-type gallium nitride gate.

圖1G顯示掘入式閘極的能帶圖。 Figure 1G shows the energy band diagram of the submerged gate.

圖1H顯示p型氮化鎵閘極的能帶圖。 Figure 1H shows the band diagram of the p-type gallium nitride gate.

圖1I顯示汲極電流跟閘極電壓圖。 Figure 1I shows a graph of drain current versus gate voltage.

圖1J顯示汲極電流跟汲極電壓圖。 Figure 1J shows a graph of drain current versus drain voltage.

圖1K顯示本實施例之電場圖。 FIG. 1K shows the electric field diagram of this embodiment.

圖1L顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。 FIG. 1L shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention.

圖2A顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。 FIG. 2A shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention.

圖2B顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。 FIG. 2B shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention.

圖3顯示一封裝晶片之示意圖。 FIG. 3 shows a schematic diagram of a packaged chip.

請參考圖1A，圖1A顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。結構100包含：源極電極source、汲極電極drain、閘極電極gate、p-III族氮化物層101、III族氮化物層102、III族阻障層103、場效電板PL、介電層D、通道層C、緩衝層B、以及基板S。 Please refer to FIG. 1A . FIG. 1A shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention. The structure 100 includes: source electrode source, drain electrode drain, gate electrode gate, p-III nitride layer 101, III nitride layer 102, III barrier layer 103, field effect plate PL, dielectric Layer D, channel layer C, buffer layer B, and substrate S.

p-III族氮化物層101，設置於閘極電極gate之下；、III族氮化物層102接觸p-III族氮化物層101之下表面、汲極電極drain之下表面、以及源極電極source之下表面；III族阻障層103設置於III族氮化物層102之下表面。 The p-III nitride layer 101 is disposed under the gate electrode gate; the III nitride layer 102 contacts the lower surface of the p-III nitride layer 101, the lower surface of the drain electrode, and the source electrode The lower surface of the source; the group III barrier layer 103 is disposed on the lower surface of the group III nitride layer 102 .

在一實施例中，p-III族氮化物層101為P型氮化鎵(p-GaN)所實現、III族氮化物層102為氮化鎵(GaN)所實現。 In one embodiment, the p-III nitride layer 101 is realized by p-type gallium nitride (p-GaN), and the group III nitride layer 102 is realized by gallium nitride (GaN).

請注意，在本實施例中，閘極電極gate為一L型電極，且閘極電極gate與源極電極source之間存在一溝槽R，源極電極source橫跨溝槽R，且溝槽R之底部終止於III族阻障層103之中，意即溝槽R之底部接近III族阻障層103與通道層C之交界；其中，閘極電極gate之一端設置於溝槽R之中，而汲極電極drain或源極電極source覆蓋部分p-III族氮化物層101之上表面。於一實施例中，閘極電極gate之一端J係垂直伸入於溝槽R中，且閘極電極gate之一端J不接觸III族阻障層103之側壁，閘極電極gate之一端J終止於III族阻障層103所延伸之平面。 Please note that in this embodiment, the gate electrode gate is an L-shaped electrode, and there is a trench R between the gate electrode gate and the source electrode source, the source electrode source spans the trench R, and the trench The bottom of R terminates in the group III barrier layer 103 , which means that the bottom of the trench R is close to the boundary between the group III barrier layer 103 and the channel layer C; wherein, one end of the gate electrode gate is arranged in the trench R , and the drain electrode drain or the source electrode source covers part of the upper surface of the p-III nitride layer 101 . In one embodiment, one end J of the gate electrode gate extends vertically into the trench R, and one end J of the gate electrode gate does not contact the sidewall of the group III barrier layer 103 , and one end J of the gate electrode gate terminates On the plane where the group III barrier layer 103 extends.

除此之外，源極電極source亦為L型電極，閘極電極gate與源極電極source之間存在溝槽R，閘極電極gate另一端則接觸p-III族氮化物層101之上表面。 In addition, the source electrode source is also an L-shaped electrode, a trench R exists between the gate electrode gate and the source electrode source, and the other end of the gate electrode gate contacts the upper surface of the p-III nitride layer 101 .

場效電板PL覆蓋部分閘極電極gate，且場效電板PL凸出於閘極電極gate上表面；以及介電層D填充於溝槽R並覆蓋源極電極source之表面、場效電板PL之表面、汲極電極drain之表面、閘極電極gate之表面、p-III族氮化物層101之表面、III族氮化物層102之表面以及III族阻障層103之表面。 The field effect plate PL covers part of the gate electrode gate, and the field effect plate PL protrudes from the upper surface of the gate electrode gate; and the dielectric layer D is filled in the trench R and covers the surface of the source electrode source, the field effect electrode The surface of the plate PL, the surface of the drain electrode, the surface of the gate electrode gate, the surface of the p-III nitride layer 101 , the surface of the III nitride layer 102 and the surface of the III barrier layer 103 .

源極電極source為另一個L型電極，源極電極source之一端接觸III族氮化物層102，另一端延伸於場效電板PL與p-III族氮化物層101之上，且源極電極source橫跨溝槽R。其中，二維電子氣2DEG位置如圖所示。 The source electrode source is another L-shaped electrode, one end of the source electrode source is in contact with the group III nitride layer 102, the other end extends over the field effect plate PL and the p-III group nitride layer 101, and the source electrode source spans trench R. Among them, the position of the two-dimensional electron gas 2DEG is shown in the figure.

請同時參考圖1B與圖1C，圖1B顯示基板S上表面之凸塊T之側面示意圖，圖1C顯示基板S上表面之凸塊T之俯視示意圖，基板S上表面分布設置複數個凸塊T，凸塊T呈陣列形排列，且凸塊T凸出於基板S上表面，而基板S設置於緩衝層B之下表面；通道層C設置於緩衝層B之上，且通道層C設置於III族阻障層103之下表面。其中，緩衝層B可為氮化鋁鎵(AlxGa1-x N)所實現，且x=0.03~0.05。 Please refer to FIGS. 1B and 1C at the same time. FIG. 1B shows a schematic side view of the bumps T on the upper surface of the substrate S, and FIG. 1C shows a top view of the bumps T on the upper surface of the substrate S. A plurality of bumps T are distributed on the upper surface of the substrate S. , the bumps T are arranged in an array, and the bumps T protrude from the upper surface of the substrate S, and the substrate S is arranged on the lower surface of the buffer layer B; the channel layer C is arranged on the buffer layer B, and the channel layer C is arranged on the The lower surface of the group III barrier layer 103 . Wherein, the buffer layer B can be realized by aluminum gallium nitride (Al x Ga 1-x N), and x=0.03-0.05.

凸塊T之高度小於1μm，凸塊T最大長度小於200nm，凸塊T之間的距離為490~500nm。 The height of the bumps T is less than 1 μm, the maximum length of the bumps T is less than 200nm, and the distance between the bumps T is 490-500nm.

在一實施例中，凸塊T可為六角柱狀體所實現；上述之結構100可以減少先前技術之缺陷密度，並使結構100減少漏電以及磊晶厚度(磊晶厚度可小於4μm)；除此之外，因場效電板PL凸出於閘極電極gate上表面、以及源極電極source為另一個L型電極，可同時維持或增加結構100的高崩潰電壓。 In one embodiment, the bump T can be realized by a hexagonal column; the above-mentioned structure 100 can reduce the defect density of the prior art, and make the structure 100 reduce leakage and epitaxial thickness (the epitaxial thickness can be less than 4 μm); In addition, because the field effect plate PL protrudes from the upper surface of the gate electrode gate and the source electrode source is another L-shaped electrode, the high breakdown voltage of the structure 100 can be maintained or increased at the same time.

順向導通(Vth)由掘入式和p-GaN閘極空乏至通道濃度降低(Vds=10V,Vgs=0V)，隨著Vgs=1、5、10V電壓增 加通道濃度提升，如圖1D濃度分佈圖所示，其中Electron Conc表示電子濃度；圖1E~1H能帶圖表示掘入式(recessed gate)和p-GaN閘極分別所需電壓。 The forward conduction (Vth) decreases from the depletion of the submerged and p-GaN gate to the channel concentration (Vds=10V, Vgs=0V), with the increase of Vgs=1, 5, 10V Increase the channel concentration, as shown in the concentration distribution diagram in Figure 1D, where Electron Conc represents the electron concentration; Figure 1E~1H energy band diagrams represent the voltages required for the recessed gate and the p-GaN gate, respectively.

請參考1I~1J圖，圖1I顯示汲極電流跟閘極電壓圖，圖1J顯示汲極電流跟汲極電壓圖。順向導通電壓隨著(Vgs>0V)由掘入式閘極增加導通電流濃度(-2V)，隨後；大電壓(Vgs>>0)增加p-GaN閘極導通(Vgs~2V)，以提升整體元件Vth=3.2V。 Please refer to Figures 1I~1J. Figure 1I shows the graph of drain current and gate voltage, and Figure 1J shows the graph of drain current and drain voltage. The forward conduction voltage increases with (Vgs>0V) the conduction current concentration (-2V) from the digging gate, and then; the large voltage (Vgs>>0) increases the p-GaN gate conduction (Vgs~2V), to Raise the overall component Vth=3.2V.

如圖1J所示一般掘入式閘極有較大的導通電阻(Rds,on)；然此本發明之結構100有相對低於傳統式結構的導通電阻(Rds,on~3m Ω-cm2)。 As shown in FIG. 1J , the digging gate generally has a larger on-resistance (Rds,on); however, the structure 100 of the present invention has a relatively lower on-resistance (Rds,on~3m Ω-cm 2 than the conventional structure). ).

如圖1K所示，圖1K顯示本實施例之電場圖；在高電壓下，電場會由掘入式閘極轉移至p型氮化鎵閘極。。 As shown in FIG. 1K , FIG. 1K shows the electric field diagram of this embodiment; under high voltage, the electric field will be transferred from the digging gate to the p-type gallium nitride gate. .

請同時參考圖1L，圖1L顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖，結構100的源極電極source可以被一二極體diode所共用；或者本實施例之源極電極source可視為兩個源極電極source之耦接。 Please refer to FIG. 1L at the same time. FIG. 1L shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention. The source electrode source of the structure 100 can be shared by a diode diode; or the source electrode of this embodiment The electrode source can be regarded as the coupling of the two source electrodes source.

請參考圖2A，圖2A顯示本發明增強型氮化鎵電晶體之結構一實施例之示意圖。結構200包含：源極電極source、汲極電極drain、閘極電極gate、p-III族氮化物層201、III族氮化物層202、III族阻障層203、場效電板PL、介電層D、通道層C、緩衝層B、以及基板S。 Please refer to FIG. 2A. FIG. 2A shows a schematic diagram of an embodiment of the structure of the enhancement mode gallium nitride transistor of the present invention. The structure 200 includes: source electrode source, drain electrode drain, gate electrode gate, p-III nitride layer 201, III nitride layer 202, III barrier layer 203, field effect plate PL, dielectric Layer D, channel layer C, buffer layer B, and substrate S.

p-III族氮化物層201，設置於閘極電極gate之下；、III族氮化物層202接觸p-III族氮化物層201之下表面、汲極電極drain之下表面、以及源極電極source之下表面；III族阻障層203設置於III族氮化物層202之下表面。 The p-III nitride layer 201 is disposed under the gate electrode gate; the III nitride layer 202 contacts the lower surface of the p-III nitride layer 201, the lower surface of the drain electrode, and the source electrode The lower surface of the source; the group III barrier layer 203 is disposed on the lower surface of the group III nitride layer 202 .

在一實施例中，p-III族氮化物層201為P參雜氮化鎵(GaN)所實現、III族氮化物層202為氮化鎵(GaN)所實現。 In one embodiment, the p-III nitride layer 201 is realized by p-doped gallium nitride (GaN), and the group III nitride layer 202 is realized by gallium nitride (GaN).

請注意，在本實施例中，汲極電極drain為一L 型電極，且閘極電極gate與汲極電極drain之間存在一溝槽R，且溝槽R之底部終止於III族阻障層203之中，意即溝槽R之底部接近III族阻障層203與通道層C之交界；其中，汲極電極drain之一端設置於溝槽R之中，而汲極電極drain或源極電極source覆蓋部分p-III族氮化物層201之上表面。於一實施例中，汲極電極drain之一端K係垂直伸入於溝槽R中，且汲極電極drain之一端K不接觸III族阻障層203之側壁，汲極電極drain之一端K終止於III族阻障層203所延伸之平面。 Please note that in this embodiment, the drain electrode drain is one L type electrode, and there is a trench R between the gate electrode gate and the drain electrode drain, and the bottom of the trench R is terminated in the group III barrier layer 203, which means that the bottom of the trench R is close to the group III barrier The boundary between the layer 203 and the channel layer C; wherein, one end of the drain electrode drain is disposed in the trench R, and the drain electrode drain or the source electrode source covers part of the upper surface of the p-III nitride layer 201 . In one embodiment, one end K of the drain electrode extends vertically into the trench R, and one end K of the drain electrode does not contact the sidewall of the group III barrier layer 203 , and one end K of the drain electrode is terminated On the plane where the group III barrier layer 203 extends.

場效電板PL覆蓋部分閘極電極gate，且場效電板PL凸出於閘極電極gate上表面；以及介電層D填充於溝槽R並覆蓋、場效電板PL之表面、源極電極source之表面、汲極電極drain之表面、閘極電極gate之表面、p-III族氮化物層201之表面、III族氮化物層202之表面以及III族阻障層203之表面。 The field effect plate PL covers part of the gate electrode gate, and the field effect plate PL protrudes from the upper surface of the gate electrode gate; and the dielectric layer D is filled in the trench R and covers, the surface of the field effect plate PL, the source The surface of the source electrode source, the surface of the drain electrode, the surface of the gate electrode gate, the surface of the p-III nitride layer 201 , the surface of the III nitride layer 202 and the surface of the III barrier layer 203 .

源極電極source為另一個L型電極，源極電極source之一端接觸III族氮化物層202，另一端延伸於場效電板PL與III族氮化物層202、閘極電極gate、以及溝槽R之上。 The source electrode source is another L-shaped electrode, one end of the source electrode source contacts the III-nitride layer 202 , and the other end extends to the field effect plate PL and the III-nitride layer 202 , the gate electrode gate, and the trench above R.

結構200的基板S上表面分布設置複數個凸塊T，凸塊T呈陣列形排列，且凸塊T凸出於基板S上表面，而基板S設置於緩衝層B之下表面；通道層C設置於緩衝層B之上，且通道層C設置於III族阻障層203之下表面。同前所述，緩衝層B可為氮化鋁鎵(AlxGa1-x N)所實現，且x=0.03~0.05。 A plurality of bumps T are distributed on the upper surface of the substrate S of the structure 200, the bumps T are arranged in an array, and the bumps T protrude from the upper surface of the substrate S, and the substrate S is arranged on the lower surface of the buffer layer B; the channel layer C is disposed on the buffer layer B, and the channel layer C is disposed on the lower surface of the group III barrier layer 203 . As mentioned above, the buffer layer B can be realized by aluminum gallium nitride (Al x Ga 1-x N), and x=0.03-0.05.

凸塊T之高度小於1μm，凸塊T最大長度小於200nm，凸塊T之間的距離為490~500nm。 The height of the bumps T is less than 1 μm, the maximum length of the bumps T is less than 200nm, and the distance between the bumps T is 490-500nm.

在一實施例中，凸塊T可為六角柱狀體所實現；上述之結構200可以減少先前技術之缺陷密度，並使結構200減少漏電以及磊晶厚度(磊晶厚度可小於4um)；除此之外，因源極電極source為一個L型電極，可同時維持或增加結構200的高崩潰電壓。 In one embodiment, the bump T can be realized by a hexagonal column; the above-mentioned structure 200 can reduce the defect density of the prior art, and make the structure 200 reduce leakage and epitaxial thickness (the epitaxial thickness can be less than 4um); In addition, since the source electrode source is an L-shaped electrode, the high breakdown voltage of the structure 200 can be maintained or increased at the same time.

請同時參考圖2B，圖2B顯示本發明增強型氮化 鎵電晶體之結構一實施例之示意圖，結構200的源極電極source可以被一二極體diode所共用；或者本實施例之源極電極source可視為兩個源極電極source之耦接。 Please also refer to FIG. 2B. FIG. 2B shows the enhancement mode nitridation of the present invention. A schematic diagram of an embodiment of the structure of a gallium transistor, the source electrode source of the structure 200 can be shared by a diode diode; or the source electrode source of this embodiment can be regarded as a coupling of two source electrodes source.

接著請同時參考圖3，圖3顯示一封裝晶片之示意圖。請注意，封裝晶片300可以包含至少一個結構100或200或及其組合。 Next, please refer to FIG. 3 at the same time. FIG. 3 shows a schematic diagram of a packaged chip. Note that the package die 300 may include at least one structure 100 or 200 or a combination thereof.

在一實施例中，封裝晶片300包含兩個非掘入式的增強型氮化鎵電晶體之結構30、掘入式的增強型氮化鎵電晶體之結構100以及掘入式的增強型氮化鎵電晶體之結構200，其中至少一個非掘入式的增強型氮化鎵電晶體之結構30與至少其一的結構100或200共用其源極電極source。 In one embodiment, the packaged chip 300 includes two structures 30 of a non-drilled enhancement mode GaN transistor, a structure 100 of a submerged enhancement mode GaN transistor, and a submerged enhancement mode nitrogen In the structure 200 of the GaN transistor, the structure 30 of at least one non-digging enhancement mode GaN transistor shares its source electrode source with at least one of the structures 100 or 200 .

在一實施例中，掘入式的增強型氮化鎵電晶體之結構200、非掘入式的增強型氮化鎵電晶體之結構30、與結構100或200均共用其汲極電極drain；除此之外，結構200之源極電極source可為克爾文源極電極(Kelvin Source)所實現。 In one embodiment, the structure 200 of the burrowed enhancement mode GaN transistor, the structure 30 of the non-burrowed enhancement mode GaN transistor, and the structure 100 or 200 all share the drain electrode drain; Besides, the source electrode source of the structure 200 can be realized by a Kelvin source electrode.

綜上所述，本發明的結構利用掘入式的增強型氮化鎵電晶體之結構，可使增強型氮化鎵電晶體之結構臨限電壓大於2V、崩潰電壓大於1000V，且本發明結構無遲滯現象產生。 To sum up, the structure of the present invention utilizes the structure of the digging-type enhancement mode gallium nitride transistor, so that the structural threshold voltage of the enhancement mode gallium nitride transistor can be greater than 2V and the breakdown voltage is greater than 1000V, and the structure of the present invention No hysteresis occurs.

100:增強型氮化鎵電晶體之結構 100: Structure of Enhancement Mode Gallium Nitride Transistor

source:源極電極 source: source electrode

drain:汲極電極 drain: drain electrode

gate:閘極電極 gate: gate electrode

101:p-III族氮化物層 101: p-III nitride layer

102:III族氮化物層 102: Group III nitride layer

103:III族阻障層 103: Group III barrier layer

PL:場效電板 PL: Field Effect Panel

D:介電層 D: Dielectric layer

C:通道層 C: channel layer

B:緩衝層 B: buffer layer

S:基板 S: substrate

2DEG:二維電子氣 2DEG: two-dimensional electron gas

J:端 J: end

T:凸塊 T: bump

diode:二極體 diode: diode

R:溝槽 R: groove

Claims (12)

一種增強型氮化鎵電晶體之結構，包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電極之下表面；以及一III族阻障層，設置於該III族氮化物層之下表面；其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中；當該源極電極為另一個該L型電極，則該閘極電極與該源極電極之間存在該溝槽，且該閘極電極另一端接觸該p-III族氮化物層；該結構包含：一場效電板，覆蓋部分該閘極電極；以及一介電層，填充該溝槽並覆蓋該源極電極之表面、該場效電板之表面、該汲極電極之表面、該閘極電極之表面、該p-III族氮化物層之表面、該III族氮化物層之表面以及該III族阻障層之表面；該源極電極為另一個該L型電極，該源極電極之一端接觸該III族氮化物層，另一端延伸於該場效電板與該p-III族氮化物層之上；以及該源極電極為另一個該L型電極，該源極電極之一端接觸 該III族氮化物層，另一端延伸於該場效電板與該p-III族氮化物層之上。 A structure of an enhancement mode gallium nitride transistor, comprising: a source electrode; a drain electrode; a gate electrode; a p-III group nitride layer disposed under the gate electrode; a group III nitrogen a compound layer contacting the lower surface of the p-III nitride layer, the lower surface of the drain electrode, and the lower surface of the source electrode; and a group III barrier layer disposed between the group III nitride layer lower surface; wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and at least one of the gate electrode and the source electrode, or between the gate electrode and the drain electrode a trench exists, the bottom of the trench terminates in the group III barrier layer; one end of the gate electrode or the drain electrode is disposed in the trench; when the source electrode is another of the L-type electrode, the trench exists between the gate electrode and the source electrode, and the other end of the gate electrode contacts the p-III nitride layer; the structure includes: a field effect plate, covering part of the gate electrode; and a dielectric layer filling the trench and covering the surface of the source electrode, the surface of the field effect plate, the surface of the drain electrode, the surface of the gate electrode, the p-III group the surface of the nitride layer, the surface of the group III nitride layer and the surface of the group III barrier layer; the source electrode is another of the L-type electrodes, and one end of the source electrode contacts the group III nitride layer, The other end extends above the field effect plate and the p-III nitride layer; and the source electrode is another L-shaped electrode, and one end of the source electrode is in contact with The other end of the group III nitride layer extends over the field effect plate and the p-III group nitride layer. 根據請求項1所述的結構，其中，該源極電極被一二極體共用。 The structure according to claim 1, wherein the source electrode is shared by a diode. 根據請求項2所述的結構，其中，該結構更包含：一通道層；一緩衝層；以及一基板，該基板上表面分布設置複數個凸塊，且該基板設置於該緩衝層之下表面；其中，該通道層設置於該緩衝層之上，且該通道層設置於該III族阻障層之下表面。 The structure according to claim 2, wherein the structure further comprises: a channel layer; a buffer layer; and a substrate, a plurality of bumps are arranged on the upper surface of the substrate, and the substrate is arranged on the lower surface of the buffer layer ; wherein, the channel layer is arranged on the buffer layer, and the channel layer is arranged on the lower surface of the group III barrier layer. 一種增強型氮化鎵電晶體之結構，包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電極之下表面；以及一III族阻障層，設置於該III族氮化物層之下表面；其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中；該汲極電極為該L型電極，該閘極電極與該汲極電極之間存在該溝槽，且該汲極電極另一端接觸該III族氮化物層；該結構包含：一場效電板，覆蓋部分該閘極電極；以及一介電層，填充該溝槽並覆蓋該源極電極之表面、該汲極電極之表面、該閘極電極之表面、該p-III族氮化物層之表面、該III族氮化物層之表面以及該III族阻障層之表面；以及該源極電極為該L型電極，該源極電極之一端接觸該III族氮化物層，另一端延伸於該場效電板與該p-III族氮化物層之上。 A structure of an enhancement mode gallium nitride transistor, comprising: a source electrode; a drain electrode; a gate electrode; a p-III group nitride layer disposed under the gate electrode; a group III nitrogen a compound layer contacting the lower surface of the p-III nitride layer, the lower surface of the drain electrode, and the lower surface of the source electrode; and a group III barrier layer disposed between the group III nitride layer lower surface; wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and at least one of the gate electrode and the source electrode, or between the gate electrode and the drain electrode A trench exists, and the bottom of the trench terminates in the group III barrier layer; an end of the gate electrode or the drain electrode is disposed in the trench; the drain electrode is the L-shaped electrode , the trench exists between the gate electrode and the drain electrode, and the other end of the drain electrode contacts the III-nitride layer; the structure includes: a field effect plate, covering part of the gate electrode; and a A dielectric layer filling the trench and covering the surface of the source electrode, the surface of the drain electrode, the surface of the gate electrode, the surface of the p-III nitride layer, the surface of the III nitride layer and the surface of the group III barrier layer; and the source electrode is the L-type electrode, one end of the source electrode contacts the group III nitride layer, and the other end extends between the field effect plate and the p-III group over the nitride layer. 根據請求項4所述的結構，其中，該源極電極被一二極體共用。 The structure of claim 4, wherein the source electrode is shared by a diode. 根據請求項5所述的結構，其中，該結構更包含：一通道層；一緩衝層；以及一基板，該基板上表面分布設置複數個凸塊，且該基板設置於該緩衝層之下表面；其中，該通道層設置於該緩衝層之上，且該通道層設置於該III族阻障層之下表面。 The structure according to claim 5, wherein the structure further comprises: a channel layer; a buffer layer; and a substrate, a plurality of bumps are arranged on the upper surface of the substrate, and the substrate is arranged on the lower surface of the buffer layer ; wherein, the channel layer is arranged on the buffer layer, and the channel layer is arranged on the lower surface of the group III barrier layer. 一種封裝晶片，包含：至少一增強型氮化鎵電晶體之結構，該結構包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電極之下表面；一III族阻障層，設置於該III族氮化物層之下表面；以及其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中；以及該封裝晶片為該結構之組合；其中，當該源極電極為另一個該L型電極，該閘極電極與該源極電極之間存在該溝槽，且該閘極電極另一端接觸該p-III族氮化物層；該結構包含：一場效電板，覆蓋部分該閘極電極；以及 一介電層，填充該溝槽並覆蓋該源極電極之表面、該場效電板之表面、該汲極電極之表面、該閘極電極之表面、該p-III族氮化物層之表面、該III族氮化物層之表面以及該III族阻障層之表面；以及該源極電極為該L型電極，該源極電極之一端接觸該III族氮化物層，另一端延伸於該場效電板與該p-III族氮化物層之上。 A package chip, comprising: a structure of at least one enhancement mode gallium nitride transistor, the structure comprising: a source electrode; a drain electrode; a gate electrode; a p-III nitride layer disposed on the gate under the electrode electrode; a group III nitride layer, contacting the lower surface of the p-III group nitride layer, the lower surface of the drain electrode, and the lower surface of the source electrode; a group III barrier layer, provided on the lower surface of the III-nitride layer; and wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and between the gate electrode and the source electrode, or the gate electrode There is a trench between at least one of the drain electrodes, the bottom of the trench is terminated in the group III barrier layer; an end of the gate electrode or the drain electrode is disposed in the trench; And the package chip is a combination of the structure; wherein, when the source electrode is another L-shaped electrode, the trench exists between the gate electrode and the source electrode, and the other end of the gate electrode contacts the p-III nitride layer; the structure includes: a field effect plate covering a portion of the gate electrode; and a dielectric layer filling the trench and covering the surface of the source electrode, the surface of the field effect plate, the surface of the drain electrode, the surface of the gate electrode, and the surface of the p-III nitride layer , the surface of the group III nitride layer and the surface of the group III barrier layer; and the source electrode is the L-type electrode, one end of the source electrode contacts the group III nitride layer, and the other end extends in the field over the effective plate and the p-III nitride layer. 根據請求項7所述的封裝晶片，其中，該源極電極被一二極體共用。 The packaged chip according to claim 7, wherein the source electrode is shared by a diode. 根據請求項8所述的結構，其中，該結構更包含：一通道層；一緩衝層；以及一基板，該基板上表面分布設置複數個凸塊，且該基板設置於該緩衝層之下表面；其中，該通道層設置於該緩衝層之上，且該通道層設置於該III族阻障層之下表面。 The structure according to claim 8, wherein the structure further comprises: a channel layer; a buffer layer; and a substrate, a plurality of bumps are arranged on the upper surface of the substrate, and the substrate is arranged on the lower surface of the buffer layer ; wherein, the channel layer is arranged on the buffer layer, and the channel layer is arranged on the lower surface of the group III barrier layer. 一種封裝晶片，包含：至少一增強型氮化鎵電晶體之結構，且該結構包含：一源極電極；一汲極電極；一閘極電極；一p-III族氮化物層，設置於該閘極電極之下；一III族氮化物層，接觸該p-III族氮化物層之下表面、該汲極電極之下表面、以及該源極電極之下表面；一III族阻障層，設置於該III族氮化物層之下表面；以及其中，該閘極電極或該汲極電極至少其一為一L型電極，且該閘極電極與該源極電極之間、或該閘極電極與該汲極電極之間至少其一存在一溝槽，該溝槽之底部終止於該III族阻障層之中；該閘極電極或該汲極電極之一端設置於該溝槽之中；以及該封裝晶片為該結構之組合；其中，該汲極電極為該L型電極，該閘極電極與該汲極電極之間存在該溝槽，且該汲極電極另一端接 觸該III族氮化物層；且該結構包含：一場效電板，覆蓋部分該閘極電極；一介電層，填充該溝槽並覆蓋該源極電極之表面、該汲極電極之表面、該閘極電極之表面、該p-III族氮化物層之表面、該III族氮化物層之表面以及該III族阻障層之表面；以及該源極電極為該L型電極，該源極電極之一端接觸該III族氮化物層，另一端延伸於該場效電板與該p-III族氮化物層之上。 A package chip, comprising: a structure of at least one enhancement mode gallium nitride transistor, and the structure comprises: a source electrode; a drain electrode; a gate electrode; a p-III nitride layer, disposed on the under the gate electrode; a group III nitride layer contacting the lower surface of the p-III group nitride layer, the lower surface of the drain electrode, and the lower surface of the source electrode; a group III barrier layer, disposed on the lower surface of the III-nitride layer; and wherein, at least one of the gate electrode or the drain electrode is an L-shaped electrode, and between the gate electrode and the source electrode, or the gate electrode There is a trench between at least one of the electrode and the drain electrode, the bottom of the trench is terminated in the group III barrier layer; one end of the gate electrode or the drain electrode is arranged in the trench ; And the packaged chip is a combination of the structure; wherein, the drain electrode is the L-shaped electrode, the trench exists between the gate electrode and the drain electrode, and the other end of the drain electrode is connected contacting the III-nitride layer; and the structure comprises: a field effect plate covering part of the gate electrode; a dielectric layer filling the trench and covering the surface of the source electrode, the surface of the drain electrode, the surface of the gate electrode, the surface of the p-III group nitride layer, the surface of the group III nitride layer and the surface of the group III barrier layer; and the source electrode is the L-type electrode, the source electrode One end of the electrode contacts the group III nitride layer, and the other end extends over the field effect plate and the p-III group nitride layer. 根據請求項10所述的封裝晶片，其中，該源極電極被一二極體共用。 The packaged chip according to claim 10, wherein the source electrode is shared by a diode. 根據請求項11所述的結構，其中，該結構更包含：一通道層；一緩衝層；以及一基板，該基板上表面分布設置複數個凸塊，且該基板設置於該緩衝層之下表面；其中，該通道層設置於該緩衝層之上，且該通道層設置於該III族阻障層之下表面。 The structure according to claim 11, wherein the structure further comprises: a channel layer; a buffer layer; and a substrate, a plurality of bumps are arranged on the upper surface of the substrate, and the substrate is arranged on the lower surface of the buffer layer ; wherein, the channel layer is arranged on the buffer layer, and the channel layer is arranged on the lower surface of the group III barrier layer.
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