TWI577009B - Enhanced High Electron Mobility Crystal - Google Patents

Description

Enhanced high electron mobility transistor

This invention relates to a transistor, and more particularly to a reinforced high electron mobility transistor.

Since gallium nitride has a wide energy gap, it can be successfully applied to high-frequency power components in addition to being used as a light-emitting material. In a transistor made of gallium nitride/aluminum gallium nitride material, the bending of the band and the discontinuity of the band due to the difference in energy gap between gallium nitride/aluminum gallium nitride are limited. A large number of electrons form 2DEG (two-dimensional electron gas). 2DEG has a very high electron mobility (about 1500 cm ² /Vs) and therefore has a high switching speed, but also because electrons exist in this region, so that the transistor needs to operate in a depletion mode, operating in this depletion mode. A transistor is generally referred to as a normally on transistor. The threshold voltage of such a normally-on transistor is a negative value, so that the transistor still conducts current when the gate is zero-biased, and additional power consumption is formed.

In order to apply GaN/AlGaN crystals to components such as high-power high-efficiency amplifiers, high-energy switching devices, and power-saving modes, it is necessary to form a normally off transistor, that is, components are biased at zero. A transistor that is not turned on during pressing and is turned on when a biasing operation is applied. Such a normally off transistor is currently fabricated using a recessed gate, or a barrier layer under the channel of aluminum gallium nitride (AlGaN), using a barrier layer. Polarized charge depletion channel charge, or CF ₄ plasma treatment, so that fluoride ions enter the channel of aluminum gallium nitride, the charge of the depletion channel, so that the transistor does not conduct at zero bias, and get the usual Normal off the transistor.

However, the above-mentioned gallium nitride/aluminum gallium nitride crystal is formed into a normally off transistor, and a recessed gate structure is used. Since etching is required, problems such as an increase in sheet resistance and an increase in leakage current are likely to occur. It affects the characteristics of the transistor; and the plasma treatment method is also easy to affect the semiconductor material because the fluoride ion enters the deep region of the semiconductor.

Accordingly, it is an object of the present invention to provide a reinforced high electron mobility transistor.

Thus, the reinforced high electron mobility transistor of the present invention comprises: a substrate, a semiconductor unit, a negatively charged layer, a dielectric layer, and an electrode unit.

The semiconductor unit includes a gallium nitride-based semiconductor material formed on a surface of the substrate and having a top surface away from the substrate.

The negatively charged layer is formed in a region of the top surface of the semiconductor unit.

The dielectric layer is disposed on a portion of the top surface of the semiconductor unit and covers the negatively charged layer.

The electrode unit includes a top surface disposed on the semiconductor unit, And a source, a drain, and a gate disposed on the dielectric layer via the dielectric layer.

The invention has the effect of forming a negatively charged layer in the shallow region of the top surface of the semiconductor unit, and using the electrons in the negatively charged channel region of the negatively charged layer to obtain a normally off transistor, because the negatively charged layer It is formed only in the shallow region and, therefore, does not damage the material properties of the semiconductor unit.

21‧‧‧Substrate

22‧‧‧ Buffer layer

23‧‧‧Semiconductor unit

231‧‧‧First semiconductor layer

232‧‧‧Second semiconductor layer

233‧‧‧ Third semiconductor layer

24‧‧‧With negative layer

25‧‧‧Dielectric layer

26‧‧‧Electrode unit

261‧‧‧ source

262‧‧‧汲polar

263‧‧‧ gate

Other features and effects of the present invention will be apparent from the embodiments of the present invention, wherein: FIG. 1 is a block diagram showing an embodiment of the reinforced high electron mobility transistor of the present invention; It is a physical property analysis diagram, and the SIMS (Secondary Ion Mass Spectrometer Analysis) diagram confirms that the fluoride ion is located on the upper surface of a third semiconductor layer; FIG. 3 is an electrical diagram illustrating a specific example in which V _GS is 0 V, 1 V, respectively. V _DS -I _DS under 2V, 3V, 4V, 5V; and FIG. 4 is an electrical diagram illustrating V _GS -I _DS under V _DS of 5V, 10V, 15V, 20V, respectively.

Referring to FIG. 1, an embodiment of a reinforced high electron mobility transistor of the present invention comprises: a substrate 21, a buffer layer 22, a semiconductor unit 23, a negatively charged layer 24, a dielectric layer 25, and an electrode. Unit 26.

The substrate 21 may be selected from sapphire, tantalum carbide (SiC) or bismuth (Si).

The buffer layer 22 is formed on the surface of the substrate and is selected from a gallium nitride or aluminum nitride material.

The semiconductor unit 23 includes a first semiconductor layer 231, a second semiconductor layer 232, and a third semiconductor layer 233 formed in this order from the surface of the buffer layer 22, wherein the surface of the third semiconductor layer 233 is The top surface of the semiconductor unit 23.

The semiconductor unit 23 can be deposited by chemical vapor deposition (CVD), molecular beam epitaxial growth (MBE) or organometallic vapor phase epitaxy (MOVPE), and since these process methods are well known in the art, they are no longer More details.

The first, second, and third semiconductor layers 231, 232, and 233 are selected from gallium nitride-based compounds. In the embodiment of the present invention, the first and third semiconductor layers 231 and 233 are made of gallium nitride. (GaN), the constituent material of the second semiconductor layer 232 is aluminum gallium nitride (AlGaN). It is to be noted that the film structure of the semiconductor unit 23 may further form an AlGaN semiconductor layer made of aluminum gallium nitride (AlGaN) between the first semiconductor layer 231 and the substrate 21 as needed, or Further forming a plurality of semiconductor film layers each composed of gallium nitride (GaN) and aluminum gallium nitride (AlGaN) to form a multi-layer structure of (AlGaN/GaN)n/GaN/AlGaN/GaN, n≧1, Since the related materials and film structures related to the semiconductor film layers are well known to those skilled in the art of HFMT, and are not the focus of the present technology, detailed descriptions thereof will not be repeated.

The negatively charged layer 24 contains a plurality of negative charges, which may be negative ions or electrons, formed in a shallow region of the top surface of the portion of the semiconductor unit 23.

In detail, the negatively charged layer 24 may be ICP-RIE (CF ₄ , SF ₆ ) (inductively coupled plasma reactive ion etching) in a nitrogen chamber, and the upper and lower electrodes are respectively 800/150 W, and processed. The surface of the third semiconductor layer 233 is bombarded by the plasma-enhanced reactive ion gas under the condition of a time of 100 seconds, and the third semiconductor layer 233 is subjected to a fluoride ion plasma surface treatment. The third semiconductor layer 233 is formed with the negatively charged layer 24 via the surface treated by the fluoride ion plasma, and the negatively charged layer 24 is placed in the shallow region of the surface of the third semiconductor layer 233.

It should be additionally noted that when the concentration of the fluoride ion of the negatively charged layer 24 is insufficient (that is, the surface treatment time of the fluoride ion plasma is too short), the negatively charged layer 24 cannot effectively interrupt the current.

The dielectric layer 25 is disposed on a portion of the top surface of the semiconductor unit 23 and covers the negatively charged layer 24.

The material of the dielectric layer 25 is selected from one of the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , ZrO ₂ , AlN, TiO ₂ , Y ₂ O ₃ , Ta ₂ O ₅ , BST, STO. It is deposited by chemical vapor deposition (CVD), electron beam evaporation (E-gun), organic metal vapor phase epitaxy (MOVPE), or atomic layer deposition (ALD).

The electrode unit 26 includes a source 261 and a drain disposed on a top surface of the semiconductor unit 23 and spaced apart from each other via the dielectric layer 25 262; and a gate 263 disposed on the dielectric layer 25 and corresponding to the location of the negatively charged layer 24, and wherein the surface area of the gate 263 is not less than the surface area of the negatively charged layer 24.

The material of the gate 263, the source 261, and the drain 262 may be selected from one of the following common metal groups: Ti, Al, Au, Cu, and may be a single layer or a multilayer structure as desired. Since the preparation, film structure and material selection of the electrode unit 26 are well known in the art, no further details are provided.

The present invention performs fluorochemical plasma surface treatment on the semiconductor unit 23 by ICP-RIE (CF ₄ , SF ₆₎ (inductively coupled plasma reactive ion etching) so that the semiconductor unit 23 is on the top (shallow) layer near the top surface. The region forms a negatively charged layer 24 with a plurality of fluoride ions, and therefore, the fluoride ions can be removed by the lower portion of the gate 263 and located at the junction of the first and second semiconductor layers 261 and 262 (GaN/AlGaN). The 2DEG charge between them is such that it does not conduct when the gate bias is zero, resulting in a normally off transistor. This method can avoid the conventional method of using the recessed gate structure, or the fluoride ion plasma treatment directly at the AlGaN/GaN interface, because the lattice structure of the semiconductor material is damaged, resulting in, for example, increased sheet resistance and leakage. Problems such as increased current.

Next, the reinforced high electron mobility transistor of the present invention will be described in detail using a specific example, which can be more clearly understood.

A specific example of the reinforced high electron mobility transistor of the present invention has substantially the same structure as the embodiment, but more precisely explains the actual thickness of the structure and the choice of materials.

In this embodiment, the material of the substrate is bismuth (Si), the buffer layer is selected from gallium nitride or aluminum nitride, and the semiconductor unit is upward from the buffer layer and has four semiconductor layers (in order A stacked structure of an AlGaN layer, a first GaN layer, a second AlGaN layer, and a second GaN layer).

Wherein, the thickness of the buffer layer is about 5 μm, and the thickness of each of the film layers (the first AlGaN layer/the first GaN layer/the second AlGaN layer/the second GaN layer) in the semiconductor unit is 10 nm/1 μm/25 nm/1.5, respectively. Nm.

The negatively charged layer is located on a shallow surface of the surface of the second GaN layer.

The dielectric layer covers the negatively charged layer, the gate level is located on the dielectric layer, and the orthographic projection of the gate level completely covers the negatively charged layer; the source and the drain are located on both sides of the dielectric layer And located on the surface of the second GaN layer. In this embodiment, the dielectric layer is Al ₂ O ₃ , the thickness is 25 nm, the gate width is 7 μm, and the source and the drain are made of titanium/aluminum/titanium/gold (Ti/Al/Ti). /Au) The film composition has a thickness of 25 nm / 1250 nm / 45 nm / 60 nm. The gate was composed of a nickel/gold (Ni/Au) film layer, followed by a sequence of 150 nm/50 nm.

A method for producing a specific example of the above-described reinforced high electron mobility transistor will be described below.

First, the buffer layer is formed by chemical vapor deposition (MOCVD) from a substrate surface, and then the first AlGaN layer, the first GaN layer, and the second AlGaN are sequentially deposited from the surface of the buffer layer by MOCVD. Layer, second GaN layer. Then, by wet etching, a portion of the surface of the first GaN layer is exposed from the top surface of the second GaN layer to be exposed, and the surface is exposed. Forming a platform (mesa) to obtain the semiconductor unit.

Then, a mask having two openings spaced apart from each other is formed on the surface of the second GaN layer by using a lithography process, and two metal layers are deposited on the surface of the second GaN layer from the two openings, and then the The source and the drain were obtained by masking and rapidly annealing the two metal layers (870 ° C, N ₂ condition, 30 sec).

Then, using a second lithography process, a mask having an opening between the source and the drain is formed on the surface of the second GaN layer, and then the second GaN layer is subjected to fluoride ionization from the opening. The surface of the slurry is treated for 100 seconds, and then the mask is removed to obtain the negatively charged layer located in the second GaN layer adjacent to the shallow region of the top surface of the second GaN layer, and after forming the negatively charged layer Subsequent processes can be performed without an annealing step.

Then, an ALD (Atomic Layer Deposition) is used to form the dielectric layer on the surface of the second GaN layer corresponding to the negative electrode layer, and finally, the surface of the dielectric layer is formed by sputtering to cover the tape. The reinforced high electron mobility transistor of the present invention can be obtained by the gate of the negative electrode layer.

Next, the reinforced high electron mobility transistor prepared in the above specific example was subjected to physical properties and electrical measurements.

Referring to FIG. 2, FIG. 2 is a SIMS (Secondary Ion Mass Spectrometry) measurement result of the reinforced high electron mobility transistor. The overall structure of this embodiment of the present invention is sequentially from the dielectric layer to Al ₂ O ₃ / negatively charged layer / GaN / AlGaN / GaN (25 nm / 1.5 nm / 25 nm / 1 μm / 10 nm). It can be seen from the SIMS results that the peak of the elemental fluorine (F) is located at about 26 nm, thus confirming that the elemental fluorine (F) is located in the shallow surface region of the second GaN layer.

In addition, the normally-closed transistor is such that when the gate bias voltage (V _GS ) is less than zero, the gate current (I _DS ) is not turned on due to the lack of space under the positive projection of the gate (no carrier passes). Referring to FIG. 3, FIG. 3 is a diagram illustrating the drain voltage V _DS versus the drain current ₍ I _DS ) of the specific example under different gate bias voltages (V _GS ) (0V, 1V, 2V, 3V, 4V, 5V). The change. In Fig. 3, when the gate bias voltage (V _GS ) is 0 V, due to the action of the fluorine ions, part of the 2DEG charge at the positive projection of the gate is excluded, so that the drain current (I _DS ) is not smooth. Turned on (I _DS value is zero), and when the gate bias (V _GS ) gradually increases, the drain current (I _DS ) begins to conduct. It was confirmed that the present invention can obtain a normally closed transistor by means of surface fluoride ion plasma treatment.

Referring to FIG. 4, FIG. 4 is a V _GS -I _{DS of} the specific example (CF ₄ plasma processing time is 100 seconds) under different V _DS (5V, 10V, 15V, 20V), which is known from FIG. 4 . When the drain bias voltage (V _DS )=5V, the threshold voltage (V _TH )=0.7V, and the drain current (I _DS ) regardless of the drain bias voltage (V _DS )=10V, 15V, or 20V The magnitude is related to the bias applied by the gate bias (V _GS ), confirming that the gate bias (V _GS ) of the present invention has good current control.

In addition, it should be added that the magnitude of V _TH (threshold voltage) can be further regulated by the concentration of the negatively charged layer, and when the concentration of the negatively charged layer is increased, the gate bias (V _GS ) needs to be added. With a negative layer, the 2DEG can be turned on smoothly, so the required V _TH (threshold voltage) is also increased.

In summary, the present invention performs fluorine on the second GaN layer. The surface treatment of the ionic plasma forms a negatively charged layer composed of a plurality of negative ions or electrons under the gate, and therefore can be eliminated by the negative charge corresponding to the underside of the gate and located at the first and second semiconductor layers The charge of 2DEG between the (GaN/AlGaN) junctions is not only simple in process, but also avoids the conventional recessed gate structure, or the method of performing fluoride ion plasma treatment directly on the AlGaN/GaN interface. The lattice structure causes damage and affects the characteristics of the crystal, so that the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the patent application scope and the patent specification of the present invention are still It is within the scope of the patent of the present invention.

21‧‧‧Substrate

22‧‧‧ Buffer layer

23‧‧‧Semiconductor unit

231‧‧‧First semiconductor layer

232‧‧‧Second semiconductor layer

233‧‧‧ Third semiconductor layer

24‧‧‧With negative layer

25‧‧‧Dielectric layer

26‧‧‧Electrode unit

261‧‧‧ source

262‧‧‧汲polar

263‧‧‧ gate

Claims (8)

A reinforced high electron mobility transistor comprises: a substrate; a semiconductor unit comprising a gallium nitride based semiconductor material formed on the surface of the substrate and having a top surface away from the substrate, the top surface being completely flat a negatively charged layer, a shallow surface region formed on a top surface of the semiconductor unit portion and downward from the top surface; a dielectric layer disposed on a portion of the top surface of the semiconductor unit and covering the negatively charged layer; And an electrode unit, comprising a source, a drain, and a gate disposed on the top surface of the semiconductor unit and spaced apart from each other via the dielectric layer. The reinforced high electron mobility transistor according to claim 1, wherein the negatively charged layer may be an ion layer. The reinforced high electron mobility transistor according to claim 1, wherein the negatively charged layer may be an electron layer. The reinforced high electron mobility transistor of claim 1, wherein the negatively charged layer has a surface area no greater than a surface area of the gate. The reinforced high electron mobility transistor according to claim 1, wherein the material of the dielectric layer is selected from one of the group consisting of Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , ZrO ₂ , AlN, TiO ₂ , Y ₂ O ₃ , Ta ₂ O ₅ , BST, STO. The reinforced high electron mobility transistor according to claim 1, wherein the semiconductor unit has a first half in order from the surface of the substrate a conductor layer, a second semiconductor layer, and a third semiconductor layer, wherein the first semiconductor layer and the third semiconductor layer are gallium nitride, and the second semiconductor layer is aluminum gallium nitride. The reinforced high electron mobility transistor according to claim 1, further comprising a buffer layer between the substrate and the semiconductor unit. The reinforced high electron mobility transistor according to claim 7, wherein the material of the buffer layer is selected from gallium nitride or aluminum nitride.