CN106298887A - A kind of preparation method of high threshold voltage high mobility notched gates MOSFET - Google Patents
A kind of preparation method of high threshold voltage high mobility notched gates MOSFET Download PDFInfo
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- CN106298887A CN106298887A CN201610868777.9A CN201610868777A CN106298887A CN 106298887 A CN106298887 A CN 106298887A CN 201610868777 A CN201610868777 A CN 201610868777A CN 106298887 A CN106298887 A CN 106298887A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 18
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000203 mixture Substances 0.000 claims abstract description 22
- 238000005036 potential barrier Methods 0.000 claims abstract description 21
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000004411 aluminium Substances 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 6
- 238000003475 lamination Methods 0.000 claims abstract description 6
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 230000008859 change Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 15
- 229910001020 Au alloy Inorganic materials 0.000 claims description 14
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 230000008020 evaporation Effects 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 2
- 229910000846 In alloy Inorganic materials 0.000 claims description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 2
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 2
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 2
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000007769 metal material Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 1
- 150000002500 ions Chemical class 0.000 claims 1
- 125000002524 organometallic group Chemical group 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 5
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- 230000005669 field effect Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
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- 230000008901 benefit Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
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- 230000000717 retained effect Effects 0.000 description 2
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- 229910017083 AlN Inorganic materials 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
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- 229910052593 corundum Inorganic materials 0.000 description 1
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- 230000003628 erosive effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention relates to the technical field of semiconductor epitaxial process, more particularly, to the preparation method of a kind of high threshold voltage high mobility notched gates MOSFET.Comprise the steps: first to provide the heterojunction material with low al composition AlGaN/GaN/ high aluminium component AlGaN lamination barrier layer, at described material surface one layer of dielectric layer of deposition as mask layer, photoetching development technology and wet etching is used to remove area of grid dielectric layer, realize graphical to mask layer, utilize wet-dry change to combine to be removed by the top layer high aluminium component AlGaN of area of grid and obtain groove, GaN thin layer removes groove surfaces damage as wet etching stop layer, and the low al composition AlGaN potential barrier of reservation can realize high channel mobility and high threshold voltage.Threshold voltage is regulated and controled further by depositing p-type oxide as grid.Finally form source electrode and drain region at two ends and cover metal formation source electrode and drain electrode.Present invention process is simple, can solve damage during conventional dry etched recesses caused area of grid well, can form the raceway groove of low two-dimensional electron gas simultaneously, thus obtain high threshold voltage while improving channel mobility.
Description
Technical field
The present invention relates to the technical field of semiconductor epitaxial process, migrate more particularly, to a kind of high threshold voltage height
The preparation method of rate notched gates MOSFET.
Background technology
Gallium nitride (GaN) material has that energy gap is big, breakdown field strength is high, electronics saturation drift velocity is big, thermal conductance
Rate advantages of higher, is very suitable for making high-power, high frequency, high temperature power electronic devices.In applied power electronics field, in order to full
Foot fail safe, field-effect transistor (FET) device must realize normally-off (also known as enhancement mode) work, and in some occasion
Threshold voltage needs at least 4-5V.And for conventional AlGaN/GaN HFET (HFET), due to interface
High concentration, the existence of two-dimensional electron gas (2DEG) of high mobility, even if when additional grid voltage is zero, device is also at opening shape
State (normally on device).In order to solve these problems, the isolated-gate field effect transistor (IGFET) (MOSFET) using MOS structure is one
Effective technology path.
GaN base notched gates MOSFET element is retaining the premise of access area 2DEG concentration (not sacrificing break-over of device characteristic)
Under, grid when removing zero-bias the most completely is reduced by partly or completely etching grid region AlGaN potential barrier
The 2DEG of lower section, and MOS structure grid can be used to achieve normally-off, low-leakage current and the high grid voltage amplitude of oscillation.Part is carved
Erosion barrier layer can be effectively retained electron channel and obtain high field-effect mobility, but the barrier layer meeting of residual and gate metal
And gate dielectric layer forms MOSHFET and reduces threshold voltage.On the contrary, etching barrier layer completely can obtain high threshold voltage,
But electron channel produces between gate dielectric layer and GaN, and strong interface scattering causes field-effect mobility on the low side.Additionally, it is recessed
In groove etched technique, the lattice of channel region can be caused damage by traditional plasma dry etch, although wet etching energy
But effectively remove plasma damage long time treatment and also can observe substantial amounts of etching hole on the surface of GaN channel layer, enter
And affect the reliability and stability at MOS interface.It is therefore desirable to seek the preparation side of a kind of new GaN base notched gates MOSFET
Method, to overcome the shortcoming in traditional handicraft, thus obtains higher mobility and threshold voltage.
Summary of the invention
The present invention is to overcome at least one defect described in above-mentioned prior art, it is provided that a kind of high threshold voltage high mobility
The preparation method of notched gates MOSFET, can be effectively improved channel mobility and threshold voltage.The technical solution used in the present invention
Being: utilize lamination barrier layer construction, GaN interposed layer can remove plasma damage as wet etching stop layer, the most permissible
Retain low al composition AlGaN and form the raceway groove of low two-dimensional electron gas, and combine p-type oxide grid to channel carrier
Concentration regulates and controls, thus obtains high threshold voltage while improving channel mobility.
Specifically include following steps:
S1, at Grown stress-buffer layer；
S2, on stress-buffer layer grow GaN epitaxial layer；
S3, in GaN epitaxial layer grow one layer low al composition AlGaN potential barrier；
S4, in low al composition AlGaN potential barrier deposit one layer of GaN etch stop layer；
S5, on GaN etch stop layer, grow a floor height al composition AlGaN potential barrier；
S6, in AlGaN potential barrier deposit one layer of SiO2, as mask layer；
S7, method by photoetching and wet etching, remove the mask layer of area of grid；
S8, utilize dry/wet method to combine to remove the high aluminium component AlGaN potential barrier of area of grid；
S9, dry etching complete device isolation, clean surface depositing p-type oxide gate；
S10, on source electrode and drain region are deposited with source electrode and drain ohmic contact metal；
S11, form Ohmic contact in groove grids region evaporation metal and p-type oxide.
Concrete, described step S3-S5 grows low al composition AlGaN/GaN/ high aluminium component AlGaN lamination barrier layer
Heterojunction material；In described step S9, channel electrons concentration is modulated by depositing p-type oxide gate, and then regulation and control threshold
Threshold voltage.
Described substrate is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
Described stress-buffer layer is any one of AlN, AlGaN, GaN or combines；Stress buffer layer thickness is 10 nm ~ 5
μm。
Described GaN epitaxial layer is GaN epitaxial layer or the high resistant GaN epitaxial layer of doping, the described doping of involuntary doping
The doped chemical of resistive formation is carbon or ferrum；GaN epitaxial layer thickness is 100 nm ~ 20 μm.
Described AlGaN epitaxial layer is low al composition AlGaN, and AlGaN layer thickness is 0-20 nm, and al composition concentration can
Change at 0-15%.
Described interposed layer is the GaN etch stop layer of high-quality, low-dislocation-density；Stop layer thickness is 0 nm ~ 20nm.
Described AlGaN epitaxial layer is high aluminium component AlGaN, and AlGaN layer thickness is 0-50 nm, and al composition concentration can
Change at 15-40%.
Described AlGaN potential barrier material can also be a kind of or the most several in AlInN, InGaN, AlInGaN, AlN
The combination planted.
In described AlGaN potential barrier, and can also insert an AlN thin layer between GaN layer, thickness is 1-10 nm；
Described p-type oxide gate electrode is high-quality NiO, Cu2The materials such as O, ZnO or a combination thereof, thickness is 1-500
nm；
Source electrode and drain material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/
Ti/TiN alloy；It is Ni/Au alloy, In/Au alloy or Pd/Au alloy that gate electrode thickeies metal material；
AlGaN epitaxial layer in stress-buffer layer in described step S1, the GaN epitaxial layer in step S2, step S3, step S4
In GaN epitaxial layer and the growing method of AlGaN epitaxial layer in step S5 be Metalorganic Chemical Vapor Deposition, molecular beam
Epitaxy contour quality film formation method；In described step S6, the growing method of mask layer is plasma enhanced chemical vapor deposition
Method, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method.
Additionally, it is possible to be summarized as following step:
1. provide and need the AlGaN/GaN/AlGaN heterojunction material carrying out groove grids etching；
2., at described deposited on materials one dielectric layer, form mask layer；
3. on described mask layer, utilize photoetching development technology, manifest area of grid；
4. use chemical solution to remove the mask material of area of grid, retain the mask material in other regions, it is achieved mask layer figure
Shape；
5. under the auxiliary of described mask pattern, it is achieved recess etch.
6. utilize photoetching development technology, manifest area of grid and grow one layer of p-type oxide thin layer.
Further, in described step 1, described substrate is the epitaxial layer substrate with heterogeneity.
In described step 2, dielectric layer is by plasma enhanced chemical vapor deposition or ald or physics
Vapour deposition or magnetron sputtering are formed.Described dielectric layer is SiO2Or SiN.
In described step 3, described photoresist is positivity or negative photoresist.
In described step 4, described dielectric layer remove the chemical solution used be hydrofluoric acid aqueous solution or Fluohydric acid. and
The mixed solution of ammonium fluoride.
In described step 5, described recess etch is inductively coupled plasma (ICP) or reactive ion etching (RIE).
Reacting gas is Cl2、BCl3、SiCl4Or its mixed gas.
In described step 6, described p-type oxide thin layer be grown to Metalorganic Chemical Vapor Deposition, sputtering method,
Thermal oxidation method or molecular beam epitaxy.
Compared with prior art, provide the benefit that: the present invention provides the preparation side of a kind of novel GaN base notched gates MOSFET
Method, owing to utilizing lamination barrier layer construction, GaN interposed layer can remove plasma damage as wet etching stop layer, again
Low al composition AlGaN can be retained and form the raceway groove of low two-dimensional electron gas, and combine p-type oxide grid to raceway groove load
Flow sub-concentration to regulate and control, thus obtain high threshold voltage while improving channel mobility.
Accompanying drawing explanation
Fig. 1-11 is the device manufacture method process schematic representation of the embodiment of the present invention 1.
Figure 12 is the device architecture schematic diagram of the embodiment of the present invention 2.
Figure 13 is the device architecture schematic diagram of the embodiment of the present invention 3.
Detailed description of the invention
Accompanying drawing being merely cited for property explanation, it is impossible to be interpreted as the restriction to this patent；In order to the present embodiment is more preferably described, attached
Scheme some parts to have omission, zoom in or out, do not represent the size of actual product；To those skilled in the art,
In accompanying drawing, some known features and explanation thereof may be omitted and be will be understood by.Being merely cited for property of position relationship described in accompanying drawing
Explanation, it is impossible to be interpreted as the restriction to this patent.
Embodiment 1
Being the device architecture schematic diagram of the present embodiment as shown in figure 11, its structure includes substrate (1) the most successively, and stress delays
Rush layer (2), GaN epitaxial layer (3), low al composition AlGaN potential barrier (4), GaN interposed layer (5), high aluminium component AlGaN potential barrier
(6), p-type oxide grid (7), two ends form source electrode and drain electrode (8), and the upper deposition of oxide gate (7) thickeies metal (9).
The manufacture method of the device field-effect transistor of above-mentioned GaN base notched gates MOSFET as Figure 1-Figure 11, including
Following steps:
S1, utilize mocvd method, at Si substrate (1) upper growth one ply stress cushion (2), such as Fig. 1
Shown in；
S2, utilize mocvd method, stress-buffer layer (2) grows GaN epitaxial layer (3), such as Fig. 2 institute
Show；
S3, utilize mocvd method, grow low al composition AlGaN potential barrier GaN epitaxial layer (3) is upper
(4), as shown in Figure 3；
S4, utilize mocvd method, at low al composition AlGaN potential barrier (4) upper growth GaN interposed layer
(5), as shown in Figure 4；
S5, utilize mocvd method, in GaN interposed layer (5) upper growth high aluminium component AlGaN potential barrier
(6), as shown in Figure 5；
S6, by one layer of SiO of plasma enhanced chemical vapor deposition2, as mask layer (10), as shown in Figure 6；
S7, by photoetching method select region etch, remove the mask layer (10) of area of grid, as shown in Figure 7；
S8, inductively coupled plasma (ICP) or reactive ion etching (RIE) is utilized to remove area of grid high aluminium component AlGaN
Barrier layer (6) forms groove, as shown in Figure 8；
S9, removal mask layer (10), complete device isolation, utilize sputtering method, grow one layer of high-quality p-type oxide thin layer
(7), as shown in Figure 9；
S10, photoetching development go out source electrode and drain ohmic contact region, and on evaporation, Ti/Al/Ni/Au alloy is as source electrode and drain electrode
Metal ohmic contact (8), as shown in Figure 10；
S11, thicken metal (9) as grid, as shown in figure 11 at p-type oxide grid (7) upper evaporation Ni/Au alloy.
So far, the preparation process of whole device is completed.Figure 11 is the device architecture schematic diagram of embodiment 1.
Embodiment 2
Being the device architecture schematic diagram of the present embodiment as shown in figure 12, it differs only in embodiment 1 structure: in embodiment 1
Grid is single oxide, and utilizes two kinds or more of oxide to form stack gate electrode structure in embodiment 2.
Embodiment 3
Being the device architecture schematic diagram of the present embodiment as shown in figure 13, it differs only in embodiment 1 structure: in embodiment 1
Grid is p-type oxide, and embodiment 3 introduces insulating medium layer (11) below p-type oxide gate electrode, and dielectric layer is
Al2O3Or HfO2, thickness is 1-100 nm；Form dielectric layer/oxide stack structure.
Furthermore, it is necessary to explanation, the accompanying drawing of above example merely to the purpose of signal, therefore there is no need by than
Example is drawn.
Obviously, the above embodiment of the present invention is only for clearly demonstrating example of the present invention, and is not right
The restriction of embodiments of the present invention.For those of ordinary skill in the field, the most also may be used
To make other changes in different forms.Here without also cannot all of embodiment be given exhaustive.All at this
Any amendment, equivalent and the improvement etc. made within the spirit of invention and principle, should be included in the claims in the present invention
Protection domain within.
Claims (10)
1. a preparation method for high threshold voltage high mobility notched gates MOSFET, utilizes low al composition AlGaN/GaN/ high alumina
The heterojunction material of component AlGaN lamination barrier layer, specifically includes following steps:
S1, at the upper growth stress cushion (2) of substrate (1)；
S2, growth GaN epitaxial layer (3) on stress-buffer layer；
S3, GaN epitaxial layer (3) one layer low al composition AlGaN potential barrier (4) of upper growth；
S4, low al composition AlGaN potential barrier (4) one layer of GaN etch stop layer (5) of upper deposition；
S5, at GaN etch stop layer (5) upper growth one floor height al composition AlGaN potential barrier (6)；
S6, in AlGaN potential barrier deposit one layer of SiO2, as mask layer (10)；
S7, method by photoetching and wet etching, remove the mask layer (10) of area of grid；
S8, utilize dry/wet method to combine to remove the high aluminium component AlGaN potential barrier (6) of area of grid；
S9, dry etching complete device isolation, clean surface depositing p-type oxide gate (7)；
S10, on source electrode and drain region are deposited with source electrode and drain ohmic contact metal (8)；
S11, form Ohmic contact in groove grids region evaporation metal (9) and p-type oxide.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: described step S3-S5 grows the hetero-junctions material of low al composition AlGaN/GaN/ high aluminium component AlGaN lamination barrier layer
Material；In described step S9, channel electrons concentration is modulated by depositing p-type oxide gate, and then regulation and control threshold voltage.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: described substrate (1) is any one in Si substrate, Sapphire Substrate, silicon carbide substrates, GaN self-supported substrate.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: any one that stress-buffer layer (2) is AlN, AlGaN, GaN described or combination；Stress buffer layer thickness is 10 nm ~ 5
μm。
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: the described GaN epitaxial layer that GaN epitaxial layer (3) is involuntary doping or the high resistant GaN epitaxial layer of doping, described doping
The doped chemical of resistive formation is carbon or ferrum；GaN epitaxial layer thickness is 100 nm ~ 20 μm.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: described AlGaN epitaxial layer (4) is low al composition AlGaN, and AlGaN layer thickness is 0-20 nm, and al composition concentration can
Change at 0-15%.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: the described GaN etch stop layer that interposed layer (5) is high-quality, low-dislocation-density；Stop layer thickness is 0 nm ~ 20nm.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: described AlGaN epitaxial layer (6) is high aluminium component AlGaN, and AlGaN layer thickness is 0-50 nm, and al composition concentration can
Change at 15-40%.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: described AlGaN potential barrier material can also a kind of or the most several in AlInN, InGaN, AlInGaN, AlN
Combination.
The preparation method of a kind of high threshold voltage high mobility notched gates MOSFET the most according to claim 1, its feature
It is: in described AlGaN potential barrier (6), and can also insert an AlN thin layer between GaN layer, thickness is 1-10 nm；
Described p-type oxide gate electrode (7) is high-quality NiO, Cu2The materials such as O, ZnO or a combination thereof, thickness is 1-500
nm；
Source electrode and drain electrode (8) material are Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/
Al/Ti/TiN alloy；It is Ni/Au alloy, In/Au alloy or Pd/Au alloy that gate electrode thickeies metal material (9)；
AlGaN epitaxial layer in stress-buffer layer (2) in described step S1, the GaN epitaxial layer (3) in step S2, step S3
(4), the growing method of the AlGaN epitaxial layer (6) in the GaN epitaxial layer in step S4 (5) and step S5 is Organometallic Chemistry
Vapour deposition process, molecular beam epitaxy contour quality film formation method；In described step S6, the growing method of mask layer (10) is
Gas ions strengthens chemical vapour deposition technique, atomic layer deposition method, physical vaporous deposition or magnetron sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868777.9A CN106298887B (en) | 2016-09-30 | 2016-09-30 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610868777.9A CN106298887B (en) | 2016-09-30 | 2016-09-30 | Preparation method of groove gate MOSFET with high threshold voltage and high mobility |
Publications (2)
| Publication Number | Publication Date |
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| CN108321256A (en) * | 2018-03-29 | 2018-07-24 | 中山大学 | A kind of preparation method based on p-type transparent grid electrode GaN base ultraviolet detector |
| CN108666359A (en) * | 2017-03-29 | 2018-10-16 | 北京大学 | A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer |
| CN108807530A (en) * | 2018-06-19 | 2018-11-13 | 深圳大学 | Heterojunction field effect transistor and preparation method thereof |
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| CN109540988A (en) * | 2018-11-09 | 2019-03-29 | 中山大学 | Based on interdigital groove structure without reference electrode GaN base pH sensor and preparation method thereof |
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| CN109887818B (en) * | 2019-03-13 | 2024-03-12 | 西安众力为半导体科技有限公司 | Electron beam device and manufacturing method thereof |
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