WO2019241905A1 - Heterojunction field effect transistor and preparation method therefor - Google Patents

Heterojunction field effect transistor and preparation method therefor Download PDF

Info

Publication number
WO2019241905A1
WO2019241905A1 PCT/CN2018/091797 CN2018091797W WO2019241905A1 WO 2019241905 A1 WO2019241905 A1 WO 2019241905A1 CN 2018091797 W CN2018091797 W CN 2018091797W WO 2019241905 A1 WO2019241905 A1 WO 2019241905A1
Authority
WO
WIPO (PCT)
Prior art keywords
type
oxide
effect transistor
algan
gan
Prior art date
Application number
PCT/CN2018/091797
Other languages
French (fr)
Chinese (zh)
Inventor
刘新科
王磊
敖金平
Original Assignee
深圳大学
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳大学 filed Critical 深圳大学
Priority to PCT/CN2018/091797 priority Critical patent/WO2019241905A1/en
Publication of WO2019241905A1 publication Critical patent/WO2019241905A1/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the invention belongs to the field of semiconductor technology, and particularly relates to a heterojunction field effect transistor and a preparation method thereof.
  • Cuprous oxide (Cu 2 O) is an excellent group I-IV semiconductor material because it has a direct band gap of 2.1eV and a very high visible light absorption coefficient. In addition, it has non-toxic, low-cost, raw materials Rich and other advantages, it is often used in the preparation of solar cells and photodetector elements. At the same time, Cu 2 O has photocatalytic activity, which can directly use visible light to catalyze the cracking of water to generate hydrogen, which has become the material of choice for energy conservation and environmental protection in the field of hydrogen production. In addition, due to the presence of Cu vacancies in the Cu 2 O crystal structure, Cu 2 O is a p-type semiconductor of this certificate.
  • Cu 2 O has a high mobility, it is often used as a channel material in combination with an n-type semiconductor. For the preparation of thin film transistors (TFTs). Therefore, Cu 2 O will be a thin film material with very important application prospects in the fields of electricity, optics and semiconductors. With its thin-film nanostructure, it is possible to manufacture smaller-sized, more energy-efficient semiconductor chips, making it widely used in the field of nanoelectronic components. In addition, Cu 2 O has important application value in the field of gas monitoring. With the increasing development of semiconductor optoelectronics, Cu 2 O stands out as a natural p-type conductive material.
  • GaN-based LEDs have fully entered the industrialization stage, and GaN-based materials can form AlGaN with a high concentration of two-dimensional electron gas (2DEG) due to its large band gap E g , high electron saturation speed, and good thermal conductivity.
  • 2DEG two-dimensional electron gas
  • the / GaN heterostructure makes GaN-based power electronic devices particularly suitable for use in hostile environments such as high temperatures, high frequencies, high power, and radiation resistance.
  • a conventional method for preparing a p-type Cu 2 O thin film is generally to grow p-type Cu 2 O by thermal oxidation using metal copper.
  • this technology can form p-type Cu 2 O by adjusting the thermal oxidation temperature at a low temperature, it has a very fatal disadvantage. Later, it must be prepared for subsequent processes by photolithography. In this process, Cu 2 O will be oxidized to Copper oxide (CuO) and its surface may also be contaminated or introduce defects, and p-type Cu 2 O grown by the traditional thermal oxidation method often has a hole concentration below 1 ⁇ 10 16 cm -3 .
  • CuO Copper oxide
  • the purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, to provide a heterojunction field effect transistor and a preparation method thereof, and to solve the technical problems of poor threshold voltage regulation ability and low power of the existing GaN heterojunction field effect transistor. .
  • One aspect of the present invention provides a method for preparing a heterojunction field effect transistor, including the following steps:
  • a p-type oxide is deposited on the AlGaN / GaN heteroepitaxial layer by a magnetron sputtering method to prepare a p-type oxide gate.
  • the method for preparing a heterojunction field-effect transistor uses a magnetron sputtering method to deposit a p-type oxide on an AlGaN / GaN heteroepitaxial layer to obtain a p-type oxide gate.
  • the preparation method has a simple process.
  • the p-type oxide can be prevented from being polluted, and a higher-concentration p-type oxide gate can be prepared, and the forward regulation ability of the threshold voltage of the GaN-based heterojunction field effect transistor can be ensured.
  • the device power of the field effect transistor is significantly increased.
  • Another aspect of the present invention provides a heterojunction field effect transistor, which includes an AlGaN / GaN heteroepitaxial layer.
  • the AlGaN / GaN heteroepitaxial layer is provided with an active electrode and a drain electrode; and the AlGaN / GaN heteroepitaxial layer.
  • a p-type oxide gate cap layer structure composed of a p-type oxide is also disposed on the layer.
  • the heterojunction field effect transistor provided by the present invention is a GaN-based heterojunction field effect transistor, in which a p-type oxide gate cap structure composed of a p-type oxide is provided; compared with a traditional Schottky metal gate electrode
  • the p-type oxide direct bandgap semiconductor material can regulate the hole concentration and forbidden band width, which can more effectively adjust the GaN-based heterojunction band structure, and then control the threshold voltage to achieve enhanced (threshold voltage greater than 0) Volt) GaN-based heterojunction field-effect transistor power device; the heterojunction field-effect transistor can reduce unnecessary power loss and the number of devices in the secondary circuit, improve integration, and achieve GaN-based heterojunction field effect The application of transistors in power electronics conversion is of great significance.
  • FIG. 1 is a relationship between hole carrier density, resistivity, and sputtering power of a cuprous oxide thin film in a base heterojunction field effect transistor prepared in Example 1 of the present invention.
  • FIG. 2 is a comparison diagram of transfer characteristics between a GaN heterojunction field effect transistor having a p-type Cu 2 O gate cap structure and a conventional GaN heterojunction field effect transistor prepared in Example 1 of the present invention.
  • an embodiment of the present invention provides a method for manufacturing a heterojunction field effect transistor, including the following steps:
  • a p-type oxide is deposited on the AlGaN / GaN heteroepitaxial layer by a magnetron sputtering method to prepare a p-type oxide gate.
  • a method for manufacturing a heterojunction field effect transistor uses a magnetron sputtering method to deposit a p-type oxide on an AlGaN / GaN heteroepitaxial layer to obtain a p-type oxide gate; the preparation method has a simple process , Not only can prevent the p-type oxide from being contaminated, but also can produce a higher concentration of the p-type oxide gate, and can also ensure the positive control of the threshold voltage of the GaN-based heterojunction field effect transistor.
  • the device power of the QJFET has been significantly improved.
  • the substrate may be sapphire (Sapphire), and the main component is alumina.
  • an etching depth of 120 nm is formed through an inductively coupled plasma (ICP) system to ensure the disappearance of the two-dimensional electron gas channel between the devices and complete the device isolation.
  • the steps of preparing the source electrode and the drain electrode include: depositing Ti / Al / Ti / Au (50/200/40 / 40nm) multilayer metal by magnetron sputtering to complete the preparation of the source electrode and the drain electrode at 850 ° C. Anneal in an N 2 environment for 3 minutes to form an ohmic contact. If the annealing temperature is lower than 850 ° C, ohmic contact cannot be formed well.
  • the optimal source and drain electrodes can be obtained by annealing at this temperature and time.
  • the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide.
  • the embodiments of the present invention innovatively use the magnetron sputtering method to form a high-quality p-type oxide thin film as a gate electrode at a normal temperature and change the sputtering power. After one photolithography, the foregoing is deposited by the magnetron sputtering method. Any one of the p-type oxides is made into a gate, so that a GaN heterojunction field-effect transistor with a high-performance p-type oxide gate cap structure is produced.
  • the p-type oxide is preferably p-type cuprous oxide (Cu 2 O). This preparation method can prevent Cu 2 O from being contaminated with copper oxide (CuO) and Cu 2 O.
  • p-type Cu 2 O gate electrode and subsequent Ni / Au deposition can be deposited by one-time photolithography and magnetron sputtering under normal temperature conditions, which simplifies the process flow and prevents Cu 2 O is contaminated during the preparation process and the problem of lower hole concentration when Cu 2 O is prepared under thermal oxidation conditions is avoided.
  • the step of depositing the p-type oxide includes performing a magnetron sputtering process using a copper target as a copper source and a mixed gas of argon and oxygen as a sputtering gas and a reaction gas. Specifically, the volume ratio of the argon to the oxygen is 15: 3-4.
  • the reaction power of the magnetron sputtering process is 10-100W; the reaction pressure of the magnetron sputtering process is 0.2-0.3Pa.
  • the oxide on the surface of the copper target is removed, and before the reactive sputtering, a step of deoxidizing the copper target surface with argon gas is further included. Specifically, the step of removing the oxide includes: 150-160W
  • the sputtering power is 10-12min.
  • an embodiment of the present invention further provides a heterojunction field effect transistor, which includes an AlGaN / GaN heteroepitaxial layer, and the AlGaN / GaN heteroepitaxial layer is provided with an active electrode and a drain electrode; the AlGaN A / GaN heteroepitaxial layer is further provided with a p-type oxide gate cap structure composed of a p-type oxide.
  • the heterojunction field-effect transistor provided by the embodiment of the present invention is a GaN-based heterojunction field-effect transistor, in which a p-type oxide gate cap structure composed of a p-type oxide is provided; and a conventional Schottky metal gate electrode Compared with the p-type oxide direct bandgap semiconductor material, the adjustable hole concentration and forbidden band width can more effectively adjust the GaN-based heterojunction band structure, and then control the threshold voltage to achieve enhanced (threshold voltage > 0 volts) GaN-based heterojunction field-effect transistor power device; the heterojunction field-effect transistor can reduce unnecessary power loss and the number of devices in the secondary circuit, improve integration, and achieve GaN-based heterojunctions The application of field-effect transistors in power electronics conversion is of great significance.
  • the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide. These p-type oxides can be used to prepare the p-type oxide gate cap structure in the device of the embodiment of the present invention. More preferred is p-type cuprous oxide.
  • a heterojunction field effect transistor includes an AlGaN / GaN heteroepitaxial layer.
  • An active electrode and a drain electrode are disposed on the AlGaN / GaN heteroepitaxial layer.
  • a p is also disposed on the AlGaN / GaN heteroepitaxial layer.
  • Cu 2 O type composed of a p-type Cu 2 O gate cap layer structure.
  • the specific process is as follows:
  • Boil with a mixture of sulfuric acid: hydrogen peroxide 4: 1 at 100 ° C for several minutes, and then clean in a deionized water beaker with deionized water cleaning, acetone ultrasonic cleaning, and ethanol ultrasonic cleaning.
  • the specific process of preparing the source electrode, drain electrode and gate in the device is as follows (all preparation processes are based on the AlGaN / GaN heteroepitaxial structure material on the sapphire substrate to prepare the p-type Cu 2 O gate cap structure GaN Heterojunction Field Effect Transistor):
  • an etching depth of 120 nm is formed by an inductively coupled plasma (ICP) system, and then Ti / Al / Ti / Au (50/200/40 / 40nm) multilayer metals are deposited by magnetron sputtering to complete the source and drain electrodes.
  • ICP inductively coupled plasma
  • Ti / Al / Ti / Au (50/200/40 / 40nm) multilayer metals are deposited by magnetron sputtering to complete the source and drain electrodes.
  • p-type Cu 2 O gate 100nm was deposited by adjusting the argon to oxygen ratio and reaction power by magnetron sputtering, and finally Ni / Au (70 / 30nm) was deposited on it by magnetron sputtering.
  • Ni / Au 70 / 30nm
  • the copper target was surface-treated with argon at a sputtering power of 150 W for 10 minutes.
  • the product obtained under the process conditions of this embodiment is a GaN heterojunction field effect transistor (ie, Cu 2 O / HFET) having a p-type Cu 2 O gate cap structure.
  • the quality of p-type Cu 2 O thin films in the device was evaluated by atomic force microscope (AFM) and Hall test (Hall).
  • a conventional GaN heterojunction field effect transistor is also prepared.
  • the gate leakage current characteristic test results show that, as shown in Figure 2, a GaN heterojunction field effect transistor with a p-type Cu 2 O gate cap structure is better than the gate of a conventional GaN heterojunction field effect transistor. Leakage current is nearly two orders of magnitude smaller. According to the output characteristics of the device, it was found that the output current of the GaN heterojunction field-effect transistor with a p-type Cu 2 O gate cap structure was improved to a certain extent compared with the traditional GaN heterojunction field-effect transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

Provided are a heterojunction field effect transistor and a preparation method therefor. The preparation method comprises the following steps: providing a substrate (S01); preparing an AlGaN/GaN heteroepitaxial layer on the substrate (S02); preparing a source electrode and a drain electrode on the AlGaN/GaN heteroepitaxial layer (S03); and depositing a p-type oxide on the AlGaN/GaN heteroepitaxial layer by means of a magnetron sputtering method to obtain a p-type oxide grid electrode (S04). The preparation method has a simple process, so that a p-type oxide can be prevented from being polluted, a p-type oxide grid electrode with a higher concentration can also be prepared, the capability of positive regulation of a threshold voltage of a GaN-based heterojunction field effect transistor can also be ensured, and finally the device power of the heterojunction field effect transistor is remarkably improved.

Description

异质结场效应晶体管及其制备方法Heterojunction field effect transistor and preparation method thereof
本发明属于半导体技术领域,具体涉及一种异质结场效应晶体管及其制备方法。The invention belongs to the field of semiconductor technology, and particularly relates to a heterojunction field effect transistor and a preparation method thereof.
氧化亚铜(Cu2O)是一种性能优异的I-IV族半导体材料,因为它具有2.1eV的直接带隙以及非常高的可见光吸收系数,再加上它具有无毒、低价、原料丰富等优点,因此多被应用于太阳能电池以及光电探测器元件的制备。同时,Cu2O具有光催化活性,可以直接利用可见光来催化水的裂解产生氢气,成为节能环保产生氢气领域研究的首选材料。另外,由于Cu2O晶体结构中Cu空位的存在,Cu2O为本证p型半导体,因Cu2O具有较高迁移率,所以也常做为沟道材料与n型半导体相结合,用于薄膜晶体管(TFTs)的制备。因此,Cu2O将是一种在电学、光学、半导体领域具有十分重要应用前景的薄膜材料。凭借其薄膜纳米结构,使得制造更小规格、更高能效半导体芯片成为可能,使其在纳米电子元器件领域被广泛应用。此外,Cu2O在气体监测领域也具有重要的应用价值。在半导体光电日益发展的今天,Cu2O更是作为天然p型导电材料脱颖而出。Cuprous oxide (Cu 2 O) is an excellent group I-IV semiconductor material because it has a direct band gap of 2.1eV and a very high visible light absorption coefficient. In addition, it has non-toxic, low-cost, raw materials Rich and other advantages, it is often used in the preparation of solar cells and photodetector elements. At the same time, Cu 2 O has photocatalytic activity, which can directly use visible light to catalyze the cracking of water to generate hydrogen, which has become the material of choice for energy conservation and environmental protection in the field of hydrogen production. In addition, due to the presence of Cu vacancies in the Cu 2 O crystal structure, Cu 2 O is a p-type semiconductor of this certificate. Because Cu 2 O has a high mobility, it is often used as a channel material in combination with an n-type semiconductor. For the preparation of thin film transistors (TFTs). Therefore, Cu 2 O will be a thin film material with very important application prospects in the fields of electricity, optics and semiconductors. With its thin-film nanostructure, it is possible to manufacture smaller-sized, more energy-efficient semiconductor chips, making it widely used in the field of nanoelectronic components. In addition, Cu 2 O has important application value in the field of gas monitoring. With the increasing development of semiconductor optoelectronics, Cu 2 O stands out as a natural p-type conductive material.
继发展实用第一代Ge,Si基器件及第二代SiC,InP基器件后,以GaN基为代表的第三代宽禁带半导体材料的研发引起了科学家们的重视。目前GaN基LED已经完全进入产业化阶段,而GaN基材料凭借其禁带宽度Eg大,电子饱和速度高,导热性好等特点且能形成具有高浓度的二维电子气(2DEG)的AlGaN/GaN异质结构使得GaN基电力电子器件特别适用于高温、高频、大功率、抗辐射等恶略环境。Following the development of practical first-generation Ge, Si-based devices and second-generation SiC, InP-based devices, the research and development of third-generation wide-band-gap semiconductor materials represented by GaN-based has attracted the attention of scientists. At present, GaN-based LEDs have fully entered the industrialization stage, and GaN-based materials can form AlGaN with a high concentration of two-dimensional electron gas (2DEG) due to its large band gap E g , high electron saturation speed, and good thermal conductivity. The / GaN heterostructure makes GaN-based power electronic devices particularly suitable for use in hostile environments such as high temperatures, high frequencies, high power, and radiation resistance.
在半导体技术领域中,传统p型Cu2O薄膜的制备方法一般是利用金属铜通过热氧化法生长p型Cu2O。这种技术虽然可以通过低温调控热氧化温度来形成p型Cu2O,但是却具有非常致命的缺点,后要通过光刻工艺为后续工艺做准备,在这过程中Cu2O会被氧化为氧化铜(CuO)以及其表面也会被污染或是引入缺陷,而且以传统的热氧化法来生长的p型Cu2O往往其空穴浓度低于1×1016cm-3In the field of semiconductor technology, a conventional method for preparing a p-type Cu 2 O thin film is generally to grow p-type Cu 2 O by thermal oxidation using metal copper. Although this technology can form p-type Cu 2 O by adjusting the thermal oxidation temperature at a low temperature, it has a very fatal disadvantage. Later, it must be prepared for subsequent processes by photolithography. In this process, Cu 2 O will be oxidized to Copper oxide (CuO) and its surface may also be contaminated or introduce defects, and p-type Cu 2 O grown by the traditional thermal oxidation method often has a hole concentration below 1 × 10 16 cm -3 .
发明内容Summary of the Invention
本发明的目的在于克服现有技术的上述不足,提供一种异质结场效应晶体管及其制备方法,旨在解决现有GaN异质结场效应晶体管阈值电压调控能力差、功率低的技术问题。The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, to provide a heterojunction field effect transistor and a preparation method thereof, and to solve the technical problems of poor threshold voltage regulation ability and low power of the existing GaN heterojunction field effect transistor. .
为实现上述发明目的,本发明采用的技术方案如下:In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is as follows:
本发明一方面提供一种异质结场效应晶体管的制备方法,包括如下步骤:One aspect of the present invention provides a method for preparing a heterojunction field effect transistor, including the following steps:
提供衬底;Providing a substrate;
在所述衬底上制备AlGaN/GaN异质外延层;Preparing an AlGaN / GaN heteroepitaxial layer on the substrate;
在所述AlGaN/GaN异质外延层上制备源电极和漏电极;Preparing a source electrode and a drain electrode on the AlGaN / GaN heteroepitaxial layer;
利用磁控溅射法在所述AlGaN/GaN异质外延层上沉积p型氧化物,制得p型氧化物栅极。A p-type oxide is deposited on the AlGaN / GaN heteroepitaxial layer by a magnetron sputtering method to prepare a p-type oxide gate.
本发明提供的异质结场效应晶体管的制备方法,采用磁控溅射法在AlGaN/GaN异质外延层上沉积p型氧化物制得p型氧化物栅极;该制备方法工艺简单,既可以避免p型氧化物被污染,又可以实现制备较高浓度的p型氧化物栅极,而且还能保证对GaN基异质结场效应晶体管阈值电压的正向调控能力,最终该异质结场效应晶体管的器件功率得到显著提高。The method for preparing a heterojunction field-effect transistor provided by the present invention uses a magnetron sputtering method to deposit a p-type oxide on an AlGaN / GaN heteroepitaxial layer to obtain a p-type oxide gate. The preparation method has a simple process. The p-type oxide can be prevented from being polluted, and a higher-concentration p-type oxide gate can be prepared, and the forward regulation ability of the threshold voltage of the GaN-based heterojunction field effect transistor can be ensured. The device power of the field effect transistor is significantly increased.
本发明另一方面提供一种异质结场效应晶体管,包括AlGaN/GaN异质外延层,所述AlGaN/GaN异质外延层上设置有源电极和漏电极;所述AlGaN/GaN异质外延层上还设置有p型氧化物组成的p型氧化物栅极帽层结构。Another aspect of the present invention provides a heterojunction field effect transistor, which includes an AlGaN / GaN heteroepitaxial layer. The AlGaN / GaN heteroepitaxial layer is provided with an active electrode and a drain electrode; and the AlGaN / GaN heteroepitaxial layer. A p-type oxide gate cap layer structure composed of a p-type oxide is also disposed on the layer.
本发明提供的异质结场效应晶体管为GaN基异质结场效应晶体管,其中设置有p型氧化物组成的p型氧化物栅极帽层结构;与传统的肖特基金属栅电极相比,p型氧化物直接带隙半导体材料可调控的空穴浓度和禁带宽度等特性更能有效地调节GaN基异质结能带结构,进而调控阈值电压,从而实现增强型(阈值电压大于0伏)的GaN基异质结场效应晶体管的功率器件;该异质结场效应晶体管可减少不必要的功率损耗与次级电路的器件数目,提高集成度,对实现GaN基异质结场效应晶体管在电力电子转化中的应用具有重要意义。The heterojunction field effect transistor provided by the present invention is a GaN-based heterojunction field effect transistor, in which a p-type oxide gate cap structure composed of a p-type oxide is provided; compared with a traditional Schottky metal gate electrode The p-type oxide direct bandgap semiconductor material can regulate the hole concentration and forbidden band width, which can more effectively adjust the GaN-based heterojunction band structure, and then control the threshold voltage to achieve enhanced (threshold voltage greater than 0) Volt) GaN-based heterojunction field-effect transistor power device; the heterojunction field-effect transistor can reduce unnecessary power loss and the number of devices in the secondary circuit, improve integration, and achieve GaN-based heterojunction field effect The application of transistors in power electronics conversion is of great significance.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为本发明实施例1制备的基异质结场效应晶体管中氧化亚铜薄膜的空穴载流子浓度(hole carrier density)和电阻率(resistivity)与溅射功率(sputtering power)的关系曲线图;FIG. 1 is a relationship between hole carrier density, resistivity, and sputtering power of a cuprous oxide thin film in a base heterojunction field effect transistor prepared in Example 1 of the present invention. Graph;
图2为本发明实施例1制备的拥有p型Cu2O栅极帽层结构的GaN异质结场效应晶体管与传统GaN异质结场效应晶体管的转移特性对比图。FIG. 2 is a comparison diagram of transfer characteristics between a GaN heterojunction field effect transistor having a p-type Cu 2 O gate cap structure and a conventional GaN heterojunction field effect transistor prepared in Example 1 of the present invention.
具体实施例方式Specific embodiment mode
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白,以下结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the technical problems, technical solutions, and beneficial effects of the present invention clearer and clearer, the present invention is further described in detail in combination with the embodiments below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.
一方面,本发明实施例提供了一种异质结场效应晶体管的制备方法,包括如下步骤:In one aspect, an embodiment of the present invention provides a method for manufacturing a heterojunction field effect transistor, including the following steps:
S01:提供衬底;S01: providing a substrate;
S02:在所述衬底上制备AlGaN/GaN异质外延层;S02: preparing an AlGaN / GaN heteroepitaxial layer on the substrate;
S03:在所述AlGaN/GaN异质外延层上制备源电极和漏电极;S03: preparing a source electrode and a drain electrode on the AlGaN / GaN heteroepitaxial layer;
S04:利用磁控溅射法在所述AlGaN/GaN异质外延层上沉积p型氧化物,制得p型氧化物栅极。S04: A p-type oxide is deposited on the AlGaN / GaN heteroepitaxial layer by a magnetron sputtering method to prepare a p-type oxide gate.
本发明实施例提供的异质结场效应晶体管的制备方法,采用磁控溅射法在AlGaN/GaN异质外延层上沉积p型氧化物制得p型氧化物栅极;该制备方法工艺简单,既可以避免p型氧化物被污染,又可以实现制备较高浓度的p型氧化物栅极,而且还能保证对GaN基异质结场效应晶体管阈值电压的正向调控能力,最终该异质结场效应晶体管的器件功率得到显著提高。A method for manufacturing a heterojunction field effect transistor provided by an embodiment of the present invention uses a magnetron sputtering method to deposit a p-type oxide on an AlGaN / GaN heteroepitaxial layer to obtain a p-type oxide gate; the preparation method has a simple process , Not only can prevent the p-type oxide from being contaminated, but also can produce a higher concentration of the p-type oxide gate, and can also ensure the positive control of the threshold voltage of the GaN-based heterojunction field effect transistor. The device power of the QJFET has been significantly improved.
进一步地,上述步骤S01中:衬底可以为蓝宝石(Sapphire),主要成分为氧化铝。Further, in the above step S01: the substrate may be sapphire (Sapphire), and the main component is alumina.
进一步地,在上述步骤S03中,制备源电极和漏电极之前,先通过电感耦合等离子体(ICP)系统形成120nm的刻蚀深度,以保证器件间二维电子气沟道的消失,完成器件隔离。而制备源电极和漏电极的步骤包括:利用磁控溅射法沉积Ti/Al/Ti/Au(50/200/40/40nm)多层金属完成源电极与漏电极的制备后,在850℃下N2环境中退火3分钟以形成欧姆接触。如退火温度低于850℃,则不能很好形成欧姆接触,高于850℃会使串联电阻及接触电阻数值增大,影响器件性能;如退火时间低于3分钟,源电极与漏电极金属不能充分与AlGaN外延层反应,不能很好形成欧姆接触,多于3分钟会使接触电阻数值增大,降低影响器件性能。因此,在该温度和时间内退火,可得到最佳的源电极与漏电极。Further, in the above step S03, before preparing the source electrode and the drain electrode, an etching depth of 120 nm is formed through an inductively coupled plasma (ICP) system to ensure the disappearance of the two-dimensional electron gas channel between the devices and complete the device isolation. . The steps of preparing the source electrode and the drain electrode include: depositing Ti / Al / Ti / Au (50/200/40 / 40nm) multilayer metal by magnetron sputtering to complete the preparation of the source electrode and the drain electrode at 850 ° C. Anneal in an N 2 environment for 3 minutes to form an ohmic contact. If the annealing temperature is lower than 850 ° C, ohmic contact cannot be formed well. Above 850 ° C will increase the series resistance and contact resistance value, affecting the device performance; if the annealing time is less than 3 minutes, the source electrode and drain electrode metal cannot It fully reacts with the AlGaN epitaxial layer, and can not form an ohmic contact well. If it is more than 3 minutes, it will increase the contact resistance value and reduce the effect on the device performance. Therefore, the optimal source and drain electrodes can be obtained by annealing at this temperature and time.
进一步地,在上述步骤S04中,所述p型氧化物选自p型氧化铜、p型氧化亚铜、p型氧化镍和p型氧化镁中的任意一种。本发明实施例创新性地利用磁控溅射法在常温下,通过改变溅射功率可以形成高质量的p型氧化物薄膜作为栅极,通过一次光刻后,利用磁控溅射法沉积上述p型氧化物任意一种制成栅极,从而实现制备高性能p型氧化物栅极帽层结构的GaN异质结场效应晶体管。具体地,p型氧化物优选p型氧化亚铜(Cu2O)。该制备方法,可以防止Cu2O被为氧化铜(CuO)以及Cu2O被污染。Further, in the above step S04, the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide. The embodiments of the present invention innovatively use the magnetron sputtering method to form a high-quality p-type oxide thin film as a gate electrode at a normal temperature and change the sputtering power. After one photolithography, the foregoing is deposited by the magnetron sputtering method. Any one of the p-type oxides is made into a gate, so that a GaN heterojunction field-effect transistor with a high-performance p-type oxide gate cap structure is produced. Specifically, the p-type oxide is preferably p-type cuprous oxide (Cu 2 O). This preparation method can prevent Cu 2 O from being contaminated with copper oxide (CuO) and Cu 2 O.
本发明实施例的制备工艺流程可以通过一次光刻以及常温的条件下利用磁控溅射法沉积p型Cu2O栅极与随后的Ni/Au的沉积,这样既简化了工艺流程也防止了Cu2O在制备工艺中污染以及避免了在热氧化条件下制备Cu2O时,空穴浓度较低的问题。In the manufacturing process of the embodiment of the present invention, p-type Cu 2 O gate electrode and subsequent Ni / Au deposition can be deposited by one-time photolithography and magnetron sputtering under normal temperature conditions, which simplifies the process flow and prevents Cu 2 O is contaminated during the preparation process and the problem of lower hole concentration when Cu 2 O is prepared under thermal oxidation conditions is avoided.
进一步地,沉积所述p型氧化物的步骤包括:以铜靶为铜源,以氩气与氧气的混合气体为溅射气体和反应气体,进行磁控溅射处理。具体地,所述氩气与所述氧气的体积比为15:3-4。所述磁控溅射处理的反应功率为10-100W;所述磁控溅射处理的反应压强为0.2-0.3Pa。去除铜靶表面的氧化物,在反应溅射之前,还包括用氩气对所述铜靶表面进行去氧化物处理的步骤;具体地,所述去氧化物处理的步骤包括:以150-160W的溅射功率,通氩气10-12min。Further, the step of depositing the p-type oxide includes performing a magnetron sputtering process using a copper target as a copper source and a mixed gas of argon and oxygen as a sputtering gas and a reaction gas. Specifically, the volume ratio of the argon to the oxygen is 15: 3-4. The reaction power of the magnetron sputtering process is 10-100W; the reaction pressure of the magnetron sputtering process is 0.2-0.3Pa. The oxide on the surface of the copper target is removed, and before the reactive sputtering, a step of deoxidizing the copper target surface with argon gas is further included. Specifically, the step of removing the oxide includes: 150-160W The sputtering power is 10-12min.
另一方面,本发明实施例还提供了一种异质结场效应晶体管,包括AlGaN/GaN异质外延层,所述AlGaN/GaN异质外延层上设置有源电极和漏电极;所述AlGaN/GaN异质外延层上还设置有p型氧化物组成的p型氧化物栅极帽层结构。On the other hand, an embodiment of the present invention further provides a heterojunction field effect transistor, which includes an AlGaN / GaN heteroepitaxial layer, and the AlGaN / GaN heteroepitaxial layer is provided with an active electrode and a drain electrode; the AlGaN A / GaN heteroepitaxial layer is further provided with a p-type oxide gate cap structure composed of a p-type oxide.
本发明实施例提供的异质结场效应晶体管为GaN基异质结场效应晶体管,其中设置有p型氧化物组成的p型氧化物栅极帽层结构;与传统的肖特基金属栅电极相比,p型氧化物直接带隙半导体材料可调控的空穴浓度和禁带宽度等特性更能有效地调节GaN基异质结能带结构,进而调控阈值电压,从而实现增强型(阈值电压大于0伏)的GaN基异质结场效应晶体管的功率器件;该异质结场效应晶体管可以减少不必要的功率损耗与次级电路的器件数目,提高集成度,对实现GaN基异质结场效应晶体管在电力电子转化中的应用具有重要意义。The heterojunction field-effect transistor provided by the embodiment of the present invention is a GaN-based heterojunction field-effect transistor, in which a p-type oxide gate cap structure composed of a p-type oxide is provided; and a conventional Schottky metal gate electrode Compared with the p-type oxide direct bandgap semiconductor material, the adjustable hole concentration and forbidden band width can more effectively adjust the GaN-based heterojunction band structure, and then control the threshold voltage to achieve enhanced (threshold voltage > 0 volts) GaN-based heterojunction field-effect transistor power device; the heterojunction field-effect transistor can reduce unnecessary power loss and the number of devices in the secondary circuit, improve integration, and achieve GaN-based heterojunctions The application of field-effect transistors in power electronics conversion is of great significance.
具体地,上述p型氧化物选自p型氧化铜、p型氧化亚铜、p型氧化镍和p型氧化镁中的任意一种。这些p型氧化物都可用于制备本发明实施例器件中的p型氧化物栅极帽层结构。进一步优选p型氧化亚铜。Specifically, the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide. These p-type oxides can be used to prepare the p-type oxide gate cap structure in the device of the embodiment of the present invention. More preferred is p-type cuprous oxide.
本发明先后进行过多次试验,现举一部分试验结果作为参考对发明进行进一步详细描述,下面结合具体实施例进行详细说明。The present invention has been tested many times in succession, and a part of the test results is used as a reference to further describe the invention in detail. The detailed description is given below in conjunction with specific examples.
实施例1Example 1
一种异质结场效应晶体管,包括AlGaN/GaN异质外延层,所述AlGaN/GaN异质外延层上设置有源电极和漏电极;所述AlGaN/GaN异质外延层上还设置有p型Cu2O组成的p型Cu2O栅极帽层结构。A heterojunction field effect transistor includes an AlGaN / GaN heteroepitaxial layer. An active electrode and a drain electrode are disposed on the AlGaN / GaN heteroepitaxial layer. A p is also disposed on the AlGaN / GaN heteroepitaxial layer. Cu 2 O type composed of a p-type Cu 2 O gate cap layer structure.
该异质结场效应晶体管的制备方法包括如下步骤:The method for preparing the heterojunction field effect transistor includes the following steps:
一、首先将蓝宝石衬底沉积一层AlGaN/GaN异质外延结构材料,将沉积的AlGaN/GaN异质外延结构材料进行清洗,具体过程如下:First, first deposit a layer of AlGaN / GaN heteroepitaxial structure material on the sapphire substrate, and clean the deposited AlGaN / GaN heteroepitaxial structure material. The specific process is as follows:
用硫酸:双氧水=4:1的混合液在100℃煮数分钟,然后依次去离子水清洗、丙酮超声清洗、乙醇超声清洗去离子水烧杯中清洗。Boil with a mixture of sulfuric acid: hydrogen peroxide = 4: 1 at 100 ° C for several minutes, and then clean in a deionized water beaker with deionized water cleaning, acetone ultrasonic cleaning, and ethanol ultrasonic cleaning.
二、器件中源电极、漏电极和栅极的制备具体过程如下(所有制备过程是以蓝宝石衬底上的AlGaN/GaN异质外延结构材料为基础来制备p型Cu2O栅极帽层结构的GaN异质结场效应晶体管):Second, the specific process of preparing the source electrode, drain electrode and gate in the device is as follows (all preparation processes are based on the AlGaN / GaN heteroepitaxial structure material on the sapphire substrate to prepare the p-type Cu 2 O gate cap structure GaN Heterojunction Field Effect Transistor):
首先通过电感耦合等离子体(ICP)系统形成120nm的刻蚀深度,随后通过磁控溅射法沉积Ti/Al/Ti/Au(50/200/40/40nm)多层金属完成源电极与漏电极的制备后,在850℃下N2环境中退火3分钟以形成欧姆接触。然后采用磁控溅射法通过调控氩气与氧气比率以及反应功率沉积p型Cu2O栅极(100nm)后,最后再在其上通过磁控溅射法沉积Ni/Au(70/30nm)以形成栅极欧姆接触。Firstly, an etching depth of 120 nm is formed by an inductively coupled plasma (ICP) system, and then Ti / Al / Ti / Au (50/200/40 / 40nm) multilayer metals are deposited by magnetron sputtering to complete the source and drain electrodes. After the preparation, annealed in an N 2 environment at 850 ° C. for 3 minutes to form an ohmic contact. Then, p-type Cu 2 O gate (100nm) was deposited by adjusting the argon to oxygen ratio and reaction power by magnetron sputtering, and finally Ni / Au (70 / 30nm) was deposited on it by magnetron sputtering. To form a gate ohmic contact.
上述p型Cu2O栅极的制备过程为:使用高纯度铜靶(99.99 %,分析纯)为铜源,以氩气与氧气混合气体为溅射气体与反应气体,制备p型Cu2O栅极;其中,沉积温度为室温,氩气与氧气比率=15:4,反应功率为10W,反应压强为0.2pa。为了去除铜靶表面的氧化物,在反应溅射之前,用150W的溅射功率,通过氩气对铜靶进行表面处理10分钟。The preparation process of the p-type Cu 2 O grid is as follows: a high-purity copper target (99.99%, analytical purity) is used as a copper source, and a mixed gas of argon and oxygen is used as a sputtering gas and a reaction gas to prepare p-type Cu 2 O Grid; where the deposition temperature is room temperature, the ratio of argon to oxygen = 15: 4, the reaction power is 10W, and the reaction pressure is 0.2pa. In order to remove the oxide on the surface of the copper target, before the reactive sputtering, the copper target was surface-treated with argon at a sputtering power of 150 W for 10 minutes.
本实施例的工艺条件得到的产品为拥有p型Cu2O栅极帽层结构的GaN异质结场效应晶体管(即Cu2O/HFET表示)。The product obtained under the process conditions of this embodiment is a GaN heterojunction field effect transistor (ie, Cu 2 O / HFET) having a p-type Cu 2 O gate cap structure.
讨论器件性能之前,用原子力显微镜(AFM)以及霍尔测试(Hall)来评价器件中p型Cu2O薄膜的质量:使用原子力显微镜进行对p型Cu2O薄膜的表面粗糙度进行表征,随着沉积功率的减少,p型Cu2O薄膜表面粗糙度呈现下降的趋势,而且当沉积功率减少到10W,一个准非晶态的p型Cu2O薄膜被形成。同时根据霍尔测试发现,如图1所示,随着沉积功率的减少,空穴浓度呈现上升趋势,特别当沉积功率减少到10W,一个最高的空穴浓度1×1017cm-3被得到。随后根据这个优化的p型Cu2O成膜条件(磁控溅射反应功率=10W),制备p型Cu2O栅极帽层结构的GaN异质结场效应晶体管,以研究它的电学特性。Before discussing device performance, the quality of p-type Cu 2 O thin films in the device was evaluated by atomic force microscope (AFM) and Hall test (Hall). The surface roughness of p-type Cu 2 O thin films was characterized by atomic force microscope. With the decrease of the deposition power, the surface roughness of the p-type Cu 2 O film shows a downward trend. When the deposition power is reduced to 10W, a quasi-amorphous p-type Cu 2 O film is formed. At the same time, according to the Hall test, as shown in Figure 1, as the deposition power decreases, the hole concentration shows an upward trend. Especially when the deposition power is reduced to 10W, a maximum hole concentration of 1 × 10 17 cm -3 is obtained. . Then based on this optimized p-type Cu 2 O film formation conditions (magnetron sputtering reaction power = 10W), a p-type Cu 2 O gate cap structure GaN heterojunction field effect transistor was prepared to study its electrical characteristics. .
为了比较本实施例的器件性能优略性,传统的GaN异质结场效应晶体管也被制备。通过栅极漏电流特性测试结果发现,如图2所示:有p型Cu2O栅极帽层结构的GaN异质结场效应晶体管,要比传统的GaN异质结场效应晶体管的栅极漏电流小近两个数量级。又通过器件的输出特性发现,有p型Cu2O栅极帽层结构的GaN异质结场效应晶体管,比传统的GaN异质结场效应晶体管的输出电流有了一定的提高。同时我们也通过器件转移特性(对数坐标)发现,如图2所示:有p型Cu2O栅极帽层结构的GaN异质结场效应晶体管(图2中Cu2O/HFET),比传统的GaN异质结场效应晶体管(图2中HFET)除了阈值有了0.55V的正向偏移之外,在开关闭ON/OFF特性方面有了两个数量级的提高以及电子迁移率又有了一定的提高,而且亚阈值摆幅(SS)也有了很大的减小。In order to compare the device performance superiority of this embodiment, a conventional GaN heterojunction field effect transistor is also prepared. The gate leakage current characteristic test results show that, as shown in Figure 2, a GaN heterojunction field effect transistor with a p-type Cu 2 O gate cap structure is better than the gate of a conventional GaN heterojunction field effect transistor. Leakage current is nearly two orders of magnitude smaller. According to the output characteristics of the device, it was found that the output current of the GaN heterojunction field-effect transistor with a p-type Cu 2 O gate cap structure was improved to a certain extent compared with the traditional GaN heterojunction field-effect transistor. At the same time, we also found through device transfer characteristics (logarithmic coordinates), as shown in Figure 2: GaN heterojunction field effect transistor with p-type Cu 2 O gate cap structure (Cu 2 O / HFET in Figure 2), Compared with the traditional GaN heterojunction field-effect transistor (HFET in Figure 2), in addition to a threshold shift of 0.55V, it has an improvement of two orders of magnitude in the ON / OFF characteristic and electron mobility. With a certain increase, the sub-threshold swing (SS) has also been greatly reduced.
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。The above description is only the preferred embodiments of the present invention and is not intended to limit the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention shall be included in the protection of the present invention. Within range.

Claims (10)

  1. 一种异质结场效应晶体管的制备方法,其特征在于,包括如下步骤:
    提供衬底;
    在所述衬底上制备AlGaN/GaN异质外延层;
    在所述AlGaN/GaN异质外延层上制备源电极和漏电极;
    利用磁控溅射法在所述AlGaN/GaN异质外延层上沉积p型氧化物,制得p型氧化物栅极。
    A method for preparing a heterojunction field-effect transistor includes the following steps:
    Providing a substrate;
    Preparing an AlGaN / GaN heteroepitaxial layer on the substrate;
    Preparing a source electrode and a drain electrode on the AlGaN / GaN heteroepitaxial layer;
    A p-type oxide is deposited on the AlGaN / GaN heteroepitaxial layer by a magnetron sputtering method to prepare a p-type oxide gate.
  2. 如权利要求1所述的制备方法,其特征在于,所述p型氧化物选自p型氧化铜、p型氧化亚铜、p型氧化镍和p型氧化镁中的任意一种。The method according to claim 1, wherein the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide.
  3. 如权利要求1所述的制备方法,其特征在于,所述p型氧化物为p型氧化亚铜,沉积所述p型氧化物的步骤包括:以铜靶为铜源,以氩气与氧气的混合气体为溅射气体和反应气体,进行磁控溅射处理。The method according to claim 1, wherein the p-type oxide is p-type cuprous oxide, and the step of depositing the p-type oxide includes: using a copper target as a copper source, and argon and oxygen The mixed gas is a sputtering gas and a reaction gas, and is subjected to a magnetron sputtering process.
  4. 如权利要求3所述的制备方法,其特征在于,所述氩气与所述氧气的体积比为15:3-4。The method of claim 3, wherein a volume ratio of the argon gas to the oxygen gas is 15: 3-4.
  5. 如权利要求3所述的制备方法,其特征在于,所述磁控溅射处理的反应功率为10-100W;和/或
    所述磁控溅射处理的反应压强为0.2-0.3Pa。
    The method according to claim 3, wherein the reaction power of the magnetron sputtering process is 10-100W; and / or the reaction pressure of the magnetron sputtering process is 0.2-0.3Pa.
  6. 如权利要求3所述的制备方法,其特征在于,所述磁控溅射处理之前,还包括用氩气对所述铜靶表面进行去氧化物处理的步骤。The method according to claim 3, wherein before the magnetron sputtering treatment, the method further comprises a step of performing an oxide removal treatment on the surface of the copper target with argon.
  7. 如权利要求6所述的制备方法,其特征在于,所述去氧化物处理的步骤包括:以150-160W的溅射功率,通氩气10-12min。The method according to claim 6, wherein the step of deoxidizing treatment comprises: passing a argon gas at a sputtering power of 150-160W for 10-12 minutes.
  8. 如权利要求1-7任一项所述的制备方法,其特征在于,所述衬底为蓝宝石。The preparation method according to any one of claims 1 to 7, wherein the substrate is sapphire.
  9. 一种异质结场效应晶体管,包括AlGaN/GaN异质外延层,所述AlGaN/GaN异质外延层上设置有源电极和漏电极;其特征在于,所述AlGaN/GaN异质外延层上还设置有p型氧化物组成的p型氧化物栅极帽层结构。A heterojunction field-effect transistor includes an AlGaN / GaN heteroepitaxial layer, and an active electrode and a drain electrode are disposed on the AlGaN / GaN heteroepitaxial layer; the AlGaN / GaN heteroepitaxial layer is characterized in that A p-type oxide gate cap structure composed of a p-type oxide is also provided.
  10. 如权利要求9所述的异质结场效应晶体管,其特征在于,所述p型氧化物选自p型氧化铜、p型氧化亚铜、p型氧化镍和p型氧化镁中的任意一种。The heterojunction field effect transistor of claim 9, wherein the p-type oxide is selected from any one of p-type copper oxide, p-type cuprous oxide, p-type nickel oxide, and p-type magnesium oxide Species.
PCT/CN2018/091797 2018-06-19 2018-06-19 Heterojunction field effect transistor and preparation method therefor WO2019241905A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/091797 WO2019241905A1 (en) 2018-06-19 2018-06-19 Heterojunction field effect transistor and preparation method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/091797 WO2019241905A1 (en) 2018-06-19 2018-06-19 Heterojunction field effect transistor and preparation method therefor

Publications (1)

Publication Number Publication Date
WO2019241905A1 true WO2019241905A1 (en) 2019-12-26

Family

ID=68982519

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/091797 WO2019241905A1 (en) 2018-06-19 2018-06-19 Heterojunction field effect transistor and preparation method therefor

Country Status (1)

Country Link
WO (1) WO2019241905A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
CN102945860A (en) * 2012-11-21 2013-02-27 西安电子科技大学 AlGaN/GaN heterojunction enhancement-mode device with in-situ SiN cap layer and production method thereof
CN106298887A (en) * 2016-09-30 2017-01-04 中山大学 A kind of preparation method of high threshold voltage high mobility notched gates MOSFET
CN206441733U (en) * 2016-09-30 2017-08-25 中山大学 A kind of high threshold voltage high mobility notched gates MOSFET structure
CN108807509A (en) * 2018-06-13 2018-11-13 中山大学 A kind of high conduction property P-type grid electrode normally-off HEMT device of high voltage and preparation method thereof
CN208422921U (en) * 2018-06-13 2019-01-22 中山大学 A kind of high conduction property P-type grid electrode normally-off HEMT device of high voltage

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
CN102945860A (en) * 2012-11-21 2013-02-27 西安电子科技大学 AlGaN/GaN heterojunction enhancement-mode device with in-situ SiN cap layer and production method thereof
CN106298887A (en) * 2016-09-30 2017-01-04 中山大学 A kind of preparation method of high threshold voltage high mobility notched gates MOSFET
CN206441733U (en) * 2016-09-30 2017-08-25 中山大学 A kind of high threshold voltage high mobility notched gates MOSFET structure
CN108807509A (en) * 2018-06-13 2018-11-13 中山大学 A kind of high conduction property P-type grid electrode normally-off HEMT device of high voltage and preparation method thereof
CN208422921U (en) * 2018-06-13 2019-01-22 中山大学 A kind of high conduction property P-type grid electrode normally-off HEMT device of high voltage

Similar Documents

Publication Publication Date Title
Pattanasattayavong et al. p-channel thin-film transistors based on spray-coated Cu2O films
CN105474397B (en) Oxide semiconductor substrate and Schottky barrier diode
CN101916773B (en) Double-channel MOS-HEMT (Metal Oxide Semiconductor-High Electron Mobility Transistor) device and manufacturing method
JP2021052203A (en) Oxide semiconductor substrate and Schottky barrier diode
CN106920849B (en) Ga with good heat dissipation performance2O3Base metal oxide semiconductor field effect transistor and preparation method thereof
WO2020253420A1 (en) Gallium oxide sbd terminal structure and preparation method
CN109411328B (en) Preparation method of gallium oxide film with crystallization temperature reduced by doping iron
CN111341839B (en) P-type nitrogen-doped gallium oxide film and preparation method thereof
CN110164769B (en) Gallium oxide field effect transistor and preparation method thereof
Wang et al. Performance optimization of atomic layer deposited ZnO thin-film transistors by vacuum annealing
CN101866860B (en) Preparation method of ZnO thin film field-effect transistor
CN108550624A (en) A kind of high heat dispersion double grid gallium oxide field-effect thin film transistor (TFT) and preparation method thereof
CN106783997B (en) A kind of high mobility transistor and preparation method thereof
CN113594234A (en) Preparation method of low-turn-on-voltage gallium oxide Schottky diode
CN108807530B (en) Heterojunction field effect transistor and preparation method thereof
CN102263166B (en) Method for improving performances of AlGaN-based detector by using nano particles
CN110676167A (en) AlInN/GaN high electron mobility transistor with multi-channel fin structure and manufacturing method
Singh et al. Effect of mesa structure formation on the electrical properties of zinc oxide thin film transistors
CN110911485A (en) Enhanced bidirectional blocking power GaN-based device based on P-type layer and manufacturing method
CN116153933A (en) GaN-based CMOS device and preparation method thereof
WO2019241905A1 (en) Heterojunction field effect transistor and preparation method therefor
CN115763230A (en) P-type gallium oxide film and preparation method and application thereof
CN115377224A (en) Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof
CN110890280B (en) Method for preparing oxide semiconductor Schottky diode by using palladium/palladium oxide double-layer Schottky electrode
TWI698397B (en) Method of purifying silicon carbide powder

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18923680

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 08.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 18923680

Country of ref document: EP

Kind code of ref document: A1