CN115377224A - Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof - Google Patents

Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof Download PDF

Info

Publication number
CN115377224A
CN115377224A CN202211051196.8A CN202211051196A CN115377224A CN 115377224 A CN115377224 A CN 115377224A CN 202211051196 A CN202211051196 A CN 202211051196A CN 115377224 A CN115377224 A CN 115377224A
Authority
CN
China
Prior art keywords
gallium oxide
limiting ring
field limiting
type field
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202211051196.8A
Other languages
Chinese (zh)
Inventor
郑雪峰
洪悦华
张超
张方
何云龙
马晓华
郝跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202211051196.8A priority Critical patent/CN115377224A/en
Publication of CN115377224A publication Critical patent/CN115377224A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention discloses a gallium oxide Schottky diode with a high-breakdown bipolar field limiting ring structure and a preparation method thereof, and mainly solves the problem that the breakdown voltage of the existing similar devices is low. It includes from bottom to top: cathode (1), substrate (2), epitaxial layer (3) and positive pole (6), substrate (2) and epitaxial layer (3) all adopt the gallium oxide material of n type doping, and the positive pole outside of this gallium oxide epitaxial layer (3) upper surface is equipped with p type field limiting ring (4) and n type field limiting ring (5) in proper order, and n type field limiting ring (5) are located the upper portion of p type field limiting ring (4), and both adopt different semiconductor materials to form heterogeneous bipolar structure field limiting ring with the gallium oxide epitaxial layer. Compared with the existing diode, the invention greatly improves the breakdown voltage performance of the device and can be used for high-voltage-withstanding high-power electronic systems.

Description

Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof
Technical Field
The invention belongs to the field of wide bandgap semiconductors, and particularly relates to a high breakdown bipolar field ring structure gallium oxide Schottky diode which can be used for a high-voltage-withstanding high-power electronic system.
Background
Ga 2 O 3 The material has a forbidden bandwidth of 4.9eV, so that a semiconductor device developed based on the material has the characteristic of high breakdown electric field and has great application advantages in the aspect of high working voltage power electronic devices. Ga 2 O 3 The power semiconductor device is used as a potential semiconductor element, plays roles of rectification, amplification and switching in a circuit, can be applied to power supplies of various devices, driving loads and pulse power regulation systems of electronic devices in the future, and has important potential application value in the fields of new energy, rail transit and aerospace. The fields of space electric propulsion and electric energy management put great demands on high-performance power electronic devices, and gallium oxide devices are an important choice for meeting the demands.
The diode is Ga 2 O 3 One of the main research contents of electronic power devices, in the field of high voltage-withstanding and high-power application, a power diode device plays a crucial role. With the continuous progress of technology, higher requirements are put on various aspects of diode performance, especially higher and higher requirements on reverse breakdown voltage and on-resistance. The reverse breakdown voltage and the on-resistance of the diode device directly affect the practical application of the device. Fig. 1 shows a conventional gan schottky diode without a termination structure, in which the breakdown voltage of the device is lower than ideal because the electric field is concentrated at the edge and surface, and the electric field intensity at the edge of the junction is higher than that in the interior of the junction. Gallium oxide power devices currently require the use of appropriate termination structures to reduce the electric field at the edges and surfaces of the semiconductor, thereby increasing the breakdown voltage of the device. Common termination techniques include metalsThe field plate, the field limiting ring, the combination of the field plate and the field limiting ring, the floating metal ring, the groove and the bevel angle structure.
Hiroshi Kono et al published "Improving the specific on-resistance and short-circuit ruggedness of 1.2-kV-class SBD-embedded SiC MOSFETs through cell pitch reduction and internal resistance optimization" at the meeting of 2021 rd International Symposium on Power Semiconductor Devices and Ics, as shown in FIG. 2, the lowest layer of the SiC Schottky diode is the cathode, a silicon carbide substrate is above the cathode, an n-type silicon carbide drift layer is above the silicon carbide substrate, a silicon carbide current spreading layer is above the n-type silicon carbide drift layer, and an anode is above the silicon carbide current spreading layer. P formed by ion implantation at the edge of silicon carbide current spreading layer — Field limiting ring and n + Field limiting ring, wherein n + Field limiting ring at p — Above the field limiting ring. n is a radical of an alkyl radical + Field limiting ring, p — The field limiting ring and the silicon carbide current expansion layer form a homogeneous bipolar field limiting ring structure, and although the structure can reduce the fringe peak electric field and improve the breakdown voltage of the device, the p is manufactured by adopting an ion implantation method — Field limiting ring and n + When the field limiting ring is used, the device is damaged, so that the performance of the device is influenced, and the breakdown voltage of the device with the homogeneous bipolar field limiting ring structure is lower than that of the device with the heterogeneous bipolar field limiting ring structure.
Disclosure of Invention
The present invention aims to overcome the defects of the prior art and provide a high breakdown bipolar field ring structure gallium oxide schottky diode and a preparation method thereof, so as to meet the working requirements of future power electronic devices.
The technical scheme for realizing the purpose of the invention is as follows:
1. a high breakdown bipolar field ring structure gallium oxide Schottky diode comprises from bottom to top: cathode, substrate, epitaxial layer and anode, its characterized in that:
the substrate and the epitaxial layer are both made of n-type doped gallium oxide materials so as to improve the breakdown field strength;
the p-type field limiting ring (4) and the n-type field limiting ring (5) are positioned at the edge of an anode at the upper part of the gallium oxide epitaxial layer (3), the n-type field limiting ring (4) is positioned at the upper part of the p-type field limiting ring, and the p-type field limiting ring (4) and the n-type field limiting ring (5) adopt different semiconductor materials to form a field limiting ring with a hetero-bipolar structure with the gallium oxide epitaxial layer, so that the breakdown voltage of the device is further improved;
further, the p-type field limiting ring is made of any one of nickel oxide, tin oxide, cuprous oxide, silicon carbide and gallium oxide.
Furthermore, the n-type field limiting ring is made of any one of tin oxide, gallium oxide, cuprous oxide, silicon carbide and gallium oxide.
Furthermore, the cathode adopts Ti/Au double-layer metal, the thickness of the first layer of Ti close to the gallium oxide substrate is 10-30 nm, and the thickness of the second layer of Au metal is 150-400 nm.
Furthermore, the thickness of the gallium oxide substrate is 400-650 mu m, and the concentration of effective doping carriers is 10 18 ～10 19 cm-3, and the doping ion species is Si ions.
Furthermore, the thickness of the gallium oxide epitaxial layer is 5-15 μm, and the concentration of doping carriers is 10 15 ～10 17 cm-3, and the doping ion species is Si ions.
Furthermore, the anode adopts Ni/Au double-layer metal, the thickness of the first layer of metal Ni is 45-55 nm, and the thickness of the second layer of metal Au is 300-400 nm.
2. A preparation method of a high-breakdown bipolar field ring structure gallium oxide Schottky diode is characterized by comprising the following steps:
1) Selecting a gallium oxide substrate, and sequentially cleaning the gallium oxide substrate with acetone-isopropanol-deionized water;
2) Growing a gallium oxide epitaxial layer on the front surface of the cleaned gallium oxide substrate by adopting a hydride vapor phase epitaxy technology;
3) Depositing ohmic Ti/Au metal on the back of the gallium oxide substrate by adopting magnetron sputtering under the argon atmosphere to form a cathode, and carrying out ohmic annealing treatment on the cathode;
4) Spin-coating photoresist on the annealed gallium oxide epitaxial layer, photoetching a p-type field limiting ring pattern by utilizing a photoetching technology, placing the gallium oxide epitaxial layer in a magnetron sputtering reaction cavity, opening a target material of a corresponding material, setting the process conditions of the pressure in the cavity being 6-10 mTorr, the environment being 25 ℃, the power being 100-200W, introducing corresponding gas, carrying out magnetron sputtering on the gallium oxide epitaxial layer for 200-300 minutes, and depositing a p-type semiconductor material with the thickness of 90-110 nm;
5) Placing the deposited sample piece into an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid; then, the sample piece boiled with the stripping liquid is sequentially subjected to ultrasonic cleaning by using acetone-isopropanol-deionized water and blow-drying by using nitrogen so as to remove the p-type semiconductor material outside the photoetching pattern area to form a p-type field limiting ring;
6) Spin-coating photoresist on the gallium oxide epitaxial layer and the p-type field limiting ring, photoetching a pattern of the n-type field limiting ring by utilizing a photoetching technology to enable the pattern to be positioned above the p-type field limiting ring, placing a sample piece in a magnetron sputtering reaction cavity, opening a target material of a corresponding material, setting the process conditions of the pressure intensity in the cavity of 6-10 mTorr, the environment temperature of 25 ℃ and the power of 100-200W, introducing corresponding gas, carrying out magnetron sputtering on the gallium oxide epitaxial layer and the p-type field limiting ring for 200-300 minutes, and depositing an n-type semiconductor material with the thickness of 90-110 nm;
7) Placing the sample piece deposited with the n-type semiconductor material in an acetone solution, and ultrasonically cleaning under the condition that the ultrasonic intensity is 2.0; then the sample piece which is cleaned by ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid; then, the sample piece boiled with the stripping liquid is sequentially subjected to ultrasonic cleaning by using acetone-isopropanol-deionized water and blow-drying by using nitrogen so as to remove the n-type semiconductor material outside the photoetching pattern area and form an n-type field limiting ring positioned above the p-type field limiting ring;
8) Forming an anode pattern on the gallium oxide epitaxial layer and the front surface of the n-type field limiting ring by adopting a photoetching process, depositing Ni/Au metal by adopting an electron beam evaporation method according to the anode pattern, and stripping to form an anode to finish the manufacture of the device;
compared with the prior art, the invention has the following advantages:
firstly, the substrate and the epitaxial layer of the invention both adopt n-type doped gallium oxide materials, the forbidden bandwidth is 4.9eV, compared with the forbidden bandwidth of the existing device which uses silicon carbide, the forbidden bandwidth is only 3.4eV, and the breakdown voltage of the device is improved;
secondly, because the n-type field limiting ring and the p-type field limiting ring are manufactured on the surface of the gallium oxide epitaxial layer by adopting a deposition method, compared with the prior art that the n-type field limiting ring and the p-type field limiting ring are manufactured in the epitaxial layer by adopting ion implantation, the damage of the ion implantation to the epitaxial layer is avoided, and the breakdown voltage of the device is improved.
Thirdly, the invention adopts different materials to manufacture the n-type field limiting ring and the p-type field limiting ring to form a heterogeneous bipolar field limiting ring structure, and compared with the prior art which adopts the same material to manufacture a homogeneous bipolar field limiting ring structure, the breakdown voltage of the device is further improved.
Drawings
Fig. 1 is a schematic diagram of a conventional schottky diode structure without a termination structure;
FIG. 2 is a schematic view of a silicon carbide Schottky diode now having a bipolar field ring structure therein;
FIG. 3 is a schematic diagram of a high breakdown bipolar field ring structure of a gallium oxide Schottky diode according to the present invention;
FIG. 4 is a flow chart of the present invention for fabricating the GaN Schottky diode of FIG. 3;
FIG. 5 is a graph comparing forward conduction current of the diode of the present invention with that of a conventional diode;
fig. 6 is a graph comparing the reverse breakdown voltages of the diode of the present invention and the conventional diode.
Detailed Description
In order to more clearly illustrate the technical solution of the present invention, the following describes embodiments and effects of the present invention in detail with reference to the accompanying drawings. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.
Referring to fig. 3, the high breakdown bipolar field ring structured gallium oxide schottky diode of the present invention comprises: cathode 1, gallium oxide substrate 2, n type gallium oxide epitaxial layer 3, p type field limiting ring 4, n type field limiting ring 5 and anode 6, wherein:
the gallium oxide substrate 2 has a thickness of 400 to 650 mu m and a doping concentration of 10 18 ～10 19 cm -3 The doping ion species is Si ions.
The cathode 1 is positioned below the gallium oxide substrate 2, a Ti/Au double-layer metal is adopted, the thickness of a first layer of Ti close to the gallium oxide substrate 2 is 10-30 nm, and the thickness of a second layer of Au metal is 150-400 nm.
The n-type gallium oxide epitaxial layer 3 is positioned above the gallium oxide substrate 2, the thickness of the n-type gallium oxide epitaxial layer is 5-15 mu m, and the doping concentration is 10 15 ～10 17 cm -3 The doping ion species is Si ions.
The p-type field limiting rings 4 and the n-type field limiting rings 5 are positioned on the upper surface of the n-type gallium oxide epitaxial layer 3 and form a bipolar field limiting ring structure.
The p-field limiting ring 4 can be made of any one of nickel oxide, tin oxide, cuprous oxide, silicon carbide and gallium oxide.
The n-type field limiting ring 5 is positioned at the upper part of the p-type field limiting ring 4, and the material of the n-type field limiting ring can be any one of tin oxide, cuprous oxide, silicon carbide and gallium oxide;
the anode 6 is positioned above the n-type field limiting ring 5 and the n-type gallium oxide epitaxial layer 3, and is made of Ni/Au double-layer metal, wherein the thickness of the first layer of metal Ni is 45-55 nm, and the thickness of the second layer of metal Au is 300-400 nm.
Referring to fig. 4, the present invention provides the following three examples of making the device structure of fig. 3:
the first embodiment is as follows: and manufacturing the gallium oxide Schottky diode with the bipolar field limiting ring structure, wherein the n-type field limiting ring layer is made of cuprous oxide material, the thickness of the n-type field limiting ring layer is 100nm, the p-type field limiting ring layer is made of nickel oxide material, and the thickness of the p-type field limiting ring layer is 100 nm.
The method comprises the following steps: the gallium oxide substrate 2 is cleaned.
The effective doping carrier concentration is 10 18 cm -3 The doping ion species is Si ion, and the thickness is 400 μmAnd placing the gallium oxide substrate 2 in acetone-isopropanol-deionized water in sequence, ultrasonically cleaning for 3 minutes under the condition of ultrasonic intensity of 2.0, and then blowing and drying by using nitrogen.
Step two: and preparing an n-type gallium oxide epitaxial layer 3 on the front surface of the cleaned gallium oxide substrate 2 by adopting a hydride vapor phase epitaxy technology.
2.1 In a high-temperature reaction zone of a hydride vapor phase epitaxy vertical reactor, reacting HCl with high-purity metal Ga at a temperature of 800 ℃ to form GaCl and GaCl 3 ；
2.2 GaCl and GaCl produced in the high temperature reaction zone 3 Pushing into low temperature reaction zone, placing gallium oxide substrate with right side up in low temperature reaction zone of hydride vapor phase epitaxy vertical reactor to make GaCl and GaCl 3 Reacting with oxygen at 500 deg.C to form gallium oxide substrate 2 with thickness of 5 μm and doping concentration of 10 16 cm -3 An n-type gallium oxide epitaxial layer 3.
Step three: a cathode ohmic metal 1 was prepared.
Adopting a magnetron sputtering technology, sequentially depositing Ti/Au double-layer metal on the back of the gallium oxide substrate 2 under the conditions that the power is 300W, the sputtering time is 90 minutes, the pressure is 12mtorr and the ambient temperature is 30 ℃, wherein the thickness of the first layer of Ti close to the gallium oxide substrate layer is 30nm, and the thickness of the second layer of Au metal is 400nm, and forming a cathode 1;
and annealing the cathode metal in a nitrogen atmosphere by using an annealing furnace, wherein the annealing temperature is 500 ℃, and the annealing time is 2 minutes.
Step four: the p-type field limiting rings 4 are deposited.
4.1 Spin-coating photoresist on the annealed gallium oxide epitaxial layer 3, photoetching to obtain a p-type field limiting ring pattern by using a photoetching technology, placing the p-type field limiting ring pattern in a magnetron sputtering reaction chamber, opening a target of a nickel material, setting the pressure in the chamber to be 10mTorr, the environment to be 25 ℃, and O 2 Performing magnetron sputtering on the gallium oxide epitaxial layer 3 for 250 minutes under the process conditions that the flow rate of the gas of (1) is 20sccm, the flow rate of the gas of Ar is 9sccm and the power is 200W, and depositing a p-type semiconductor material with the thickness of 100 nm;
4.2 Placing the deposited sample piece into an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then, the sample piece which is cleaned by the ultrasonic is boiled for 15 minutes at the temperature of 60 ℃ by using stripping liquid; and then, ultrasonically cleaning the sample piece which is boiled with the stripping liquid by using acetone-isopropanol-deionized water in sequence, and drying by using nitrogen to remove the p-type semiconductor material outside the photoetching pattern area to form a p-type field limiting ring 4.
Step five: an n-type field limiting ring 5 is deposited.
5.1 Spin-coating photoresist on the gallium oxide epitaxial layer 3 and the p-type field limiting ring 4, photoetching the pattern of the n-type field limiting ring to be positioned above the p-type field limiting ring 4 by utilizing a photoetching technology, placing a sample piece in a magnetron sputtering reaction chamber, polishing a copper target material, setting the pressure in the chamber to be 10mTorr, the environment to be 25 ℃, and O 2 Performing magnetron sputtering on the gallium oxide epitaxial layer 3 and the p-type field limiting ring 4 for 250 minutes under the process conditions that the flow rate of the gas of (1) is 20sccm, the flow rate of the gas of Ar is 3sccm and the power is 200W, and depositing an n-type semiconductor material with the thickness of 100 nm;
5.2 Placing the sample piece deposited with the n-type semiconductor material in an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then, the sample piece which is cleaned by the ultrasonic is boiled for 15 minutes at the temperature of 60 ℃ by using stripping liquid; then, the sample piece boiled with the stripping liquid is sequentially subjected to ultrasonic cleaning by using acetone-isopropanol-deionized water and blow-drying by using nitrogen so as to remove the n-type semiconductor material outside the photoetching pattern area and form an n-type field limiting ring 5 positioned above the p-type field limiting ring 4;
step six: an anode 6 is prepared.
6.1 Photolithography is used to form an anode pattern on the front surfaces of the gallium oxide epitaxial layer 3 and the n-type field limiting ring 5;
6.2 Metal Ni/Au was deposited on the anode pattern using an electron beam evaporation method, and the thickness of the first layer of metal Ni was 45nm and the thickness of the second layer of metal Au was 300nm.
6.3 The photoresist is washed off by adopting N-methyl pyrrolidone solution, namely, the metal material deposited at the position without the photoetching pattern is removed, and the manufacture of the device is finished.
Example two: and tin oxide material is adopted for manufacturing the p-type field limiting ring layer, the thickness of the p-type field limiting ring layer is 100nm, gallium nitride material is adopted for manufacturing the n-type field limiting ring, and the thickness of the n-type field limiting ring layer is 100 nm.
Step 1: the gallium oxide substrate 2 is cleaned.
The effective doping carrier concentration is 10 19 cm -3 The gallium oxide substrate 2 with the doping ion species of Si ions and the thickness of 650 μm was sequentially placed in acetone-isopropanol-deionized water and ultrasonically cleaned for 3 minutes under the condition of ultrasonic intensity of 2.0, and then blown dry with nitrogen.
And 2, step: and preparing an n-type gallium oxide epitaxial layer 3 on the front surface of the cleaned gallium oxide substrate 2 by adopting a hydride vapor phase epitaxy technology.
Firstly, in the high-temperature reaction zone of hydride vapor phase epitaxy vertical reactor, HCl reacts with high-purity metal Ga at the temperature of 900 ℃ to generate GaCl and GaCl 3 And reacting the GaCl and GaCl 3 Pushing into a low-temperature reaction zone;
then placing the gallium oxide substrate with its right side upward in the low-temperature reaction zone of the hydride gas-phase epitaxy vertical reactor to make GaCl and GaCl 3 Reacts with oxygen at 650 deg.C to form a film with a thickness of 15 μm and a doping concentration of 10 on the gallium oxide substrate 2 17 cm -3 Of the n-type gallium oxide epitaxial layer 3.
And step 3: a cathode ohmic metal 1 was prepared.
Adopting a magnetron sputtering technology, under the conditions that the power is 100W, the sputtering time is 30 minutes, the pressure is 6mtorr and the ambient temperature is 25 ℃, sequentially depositing Ti with the thickness of 10nm and Ti with the thickness of 250nmAu on the back surface of a gallium oxide substrate 2 to form a cathode 1 consisting of Ti/Au double-layer metal;
then, the annealing was carried out at 500 ℃ for 3 minutes in a nitrogen atmosphere.
And 4, step 4: a p-type field limiting ring 4 is deposited.
Firstly, spin-coating photoresist on the annealed gallium oxide epitaxial layer 3, photoetching a p-type field limiting ring pattern by utilizing a photoetching technology, placing the pattern in a magnetron sputtering reaction cavity, opening a target of a tin material, wherein the pressure in the cavity is 10mTorr, the environment is 25 ℃, and O is 2 The flow rate of the gas (2) is 8sccm and Ar isPerforming magnetron sputtering on the gallium oxide epitaxial layer 3 for 300 minutes under the process conditions of the flow rate of 16sccm and the power of 200W, and depositing a p-type semiconductor material with the thickness of 110 nm;
then placing the deposited sample piece into an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0;
then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid;
and then, ultrasonically cleaning the sample piece which is boiled with the stripping liquid by using acetone-isopropanol-deionized water in sequence, and drying by using nitrogen to remove the p-type semiconductor material outside the photoetching pattern area to form a p-type field limiting ring 4.
And 5: an n-type field limiting ring 5 is deposited.
Firstly, photoresist is spin-coated on a gallium oxide epitaxial layer 3 and a p-type field limiting ring 4, a pattern of the N-type field limiting ring is photoetched by utilizing a photoetching technology and is positioned above the p-type field limiting ring 4, a sample piece is placed in a magnetron sputtering reaction cavity, a target material of a gallium material is opened, the pressure in the cavity is 6mTorr, the environment is 25 ℃, and N is 2 Performing magnetron sputtering on the gallium oxide epitaxial layer 3 and the p-type field limiting ring 4 for 300 minutes under the process conditions that the flow rate of the gas of (1) is 15sccm, the flow rate of the gas of Ar is 15sccm and the power is 200W, and depositing an n-type semiconductor material with the thickness of 110 nm;
then placing the sample piece deposited with the n-type semiconductor material in an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0;
then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid;
and then, ultrasonically cleaning the sample piece which is boiled with the stripping liquid by using acetone-isopropanol-deionized water in sequence, and drying the sample piece by using nitrogen to remove the n-type semiconductor material outside the photoetching pattern area to form an n-type field limiting ring 5 positioned above the p-type field limiting ring 4.
Step 6: an anode 6 is prepared.
Forming an anode pattern on the front surfaces of the gallium oxide epitaxial layer 3 and the n-type field limiting ring 5 by adopting a photoetching process, and depositing metal Ni/Au on the anode pattern by adopting an electron beam evaporation method, wherein the thickness of the first layer of metal Ni is 55nm, and the thickness of the second layer of metal Au is 400nm; and then, washing off the photoresist by adopting an N-methyl pyrrolidone solution, namely, removing the metal material deposited at the position without the photoetching pattern, and finishing the manufacture of the device.
Example three: and the gallium oxide Schottky diode with the bipolar field limiting ring structure is manufactured, wherein the n-type field limiting ring layer is made of gallium nitride material, the thickness of the gallium nitride layer is 100nm, the p-type field limiting ring layer is made of nickel oxide material, and the thickness of the gallium oxide Schottky diode is 100 nm.
Step A: the gallium oxide substrate 2 is cleaned.
A1 ) with an effective doping carrier concentration of 2X 10 18 cm -3 A gallium oxide substrate 2 having a thickness of 500 μm, in which the doping ion species is Si ions;
a2 Gallium oxide substrate 2 was sequentially placed in acetone-isopropyl alcohol-deionized water, and ultrasonically cleaned for 3 minutes under the condition of ultrasonic intensity of 2.0, and then blown dry using nitrogen gas.
And B: and preparing an n-type gallium oxide epitaxial layer 3 on the front surface of the cleaned gallium oxide substrate 2 by adopting a hydride vapor phase epitaxy technology.
B1 In a high-temperature reaction zone of a hydride vapor phase epitaxy vertical reactor, reacting HCl with high-purity metal Ga at 900 ℃ to form GaCl and GaCl 3 ；
B2 GaCl and GaCl produced in the high temperature reaction zone 3 Pushing into low-temperature reaction zone, placing gallium oxide substrate with right side upward in low-temperature reaction zone of hydride vapor phase epitaxy vertical reactor to make GaCl and GaCl 3 Reacts with oxygen at 650 deg.C to form a film with a thickness of 15 μm and a doping concentration of 10 on the gallium oxide substrate 2 15 cm -3 An n-type gallium oxide epitaxial layer 3.
And C: a cathode ohmic metal 1 was prepared.
Adopting a magnetron sputtering technology, under the process conditions that the power is 200W, the sputtering time is 60 minutes, the pressure is 9mtorr and the ambient temperature is 25 ℃, sequentially depositing Ti/Au double-layer metal on the back surface of the gallium oxide substrate 2, wherein the thickness of the first layer of Ti close to the gallium oxide substrate layer is 20nm, and the thickness of the second layer of Au metal is 300nm, and forming a cathode 1;
and annealing the cathode metal in a nitrogen atmosphere under the annealing conditions that the annealing temperature is 450 ℃ and the annealing time is 2 minutes.
Step D: a p-type field limiting ring 4 is deposited.
D1 Spin-coating photoresist on the annealed gallium oxide epitaxial layer 3, photoetching to obtain a p-type field limiting ring pattern, placing the p-type field limiting ring pattern in a magnetron sputtering reaction chamber, opening a nickel target material at a pressure of 10mTorr and an ambient temperature of 25 deg.C, and introducing O 2 Performing magnetron sputtering on the gallium oxide epitaxial layer 3 for 200 minutes under the process conditions that the flow rate of the gas of (1) is 20sccm, the flow rate of the gas of Ar is 9sccm and the power is 00W, and depositing a p-type semiconductor material with the thickness of 90;
d2 Placing the deposited sample piece into an acetone solution, and firstly carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then, the sample piece which is cleaned by the ultrasonic is boiled for 15 minutes at the temperature of 60 ℃ by using stripping liquid; and then, ultrasonically cleaning the sample piece in which the stripping liquid is boiled by using acetone-isopropanol-deionized water in sequence, and drying the sample piece by using nitrogen to remove the p-type semiconductor material outside the photoetching pattern area to form a p-type field limiting ring 4.
And E, step E: an n-type field limiting ring 5 is deposited.
E1 Spin-coating photoresist on the gallium oxide epitaxial layer 3 and the p-type field limiting ring 4, photoetching the N-type field limiting ring pattern above the p-type field limiting ring 4 by using photoetching technology, placing the sample piece in a magnetron sputtering reaction chamber, opening the target of the gallium material, wherein the pressure in the chamber is 10mTorr, the environment is 25 ℃, and the temperature is N 2 Performing magnetron sputtering on the gallium oxide epitaxial layer 3 and the p-type field limiting ring 4 for 250 minutes under the process conditions that the flow rate of the gas of (1) is 15sccm, the flow rate of the gas of Ar is 15sccm and the power is 200W, and depositing an n-type semiconductor material with the thickness of 90 nm;
e2 Placing the sample piece deposited with the n-type semiconductor material in an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid; and then, the sample piece boiled with the stripping liquid is subjected to ultrasonic cleaning by using acetone-isopropanol-deionized water in sequence and is dried by using nitrogen, so that the n-type semiconductor material outside the photoetching pattern area is removed to form an n-type field limiting ring 5 positioned above the p-type field limiting ring 4.
Step F: an anode 6 is prepared.
F1 Forming an anode pattern on the gallium oxide epitaxial layer 3 and the front surface of the n-type field limiting ring 5 by adopting a photoetching process;
f2 Adopting an electron beam evaporation method to deposit two layers of metal Ni/Au, namely Ni metal with the thickness of 45nm and Au metal with the thickness of 400nm on the anode pattern in sequence; and removing the metal material deposited at the position without the photoetching pattern by using N-methyl pyrrolidone solution to finish the manufacture of the device.
The effect of the invention can be further illustrated by the test results:
test 1: the reverse voltage is set to gradually increase from 0V to 1700V, the reverse voltage is applied to both ends of the diode of the present invention and the gan schottky diode without a termination structure, and the reverse breakdown voltage is determined by testing the magnitude of the reverse current, and the result is shown in fig. 5. As can be seen from fig. 5, the breakdown voltage of the conventional gan schottky diode without the termination structure is only 900V, while the breakdown voltage of the diode of the present invention is 1655V, which is significantly better than that of the conventional gan schottky diode without the termination structure.
And (3) testing 2: the forward voltage of-2V to 4V was set, and the forward voltage was applied to the diode of the present invention and the conventional gan schottky diode without a termination structure, and the magnitude of the forward current was measured, and the result is shown in fig. 6. As can be seen from FIG. 6, the current of the diode of the present invention is 470A/cm under the condition of 4V voltage 2 Is slightly lower than that of the prior gallium oxide Schottky diode 580A/cm without a terminal structure 2 But the breakdown voltage was improved by 83% relative to a conventional gan schottky diode without a termination structure.
The foregoing description is only three specific examples of the present invention and should not be construed as limiting the invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principles and structures of the invention, for example, the p-type semiconductor material used for the field limiting ring may be copper oxide, cuprous oxide, gallium oxide material, or the like in addition to the nickel oxide and tin oxide materials used in the above examples; besides the cuprous oxide and gallium nitride materials in the above embodiment, the n-type semiconductor material can also be copper oxide and gallium oxide materials; the semiconductor deposition is not limited to magnetron sputtering deposition, and laser pulse deposition can also be used; the anode and cathode metal preparation method is not limited to electron beam evaporation, and any one of magnetron sputtering or thermal evaporation can be used, but these modifications and changes based on the inventive idea are still within the protection scope of the claims of the present invention.

Claims (10)

1. A high breakdown bipolar field ring structure gallium oxide Schottky diode comprises from bottom to top: cathode (1), substrate (2), epitaxial layer (3) and anode (6), its characterized in that:
the substrate (2) and the epitaxial layer (3) both adopt n-type doped gallium oxide materials so as to improve the breakdown field strength;
the p-type field limiting ring (4) and the n-type field limiting ring (5) are positioned at the edge of an anode at the upper part of the gallium oxide epitaxial layer (3), the n-type field limiting ring (4) is positioned at the upper part of the p-type field limiting ring, the p-type field limiting ring (4) and the n-type field limiting ring (5) are made of different semiconductor materials, so that a heterogeneous bipolar structure field limiting ring is formed with the gallium oxide epitaxial layer, and the breakdown voltage of the device is further improved.
2. The diode of claim 1, wherein: the p-type field limiting ring (4) is made of any one of nickel oxide, tin oxide, cuprous oxide, silicon carbide and gallium oxide, and the thickness of the p-type field limiting ring is 90-110 nm.
3. The diode of claim 1, wherein: the n-type field limiting ring (5) is made of any one of tin oxide, gallium oxide, cuprous oxide, silicon carbide and gallium oxide, and the thickness of the n-type field limiting ring is 90-110 nm.
4. The diode of claim 1, wherein: the cathode (1) adopts Ti/Au double-layer metal, the thickness of the first layer of Ti close to the gallium oxide substrate is 10-30 nm, and the thickness of the second layer of Au metal is 150-400 nm.
5. The diode of claim 1, wherein: the thickness of the gallium oxide substrate (2) is 400-650 mu m, and the concentration of effective doping carriers is 10 18 ～10 19 cm-3, and the doping ion species is Si ions.
6. The diode of claim 1, wherein: the thickness of the gallium oxide epitaxial layer (3) is 5-15 mu m, and the concentration of doping carriers is 10 15 ～10 17 cm-3, and the doping ion species is Si ions.
7. The diode of claim 1, wherein: the anode (6) is made of Ni/Au double-layer metal, the thickness of the first layer of metal Ni is 45-55 nm, and the thickness of the second layer of metal Au is 300-400 nm.
8. A preparation method of a high-breakdown bipolar field ring structure gallium oxide Schottky diode is characterized by comprising the following steps:
1) Selecting a gallium oxide substrate (2), and sequentially cleaning the gallium oxide substrate with acetone-isopropanol-deionized water;
2) Growing a gallium oxide epitaxial layer (3) on the front surface of the cleaned gallium oxide substrate (2) by adopting a hydride vapor phase epitaxy technology;
3) Depositing ohmic Ti/Au metal on the back of the gallium oxide substrate (2) by adopting magnetron sputtering in an argon atmosphere to form a cathode (1), and carrying out ohmic annealing treatment on the cathode;
4) Spin-coating photoresist on the annealed gallium oxide epitaxial layer (3), photoetching a p-type field limiting ring pattern by utilizing a photoetching technology, placing the pattern into a magnetron sputtering reaction cavity, opening a target material of a corresponding material, setting the process conditions of the pressure in the cavity to be 6-10 mTorr, the environment to be 25 ℃, the power to be 100-200W, introducing corresponding gas, carrying out magnetron sputtering on the gallium oxide epitaxial layer (3) for 200-300 minutes, and depositing a p-type semiconductor material with the thickness of 90-110 nm;
5) Placing the deposited sample piece into an acetone solution, and carrying out ultrasonic cleaning under the condition that the ultrasonic intensity is 2.0; then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid; then, the sample piece boiled with the stripping liquid is sequentially ultrasonically cleaned by acetone-isopropanol-deionized water and dried by nitrogen to remove the p-type semiconductor material outside the photoetching pattern area to form a p-type field limiting ring (4);
6) Spin-coating photoresist on the gallium oxide epitaxial layer (3) and the p-type field limiting ring (4), photoetching a pattern of the n-type field limiting ring by utilizing a photoetching technology to ensure that the pattern is positioned above the p-type field limiting ring (4), placing a sample piece in a magnetron sputtering reaction cavity, opening a target material of a corresponding material, setting the process conditions of the pressure in the cavity to be 6-10 mTorr, the environment temperature to be 25 ℃, the power to be 100-200W, introducing corresponding gas, carrying out magnetron sputtering on the gallium oxide epitaxial layer (3) and the p-type field limiting ring (4) for 200-300 minutes, and depositing an n-type semiconductor material with the thickness of 90-110 nm;
7) Placing the sample piece deposited with the n-type semiconductor material in an acetone solution, and ultrasonically cleaning under the condition that the ultrasonic intensity is 2.0; then the sample piece which is cleaned by the ultrasonic is boiled for 10 to 15 minutes at the temperature of 60 ℃ by using stripping liquid; then, the sample piece boiled with the stripping liquid is sequentially subjected to ultrasonic cleaning by using acetone-isopropanol-deionized water and blow-drying by using nitrogen, so that the n-type semiconductor material outside the photoetching pattern area is removed to form an n-type field limiting ring (5) positioned above the p-type field limiting ring (4);
8) And (3) forming an anode pattern on the front surfaces of the gallium oxide epitaxial layer (3) and the n-type field limiting ring (5) by adopting a photoetching process, depositing Ni/Au metal by adopting an electron beam evaporation method according to the anode pattern, and stripping to form an anode (6), thereby finishing the manufacture of the device.
9. The method of claim 8, wherein: in the step 3), ohmic Ti/Au metal is deposited on the back surface of the gallium oxide substrate by magnetron sputtering to form a cathode (1), and the process conditions are as follows: the power is 150-300W, the sputtering time is 60-90 minutes, the pressure W is 6-12 mtorr, and the ambient temperature is 25 ℃.
10. The method according to claim 8, wherein the step 2) adopts hydride vapor phase epitaxy technique to grow gallium oxide epitaxial layer (3) on the front surface of the cleaned gallium oxide substrate (2) by the following steps:
2a) Introducing ammonia gas into a high-temperature reaction zone of the hydride vapor phase epitaxy vertical reactor, and reacting hydrogen chloride gas with high-purity metal Ga at the temperature of 800-900 ℃ to generate GaCl and GaCl3;
2b) Pushing GaCl and GaCl3 generated in the high-temperature reaction zone into the low-temperature reaction zone, then placing the gallium oxide substrate (2) with the front side facing upwards into the low-temperature reaction zone of the HVPE vertical reactor, and reacting products GaCl and GaCl3 in the high-temperature reaction zone with oxygen at the temperature of 500-650 ℃ to generate an n-type gallium oxide epitaxial layer (3) on the gallium oxide substrate (2).
CN202211051196.8A 2022-08-26 2022-08-26 Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof Pending CN115377224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202211051196.8A CN115377224A (en) 2022-08-26 2022-08-26 Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211051196.8A CN115377224A (en) 2022-08-26 2022-08-26 Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof

Publications (1)

Publication Number Publication Date
CN115377224A true CN115377224A (en) 2022-11-22

Family

ID=84070420

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202211051196.8A Pending CN115377224A (en) 2022-08-26 2022-08-26 Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof

Country Status (1)

Country Link
CN (1) CN115377224A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117613106A (en) * 2024-01-23 2024-02-27 山东大学 High-breakdown-voltage silicon carbide Schottky diode and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117613106A (en) * 2024-01-23 2024-02-27 山东大学 High-breakdown-voltage silicon carbide Schottky diode and preparation method thereof

Similar Documents

Publication Publication Date Title
CN110190129B (en) Field effect transistor and preparation method thereof
CN103579375B (en) SiC Schottky diode and manufacturing method thereof
CN110931570B (en) Gallium nitride Schottky barrier diode and manufacturing method thereof
CN108550622A (en) A kind of gallium nitride schottky barrier diode and its manufacturing method
CN110071177A (en) Schottky diode and preparation method thereof, semiconductor power device
CN110752260A (en) Novel GaN junction barrier Schottky diode and preparation method thereof
CN110137244B (en) Vertical-structure HEMT device with GaN-based self-supporting substrate and preparation method
CN117613106A (en) High-breakdown-voltage silicon carbide Schottky diode and preparation method thereof
CN115411095A (en) SBD structure with dielectric regulation mixed field plate terminal and preparation method thereof
CN110896102B (en) N-type silicon carbide thyristor based on double MOS gate control and preparation method thereof
CN113594234B (en) Preparation method of gallium oxide Schottky diode with low turn-on voltage
CN115377224A (en) Gallium oxide Schottky diode with high-breakdown bipolar field limiting ring structure and preparation method thereof
WO2021139041A1 (en) Gallium oxide schottky diode and preparation method therefor
CN116581151B (en) Low-turn-on voltage gallium oxide Schottky diode and preparation method thereof
CN112909076B (en) Mixed Schottky barrier diode structure with P-type nickel oxide material
CN115312605A (en) Gallium oxide Schottky diode for improving terminal edge peak value electric field and preparation method thereof
CN115312604A (en) Fin-type gallium oxide PN diode with high voltage resistance and low on-resistance and preparation method
CN116666428A (en) Gallium nitride Schottky diode and preparation method thereof
CN115084234A (en) Gallium oxide pn diode based on P-type doping concentration gradually changed from center to periphery and preparation method
CN116093143A (en) Gallium nitride Schottky diode integrating MISFET gate control function and field plate function and manufacturing method thereof
CN115064580A (en) High-voltage-resistance gallium oxide PN junction diode and preparation method thereof
CN115000183A (en) Hybrid array terminal power device and manufacturing method thereof
CN210837767U (en) GaN-based HEMT device
CN111785785A (en) SBD device structure and preparation method thereof
CN205911315U (en) GaN base schottky diode who mixes positive pole electrode structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination