CN115064580A - High-voltage-resistance gallium oxide PN junction diode and preparation method thereof - Google Patents
High-voltage-resistance gallium oxide PN junction diode and preparation method thereof Download PDFInfo
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- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 title claims abstract description 107
- 229910001195 gallium oxide Inorganic materials 0.000 title claims abstract description 107
- 238000002360 preparation method Methods 0.000 title abstract description 6
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims abstract description 44
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- 238000000151 deposition Methods 0.000 claims description 30
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- XOYLJNJLGBYDTH-UHFFFAOYSA-M chlorogallium Chemical compound [Ga]Cl XOYLJNJLGBYDTH-UHFFFAOYSA-M 0.000 claims description 24
- 238000002248 hydride vapour-phase epitaxy Methods 0.000 claims description 24
- 238000001259 photo etching Methods 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 18
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- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
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- 229910021641 deionized water Inorganic materials 0.000 claims description 16
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 claims description 13
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- 238000000137 annealing Methods 0.000 claims description 13
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- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 13
- 229910001887 tin oxide Inorganic materials 0.000 claims description 13
- 150000002500 ions Chemical class 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
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- GNRSAWUEBMWBQH-UHFFFAOYSA-N oxonickel Chemical compound [Ni]=O GNRSAWUEBMWBQH-UHFFFAOYSA-N 0.000 claims description 12
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- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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Abstract
The invention discloses a high-voltage-resistant gallium oxide PN junction diode and a preparation method thereof, and mainly solves the problems that the reverse breakdown voltage of a device cannot be effectively improved and the on-resistance is large in the prior art. It includes from bottom to top: the device comprises cathode metal (1), a gallium oxide substrate (2), a gallium oxide lightly-doped epitaxial layer (3), a semiconductor medium layer (4) and anode metal (5), wherein spin-on glass (SOG) is adopted at two ends of the semiconductor medium layer (4) to serve as edge media, an inverted trapezoidal groove structure is formed in the middle of the upper portion of the gallium oxide lightly-doped epitaxial layer, and p-type semiconductor materials are deposited in the groove to serve as middle-end media to improve an edge peak electric field. The invention improves the breakdown voltage, reduces the on-resistance, improves the withstand voltage of the gallium oxide device, and can be used for electronic systems of communication, power electronics, signal processing and aerospace.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium oxide PN junction diode which can be used for electronic systems of communication, power electronics, signal processing and aerospace.
Technical Field
Gallium oxide, as a new ultra-wide bandgap semiconductor material, has a large bandgap, and thus a high theoretical breakdown field is becoming an interesting research hotspot. With the research progress of material growth, the growth cost of cheap massive single crystals and the increasing epitaxial technology all lead the scale production of gallium oxide materials to be in the initial form and have great development potential. The larger forbidden band width enables the power electronic device to have lower power loss and higher conversion efficiency in application, thereby achieving rapid development.
With the rapid development of the gallium oxide single crystal growth technology and the realization of high-quality epitaxy and controllable n-type doping technology, the gallium oxide has wide application prospects in the field of power electronic devices. Although the maximum breakdown electric field of the currently reported gallium oxide device exceeds the theoretical limit of GaN and SiC, the maximum breakdown electric field is far away from the theoretical limit of gallium oxide, and the voltage resistance of gallium oxide has a great promotion space.
Ma Xiao Hua et al, in patent No. 202111069074.7, disclose "a high breakdown voltage gallium oxide power diode and a method for making the same" using a thin NiO layer with P-type characteristics and beta-Ga 2 O 3 The drift layer forms a heterogeneous PN junction structure to reduce the peak electric field at the edge of the device, improve the interface characteristic of anode metal and gallium oxide, reduce reverse leakage current and improve the breakdown voltage of the gallium oxide diode.
Wang B et al published "High-voltage vertical Ga" on Applied Physics Letters 2 O 3 The power modulators are operated at high temperature up to 600K', which adopts the edge dielectric layer structure with spin-on glass SOG to improve the peak value electric field at the edge of the deviceAnd the breakdown voltage of the gallium oxide diode is improved.
Although the method can improve the reverse breakdown voltage of the device, the improvement effect is limited, the forward on-resistance and the power consumption of the device are increased seriously, and the preparation process of the oblique angle mesa structure is complex and the process is complicated.
Disclosure of Invention
The invention aims to provide a high-voltage-resistant gallium oxide PN junction diode and a preparation method thereof aiming at the defects of the prior art, so as to further improve the reverse breakdown voltage, reduce the forward on-resistance and power consumption of the device and reduce the process complexity.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. a high-voltage-resistance gallium oxide PN junction diode comprises the following components from bottom to top: the device comprises cathode metal, a gallium oxide substrate, a gallium oxide lightly-doped epitaxial layer, a semiconductor medium layer and anode metal, and is characterized in that spin-on glass (SOG) is adopted at two ends of the semiconductor medium layer as edge media to form an inverted trapezoidal groove structure, and a p-type semiconductor material is deposited in the groove to serve as middle-end media so as to improve an edge electric field and improve the breakdown voltage of the device.
Furthermore, the p-type semiconductor material deposited in the groove can be nickel oxide, copper oxide or tin oxide.
Furthermore, the cathode metal is Ti/Au, the thickness of the first layer of Ti close to the gallium oxide substrate is 20-50 nm, and the thickness of the second layer of Au metal is 100-400 nm.
Further, the thickness of the gallium oxide substrate is 300-650 mu m, and the concentration of effective doping carriers is 10 18 ～10 19 cm -3 The doping ion species is Si ions or Sn ions.
Further, the thickness of the gallium oxide lightly doped epitaxial layer is 3-15 mu m, and the concentration of a doped carrier is 10 16 ～10 18 cm -3 。
Further, the PN junction diode anode metal is Ni/Au metal, the thickness of the first layer of metal Ni is 45-60 nm, and the thickness of the second layer of metal Au is 200-400 nm.
2. A manufacturing method of a high-voltage-resistant gallium oxide PN diode is characterized by comprising the following steps:
1) sequentially cleaning the gallium oxide substrate by acetone-isopropanol-deionized water;
2) performing epitaxial light-doped gallium oxide layer on the front side of the cleaned gallium oxide substrate by using a hydride vapor phase epitaxy technology (HVPE) method, depositing ohmic cathode metal on the back side of the gallium oxide substrate by using magnetron sputtering in an argon atmosphere, and performing ohmic annealing on the ohmic cathode metal;
3) depositing a semiconductor medium layer on the gallium oxide epitaxial layer:
3a) spin-coating the spin-coating glass SOG on the surface of the gallium oxide epitaxial layer by using a spin coater;
3b) forming a photoetching pattern on the surface of spin-on glass (SOG) by adopting a photoetching technology, preparing a BOE solution by using 2ml of 49% hydrofluoric acid and 68ml of deionized water, soaking and corroding the spin-on glass (SOG) by using the BOE solution, transferring a mask pattern formed by photoresist onto the spin-on glass (SOG), and forming an inverted trapezoidal groove on a gallium oxide epitaxial layer;
3c) setting magnetron sputtering process conditions: the power is 100W, the ratio of oxygen to argon is 50%, the treatment time is 80-120 minutes, the pressure is 10mtorr, and the ambient temperature is 25 ℃;
3d) depositing a p-type semiconductor material with the thickness of 11-30 nm in the inverted trapezoidal groove by adopting magnetron sputtering, wherein the p-type semiconductor material and the SOG (spin-on glass) at the edge form a semiconductor medium layer with an inverted trapezoidal groove structure together;
4) and forming an anode pattern on the front surface of the semiconductor medium layer by adopting a photoetching process, and depositing and stripping anode metal by adopting electron beam evaporation according to the anode pattern to finish the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
compared with the traditional gallium oxide PN junction diode without an oblique angle dielectric layer structure, the invention adopts the semiconductor dielectric layer with the inverted trapezoid groove structure, so that the peak electric field is mainly concentrated at two ends of the device, the peak electric field can be better reduced, and the breakdown voltage of the device is improved;
secondly, compared with the traditional process for preparing the gallium oxide PN junction diode, the spin-on glass SOG is used as the corrosion mask, and the reverse trapezoidal groove structure can be formed only by wet etching without carrying out multi-step photoetching and etching treatment, so that the preparation process is simple.
Thirdly, the spin-on glass SOG is adopted as the edge dielectric layer, and the breakdown voltage of the device can be further improved due to the fact that the dielectric constant and the critical field intensity of the spin-on glass SOG are large.
Drawings
Fig. 1 is a schematic structural diagram of a gallium oxide PN diode according to the prior art.
Fig. 2 is a schematic structural view of the high-withstand-voltage gallium oxide PN junction diode of the present invention.
Fig. 3 is a flow chart of an implementation of the present invention to fabricate the gan PN junction diode of fig. 2.
The specific implementation mode is as follows:
in order to more clearly illustrate the technical solutions in the embodiments of the present invention, the present invention will be further described with reference to the embodiments and the accompanying drawings used in the technical description of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details.
Referring to fig. 2, the high withstand voltage gallium oxide PN junction diode of the present invention includes: cathode metal 1, gallium oxide substrate 2, gallium oxide lightly doped epitaxial layer 3, semiconductor dielectric layer 4 and anode metal 5. Wherein:
the cathode metal 1 is positioned on the back of the gallium oxide substrate 2, the metal is Ti/Au, the thickness of Ti is 20-50 nm, and the thickness of Au is 100-400 nm;
the thickness of the gallium oxide substrate 2 is 300-650 mu m, and the doping concentration is 10 18 ～10 19 cm -3 ；
The gallium oxide lightly doped epitaxial layer 3 is positioned on the gallium oxide substrate 2, the thickness of the gallium oxide lightly doped epitaxial layer is 3-15 mu m, and the doping concentration is 10 16 ～10 18 cm -3 ；
The semiconductor medium layer 4 is of an inverted trapezoid groove structure and is positioned on the gallium oxide lightly-doped epitaxial layer 3, the edge medium of the semiconductor medium layer 4 is spin-on glass (SOG), a p-type semiconductor material is deposited in the groove and serves as a middle-end medium, and the p-type semiconductor material and the edge SOG jointly form the semiconductor medium layer 4 so as to improve an edge electric field and further improve the breakdown voltage of the device;
the anode metal 5 is located on the semiconductor medium layer 4, the metal is Ni/Au, the thickness of Ni is 45-60 nm, and the thickness of Au is 200-400 nm.
Referring to fig. 3, the present invention provides the following three embodiments for fabricating the device structure of fig. 2:
the first embodiment is as follows: and manufacturing a high-voltage-resistance gallium oxide PN junction diode with a semiconductor medium layer inverted trapezoidal groove with the depth of 11nm and nickel oxide material deposited in the groove.
The method comprises the following steps: and cleaning the gallium oxide substrate material.
The thickness of the gallium oxide substrate 2 is 650 μm, and the effective doping carrier concentration is 2 × 10 18 cm -3 And the doping ion species is Sn ions, acetone-isopropanol-deionized water is respectively used for ultrasonic cleaning for 3 minutes under the condition of ultrasonic intensity of 2.0, and then nitrogen is used for blow drying.
Step two: and preparing a gallium oxide lightly doped epitaxial layer on the front side of the cleaned gallium oxide substrate by adopting a Hydride Vapor Phase Epitaxy (HVPE) technology.
2.1) reacting HCl with highly pure metallic Ga at 850 ℃ in a high-temperature reaction zone of an HVPE vertical reactor to form GaCl and GaCl 3 ；
2.2) reacting GaCl and GaCl formed in the high-temperature reaction zone 3 Pushing into low temperature reaction zone, placing gallium oxide substrate 2 with its front side upward in low temperature reaction zone of HVPE vertical reactor, and making GaCl and GaCl on gallium oxide substrate 3 Reacting with oxygen at 600 deg.C to obtain a film with a thickness of 10 μm and a doping concentration of 2 × 10 16 cm -3 Of gallium oxide epitaxial layer 3.
Step three: and preparing cathode metal.
And depositing metal Ti/Au on the back surface of the gallium oxide substrate 2 by adopting a magnetron sputtering method, wherein the thickness of the first layer of Ti close to the gallium oxide substrate is 20nm, and the thickness of the second layer of Au metal is 400nm, so as to form the cathode metal 1.
Step four: and annealing the ohmic contact metal.
And annealing the cathode metal in a nitrogen atmosphere by using an annealing furnace, wherein the annealing temperature is 470 ℃, and the annealing time is 1 minute.
Step five: and preparing a semiconductor dielectric layer.
5.1) preparing a spin-on glass SOG deposition mask layer:
5.1.1) spin-coating a layer of spin-on glass SOG on the annealed gallium oxide epitaxial layer 3, wherein the spin-on conditions are as follows: rotating speed of a spin coater is 3000rpm, spin coating time is 17s, and after spin coating is finished, baking is carried out for 1 minute by a hot plate at 200 ℃ to form a spin-on-glass SOG mask layer;
5.1.2) preparing a mask pattern on the surface of the spin-on-glass SOG by using a photoetching technology;
5.1.3) preparing a BOE solution by using 2ml of 49% hydrofluoric acid and 68ml of deionized water, soaking a sample piece in the etching solution to etch spin-on glass (SOG), transferring a mask pattern formed by a photoresist to the SOG, and forming an inverted trapezoidal groove with the thickness of 11nm on the gallium oxide epitaxial layer 3;
5.1.4) respectively carrying out ultrasonic cleaning on the sample pieces with the spin-on glass SOG mask layers for 3 minutes by using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, and then carrying out blow-drying by using nitrogen to remove the photoresist on the surface layers of the spin-on glass SOG.
5.2) preparing a nickel oxide dielectric layer:
5.2.1) forming a required nickel oxide deposition pattern on the surface of the spin-on glass SOG by using a photoresist by adopting a photoetching technology;
5.2.2) setting the pressure in the chamber to be 10mTorr, the deposition temperature to be 25 ℃, the power to be 100W, the oxygen concentration in the chamber to be 50 percent, and the gas flow O 2 and/Ar is the process condition of 12/6sccm, a nickel target is used for sputtering for 80 minutes on the nickel oxide deposition pattern, and a nickel oxide dielectric layer with the thickness of 11nm is formed in the inverted trapezoidal groove.
5.2.3) stripping of nickel oxide:
placing the sample piece deposited with the nickel oxide dielectric layer in an acetone solution, and carrying out ultrasonic cleaning for 3 minutes under the condition that the ultrasonic intensity is 2.0; then boiling the sample piece subjected to ultrasonic cleaning for 15 minutes at the temperature of 60 ℃ by using a deposition medium stripping liquid; then, ultrasonically cleaning the sample piece in which the medium stripping liquid is boiled for 3 minutes by sequentially using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, then blowing and drying by using nitrogen, and removing nickel oxide outside the nickel oxide photoetching pattern area;
5.3) forming the semiconductor medium layer 4 by using a nickel oxide medium layer deposited in the middle of the gallium oxide epitaxial layer 3 and spin-on glass SOG spin-coated at the edge of the gallium oxide epitaxial layer 3.
Step six: and preparing anode metal.
6.1) preparing an anode pattern on the surface of the semiconductor medium layer 4 by using photoresist by utilizing a photoetching technology;
6.2) depositing metal Ni/Au on the anode pattern by adopting an electron beam evaporation method, wherein the thickness of the first layer of metal Ni is 45nm, and the thickness of the second layer of metal Au is 400 nm.
And 6.3) washing off the photoresist by adopting an N-methyl pyrrolidone solution, namely removing the metal material deposited on the semiconductor medium layer 4 without the photoetching pattern, and finishing the manufacture of the device.
Example two: and manufacturing a high-voltage-resistance gallium oxide PN junction diode with the semiconductor medium layer and the inverted trapezoidal groove with the thickness of 27nm, and depositing a copper oxide material in the groove.
Step 1: and cleaning the gallium oxide material.
The thickness of the gallium oxide substrate 2 is 600 μm, and the effective doping carrier concentration is 2 × 10 19 cm -3 And the doping ion species is Sn ions, acetone-isopropanol-deionized water is respectively used for ultrasonic cleaning for 3 minutes under the condition of ultrasonic intensity of 2.0, and then nitrogen is used for blow drying.
Step 2: and preparing a gallium oxide lightly doped epitaxial layer on the front side of the cleaned gallium oxide substrate by adopting a Hydride Vapor Phase Epitaxy (HVPE) technology.
Firstly, HCl and high-purity metal Ga are reacted in a high-temperature reaction zone of an HVPE vertical reactor at 8Reacting at 50 ℃ to generate GaCl and GaCl 3 ；
Then, GaCl and GaCl generated in the high temperature reaction zone 3 Pushing into low temperature reaction zone, placing gallium oxide substrate 2 with right side up in HVPE vertical reactor low temperature reaction zone to make GaCl and GaCl 3 Reacting with oxygen at 600 deg.C to form a gallium oxide substrate with a thickness of 8 μm and a doping concentration of 2 × 10 17 cm -3 Of gallium oxide 3.
And step 3: and preparing cathode ohmic metal.
Depositing metal Ti/Au on the back surface of the gallium oxide substrate 2 by adopting a magnetron sputtering method, wherein the thickness of a first layer of Ti close to the gallium oxide substrate is 30nm, and the thickness of a second layer of Au metal is 300nm, so as to form cathode metal 1;
and annealing the cathode metal in a nitrogen atmosphere by using an annealing furnace, wherein the annealing temperature is 470 ℃, and the annealing time is 2 minutes.
And 4, step 4: and preparing a semiconductor dielectric layer.
4a) Preparing a spin-on glass SOG deposition mask layer:
4a1) spin-coating 15s of spin-on glass SOG on the annealed gallium oxide epitaxial layer 3 by using a spin coater at the rotating speed of 2000rpm, and baking for 1 minute on a hot plate at 200 ℃ to form a spin-on glass SOG mask layer;
4a2) preparing a mask pattern on the surface of the spin-on-glass (SOG) by using a photoresist by utilizing a photoetching technology;
4a3) preparing a BOE solution by using 2ml of 49% hydrofluoric acid and 68ml of deionized water, soaking the gallium oxide epitaxial layer in the solution to corrode spin-on-glass (SOG), and transferring a mask pattern formed by the photoresist to the SOG to form an inverted trapezoidal groove with the thickness of 27 nm;
4a4) and respectively carrying out ultrasonic cleaning on the devices with the spin-on glass SOG mask layers for 3 minutes by using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, and then carrying out blow-drying by using nitrogen to remove the photoresist on the surface layers of the spin-on glass SOG.
4b) Preparing a copper oxide dielectric layer:
4b1) and forming a required copper oxide deposition pattern on the surface of the SOG by using photoresist by adopting a photoetching technology.
4b2) Putting the sample piece with the prepared copper oxide deposition pattern into a magnetron sputtering device, wherein the pressure in a cavity is 8mTorr, the deposition temperature is 25 ℃, the power is 100W, the oxygen concentration in the cavity is 50 percent, and the gas flow rate is O 2 And under the process condition that Ar is 12/6sccm, a copper target is used for sputtering for 120 minutes on the copper oxide deposition pattern, and a copper oxide dielectric layer with the thickness of 27nm is formed in the inverted trapezoidal groove.
4b3) Stripping copper oxide:
placing the sample piece deposited with the copper oxide dielectric layer in an acetone solution, and carrying out ultrasonic cleaning for 3 minutes under the condition that the ultrasonic intensity is 2.0; then boiling the sample piece subjected to ultrasonic cleaning for 15 minutes at the temperature of 60 ℃ by using a deposition medium stripping liquid; then, ultrasonically cleaning the sample piece in which the medium stripping liquid is boiled for 3 minutes by sequentially using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, then blowing dry by using nitrogen, and removing copper oxide outside the copper oxide photoetching pattern area;
4c) the semiconductor medium layer 4 is formed by a copper oxide medium layer deposited in the middle of the gallium oxide epitaxial layer 3 and spin-on glass SOG spin-coated on the edge of the gallium oxide epitaxial layer 3.
And 5: and preparing anode metal.
5a) Preparing an anode pattern on the surface of the semiconductor medium layer 4 by using photoresist by utilizing a photoetching technology;
5b) and depositing metal Ni/Au on the anode pattern by adopting an electron beam evaporation method, wherein the thickness of the first layer of metal Ni is 50nm, and the thickness of the second layer of metal Au is 300 nm.
5c) And (3) washing off the photoresist by adopting an N-methyl pyrrolidone solution, namely removing the metal material deposited on the non-photoetching pattern position on the semiconductor medium layer 4 to finish the manufacture of the device.
Example three: and manufacturing a high-voltage-resistance gallium oxide PN junction diode with the semiconductor medium layer inverted trapezoidal groove with the thickness of 18nm and tin oxide material deposited in the groove.
Step A: and cleaning the gallium oxide material.
The thickness of the gallium oxide substrate 2 is 300 μm, and the effective doping is performedHetero carrier concentration of 1X 10 19 cm -3 And the doping ion species is Sn ions, acetone-isopropanol-deionized water is respectively used for ultrasonic cleaning for 3 minutes under the condition of ultrasonic intensity of 2.0, and then nitrogen is used for blow drying.
And B: and preparing a gallium oxide lightly doped epitaxial layer on the front side of the cleaned gallium oxide substrate by adopting a Hydride Vapor Phase Epitaxy (HVPE) technology.
B1) Reacting HCl with high purity metal Ga at 850 ℃ in a high temperature reaction zone of an HVPE vertical reactor to produce GaCl and GaCl 3 ；
B2) Reacting GaCl and GaCl generated in the high-temperature reaction zone 3 Pushing into low temperature reaction zone, placing gallium oxide substrate 2 with right side up in HVPE vertical reactor low temperature reaction zone to make GaCl and GaCl 3 Reacting with oxygen at 600 deg.C to form a gallium oxide substrate with a thickness of 9 μm and a doping concentration of 1 × 10 16 cm -3 Of gallium oxide epitaxial layer 3.
And C: and preparing cathode ohmic metal.
And depositing metal Ti/Au on the back of the gallium oxide substrate 2 by adopting a magnetron sputtering method to form cathode metal 1 with the thickness of 390nm, wherein the thickness of the first layer of Ti close to the gallium oxide substrate is 40nm, and the thickness of the second layer of Au metal is 350 nm.
Step D: and annealing the ohmic contact metal.
And (3) annealing the cathode metal by using an annealing furnace under the nitrogen atmosphere and under the process conditions that the annealing temperature is 500 ℃ and the annealing time is 1 minute.
Step E: and preparing a semiconductor dielectric layer.
E1) Preparing a spin-on glass SOG deposition mask layer:
e1.1) spin-coating a layer of spin-on glass (SOG) on the annealed gallium oxide epitaxial layer 3, wherein the spin-on conditions are as follows: the rotating speed of a spin coater is 3000rpm, the spin coating time is 15s, and after the spin coating is finished, hot plate baking at 200 ℃ is carried out for 1 minute;
e1.2) preparing a mask pattern on the surface of the spin-on-glass (SOG) by using a photoresist by utilizing a photoetching technology;
e1.3) preparing a BOE solution by using 2ml of 49% hydrofluoric acid and 68ml of deionized water, soaking the sample piece with the mask pattern in the solution to corrode spin-on-glass (SOG), so that the mask pattern formed by the photoresist is transferred to the SOG to form an inverted trapezoidal groove structure with the thickness of 18 nm;
e1.4) respectively carrying out ultrasonic cleaning on the sample pieces with the spin-on glass SOG mask layers for 3 minutes by using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, and then carrying out blow-drying by using nitrogen to remove the photoresist on the surface layers of the spin-on glass SOG.
E2) Preparing a tin oxide dielectric layer:
e2.1) using photolithography to form the desired tin oxide deposition pattern on the surface of the spin-on-glass SOG using a photoresist.
E2.2) putting the sample piece with the prepared tin oxide deposition pattern into a magnetron sputtering device, setting the pressure of 10mTorr in a cavity, the deposition temperature of 25 ℃, the power of 100W, the oxygen concentration of 55 percent in the cavity and the gas flow O 2 and/Ar is the process condition of 12/6sccm, a tin target is used for sputtering for 90 minutes on the tin oxide deposition pattern, and a tin oxide dielectric layer with the thickness of 18nm is formed in the inverted trapezoidal groove.
E2.3) tin oxide stripping:
placing the sample piece deposited with the tin oxide dielectric layer in an acetone solution, and carrying out ultrasonic cleaning for 3 minutes under the condition that the ultrasonic intensity is 2.0; then boiling the sample piece subjected to ultrasonic cleaning for 15 minutes at the temperature of 60 ℃ by using a deposition medium stripping liquid;
e2.4) carrying out ultrasonic cleaning on the sample piece in which the medium stripping liquid is boiled for 3 minutes by sequentially using acetone-isopropanol-deionized water under the condition of ultrasonic intensity of 2.0, then using nitrogen to blow dry, and removing tin oxide outside the tin oxide photoetching pattern area;
e2.5) forming the semiconductor dielectric layer 4 by using the tin oxide dielectric layer in the middle of the gallium oxide epitaxial layer 3 and the spin-on glass SOG at the edge of the gallium oxide epitaxial layer 3.
Step F: and preparing anode metal.
By utilizing the photoetching technology, firstly preparing an anode pattern on the surface of the semiconductor medium layer 4 by using photoresist A; sequentially depositing Ni metal with the thickness of 45nm and Au with the thickness of 400nm on the anode pattern by adopting an electron beam evaporation method to form anode metal; and finally, washing off the photoresist by adopting an N-methyl pyrrolidone solution, namely removing the metal material deposited on the non-photoetching pattern position on the semiconductor medium layer 4 to finish the manufacture of the device.
The foregoing description is only three specific examples of the present invention and is not intended to limit the present invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the present invention, for example, any of P-type, N-type or neutral SOG can be used for the selection of spin-on glass SOG; the oxide material can be any one of nickel oxide, copper oxide and tin oxide; the deposition of the oxide medium is not limited to magnetron sputtering deposition, and laser pulse deposition can also be used; the preparation method of the anode metal and the cathode metal is not limited to electron beam evaporation, and any method of magnetron sputtering, thermal evaporation and the like can be used; such modifications and variations that are based on the inventive idea are intended to be within the scope of the appended claims.
Claims (10)
1. A high-voltage-resistance gallium oxide PN junction diode comprises the following components from bottom to top: the device comprises cathode metal (1), a gallium oxide substrate (2), a gallium oxide lightly-doped epitaxial layer (3), a semiconductor medium layer (4) and anode metal (5), and is characterized in that spin-on glass (SOG) is adopted at two ends of the semiconductor medium layer (4) to serve as edge media to form an inverted trapezoidal groove structure, and p-type semiconductor materials are deposited in the groove to serve as middle-end media so as to improve an edge electric field and further improve the breakdown voltage of the device.
2. The diode of claim 1, wherein the thickness of the semiconductor medium layer (4) of the inverted trapezoid groove structure is 11-27 nm, and the p-type semiconductor material deposited in the groove can be nickel oxide, copper oxide or tin oxide.
3. The diode of claim 1, wherein the cathode metal (1) is Ti/Au, and the first layer of Ti near the gallium oxide substrate (2) has a thickness of 20 to 50nm and the second layer of Au metal has a thickness of 100 to 400 nm.
4. The diode according to claim 1, wherein the gallium oxide substrate (2) has a thickness of 300 to 650 μm and an effective doping carrier concentration of 10 18 ～10 19 cm -3 The doping ion species is Si ions or Sn ions.
5. The diode according to claim 1, wherein the thickness of the lightly doped epitaxial layer (3) of gallium oxide is 3-15 μm, and the concentration of the doping carrier is 10 16 ～10 18 cm -3 。
6. The diode of claim 1, wherein the PN junction diode anode metal (6) is Ni/Au metal, and the first layer of metal Ni has a thickness of 45 to 60nm and the second layer of metal Au has a thickness of 200 to 400 nm.
7. A manufacturing method of a high-voltage-resistant gallium oxide PN diode is characterized by comprising the following steps:
1) sequentially cleaning the gallium oxide substrate (2) by acetone-isopropanol-deionized water;
2) performing epitaxial light-doped gallium oxide layer (3) on the front surface of the cleaned gallium oxide substrate (2) by using hydride vapor phase epitaxy technology HVPE (high voltage vapor deposition) method, depositing ohmic cathode metal (1) on the back surface of the gallium oxide substrate by using magnetron sputtering under argon atmosphere, and performing ohmic annealing on the ohmic cathode metal (1);
3) depositing a semiconductor dielectric layer (4) on the gallium oxide epitaxial layer (3):
3a) spin-coating the spin-coating glass SOG on the surface of the gallium oxide epitaxial layer (3) by using a spin coater;
3b) forming a photoetching pattern on the surface of the spin-on glass SOG by adopting a photoetching technology, preparing a BOE solution by using 2ml of 49% hydrofluoric acid and 68ml of deionized water, soaking and corroding the spin-on glass SOG by using the BOE solution to transfer a mask pattern formed by a photoresist onto the spin-on glass SOG to form an inverted trapezoidal groove structure;
3c) setting magnetron sputtering process conditions: the power is 100W, the ratio of oxygen to argon is 50%, the treatment time is 80-120 minutes, the pressure is 10mtorr, and the ambient temperature is 25 ℃;
3d) depositing a p-type semiconductor material with the thickness of 11-30 nm in the inverted trapezoidal groove by adopting magnetron sputtering, wherein the p-type semiconductor material and the SOG (spin-on glass) on the edge form a semiconductor medium layer (4);
4) and forming an anode pattern on the front surface of the semiconductor medium layer (4) by adopting a photoetching process, and depositing and stripping anode metal (5) by adopting electron beam evaporation according to the anode pattern to finish the manufacture of the device.
8. The method according to claim 7, characterized in that, in the step 2), the hydride vapor phase epitaxy HVPE technique is adopted to perform epitaxial light doping on the gallium oxide layer (3) on the front surface of the cleaned gallium oxide substrate (2), and the following is realized:
2a) setting hydride vapor phase epitaxy HVPE process conditions: in the atmosphere of ammonia gas, reacting hydrogen chloride gas with high-purity metal Ga at the temperature of 800-900 ℃ in a high-temperature reaction zone of a hydride vapor phase epitaxy HVPE vertical reactor to generate GaCl and GaCl 3 ；
2b) Putting the cleaned gallium oxide substrate (2) into an HVPE vertical reactor;
2c) GaCl and GaCl generated in the high-temperature reaction zone 3 Pushing the substrate into a low-temperature reaction zone, placing the gallium oxide substrate (2) in the HVPE vertical reactor with the front side facing upwards into the low-temperature reaction zone, and enabling products GaCl and GaCl in the high-temperature reaction zone to be at the temperature of 500-650 DEG C 3 Reacts with oxygen to form an epitaxial layer (3) of gallium oxide on the gallium oxide substrate (2).
9. The method as claimed in claim 7, wherein in the step 2), magnetron sputtering is adopted to deposit ohmic cathode metal on the back of the gallium oxide substrate, and the process conditions are as follows: the power is 100-300W, the sputtering time is 30-90 minutes, the pressure is 6-12 mtorr, and the ambient temperature is 25 ℃.
10. The method of claim 7, wherein the annealing of the ohmic cathode metal in step 2) is performed in a nitrogen atmosphere at an annealing temperature of 400 to 500 ℃ for 1 to 3 minutes.
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