CN110752260A - Novel GaN junction barrier Schottky diode and preparation method thereof - Google Patents

Novel GaN junction barrier Schottky diode and preparation method thereof Download PDF

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CN110752260A
CN110752260A CN201911050585.7A CN201911050585A CN110752260A CN 110752260 A CN110752260 A CN 110752260A CN 201911050585 A CN201911050585 A CN 201911050585A CN 110752260 A CN110752260 A CN 110752260A
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epitaxial layer
gan epitaxial
type gan
schottky diode
comb
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黎大兵
刘新科
孙晓娟
贾玉萍
石芝铭
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66143Schottky diodes

Abstract

The novel GaN junction barrier Schottky diode and the preparation method thereof provide a new way for improving the performance of the Schottky diode by utilizing novel design and relatively simple and easy-to-achieve process. Novel GaN junction barrier Schottky diode, the diode includes by lower to last in proper order: cathode, substrate, n+A type GaN epitaxial layer, an n-type GaN epitaxial layer, a high resistance region formed by annularly injecting plasma on the outer edge of the n-type GaN epitaxial layer, a comb-shaped p+A type GaN epitaxial layer and an anode. According to the method, p-type GaN does not need to be regrown in the n-type GaN layer and a subsequent activation process, so that the process difficulty and complexity are greatly reduced. Through the 4-layer epitaxial GaN structure, good ohmic contact and better PN junction can be formed, the forward on-resistance is reduced, the reverse breakdown voltage is increased, and the performance of the device is effectively improved. In addition, N2The high-resistance region formed by the Plasma can effectively inhibit the breakdown of the device at the edge of the electrode under high voltage, and the breakdown performance is enhanced.

Description

Novel GaN junction barrier Schottky diode and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a novel GaN junction barrier Schottky diode and a preparation method thereof.
Background
In recent years, high importance and wide application are brought to the improvement of the efficiency of a circuit system due to the low conduction voltage drop and the extremely short reverse recovery time of a Schottky Barrier Diode (SBD). The conventional schottky diode has the following defects: (1) the forward voltage drop V of the Schottky rectifier is close to 200V due to the reverse blocking capabilityFWill approach the forward voltage drop of the PIN rectifier and therefore the reverse blocking voltage of conventional schottky barrier diodes is typically below 200V, making them less efficient in application. (2) The reverse leakage current of the conventional schottky diode is large and sensitive to temperature, and the junction temperature of the conventional schottky diode is between 125 ℃ and 175 ℃.
Based on the above defects, a Junction Barrier Schottky (JBS) becomes a hot point of research as an enhancement Schottky, and a Junction Barrier Schottky structure is typically characterized in that a plurality of PN junctions integrated on an epitaxial layer of a conventional Schottky diode are comb-shaped. The Schottky contact part of the junction barrier Schottky diode is conducted when the junction barrier Schottky diode is in zero bias and forward bias, and the PN junction part is not conducted; when the junction barrier Schottky diode is reversely biased, a PN junction depletion region is widened to pinch off a current channel, so that the Schottky barrier lowering effect is effectively inhibited, and the reverse leakage current is effectively controlled. The junction barrier schottky diode has the outstanding advantage of possessing the on-state and fast switching characteristics of the schottky barrier diode, as well as the off-state and low leakage current characteristics of the PIN diode.
The conventional JBS device needs to etch an n-type epitaxial layer and then regrow a p-type epitaxial layer in the n-type epitaxial layer, and needs to anneal for many times at the temperature of 1100 ℃ to complete the activation of the p-type epitaxial layer, so that the process difficulty and complexity of the device are greatly increased, and the development of a gallium nitride-based JBS structure device is limited. In addition, similar to a Schottky Barrier Diode (SBD), the electric field intensity at the positive electrode edge of the JBS is high, easily causing reverse breakdown of the device.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a novel GaN junction barrier Schottky diode and a preparation method thereof, and provides a new way for improving the performance of the Schottky diode by utilizing a novel design and a relatively simple and easily achieved process.
The technical scheme adopted by the invention for solving the technical problem is as follows:
novel GaN junction barrier Schottky diode, the diode includes by lower to last in proper order: cathode, substrate, n+A type GaN epitaxial layer, an n-type GaN epitaxial layer, a high resistance region formed by annularly injecting plasma on the outer edge of the n-type GaN epitaxial layer, a comb-shaped p+A type GaN epitaxial layer and an anode.
Preferably, the substrate is made of: gallium nitride, silicon, and silicon carbide substrates.
Preferably, said n+Type GaN epitaxial layer, n-type GaN epitaxial layer, comb-shaped p-type GaN epitaxial layer and comb-shaped p+The growth method of the GaN epitaxial layer is organic chemical vapor deposition or hydride vapor phase epitaxy.
Preferably, said n+The thickness of the GaN epitaxial layer is 2 μm, and the carrier concentration is about 1.5x1018cm-3(ii) a The thickness of the n-type GaN epitaxial layer is 23 μm, and the carrier concentration is about 8x1015cm-3(ii) a The thickness of the comb-shaped p-type GaN epitaxial layer is 500nm, and the carrier concentration is about 1.5x1018cm-3(ii) a Comb-shaped p+The thickness of the GaN epitaxial layer is 30nm, and the carrier concentration is about 1.5x1020cm-3
Preferably, the plasma is N2Or Ar.
Preferably, the cathode is formed by evaporating a metal film by thermal evaporation, magnetron sputtering, electron beam evaporation, or the like, forming an electrode by a lift-off process, and then performing N deposition at 650 DEG C2And annealing under the environment.
The manufacturing method of the novel GaN junction barrier Schottky diode comprises the following steps:
the method comprises the following steps: sequentially growing n on a substrate by organic chemical vapor deposition or hydride vapor phase epitaxy+Type GaN epitaxial layer, n-type GaN epitaxial layer, p-type GaN epitaxial layer, and p+A GaN epitaxial layer;
step two: at said p+Growing a layer of SiN on the upper surface of the GaN epitaxial layer through plasma enhanced chemical vapor deposition or atomic layer deposition;
step three: preparing a cathode of an ohmic contact electrode on the back of the substrate through thermal evaporation, magnetron sputtering or electron beam evaporation;
step four: etching the p-type GaN epitaxial layer and the p-type GaN epitaxial layer on the SiN surface by a dry method+Preparing a comb-mounted structure by using the GaN epitaxial layer, and then removing the SiN layer;
step five: preparing a circular high-resistance region on the upper surface of the n-type GaN epitaxial layer through photoetching and plasma injection;
step six: in the high resistance region and comb-mounting p+And evaporating the anode of the ohmic contact electrode on the GaN epitaxial layer to complete the manufacture method of the novel GaN junction barrier Schottky diode.
Preferably, n in said step one+The thickness of the GaN epitaxial layer is 2 μm, and the carrier concentration is about 1.5x1018cm-3(ii) a The thickness of the n-type GaN epitaxial layer is 23 μm, and the carrier concentration is about 8x1015cm-3(ii) a The thickness of the comb-shaped p-type GaN epitaxial layer is 500nm, and the carrier concentration is about 1.5x1018cm-3(ii) a Comb-shaped p+The thickness of the GaN epitaxial layer is 30nm, and the carrier concentration is about 1.5x1020cm-3
Preferably, in step one, hydrosilane is used as n+GaN-type doped Si source material, and cyclopentadienyl magnesium can be used as p+Type GaN doped Mg feedstock.
Preferably, in the third step, the cathode is evaporated with a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and the like, and the electrode is formed by a stripping process at 650 ℃ and N2And annealing under the environment.
The invention has the beneficial effects that: the novel GaN JBS device provided by the patent is in operationIn the aspect of process flow, p-type GaN does not need to be grown in the n-type GaN layer and a subsequent activation process is not needed, and the process difficulty and complexity are greatly reduced. In the aspect of device structure, a good ohmic contact and a better PN junction can be formed through a 4-layer epitaxial GaN structure, the forward on-resistance is reduced, the reverse breakdown voltage is increased, and the performance of the device is effectively improved. In addition, N2The high-resistance region formed by the Plasma can effectively inhibit the breakdown of the device at the edge of the electrode under high voltage, and the breakdown performance is enhanced. The method provided by the patent is an effective new way for improving the performance of the GaN-based Schottky barrier diode. The invention has the advantages of simple process, obvious effect, wide application prospect and the like.
Drawings
FIG. 1 is a schematic diagram of a novel GaN junction barrier Schottky diode structure according to the present invention.
Fig. 2 is a schematic diagram of a first step and a second step of the manufacturing method of the novel GaN junction barrier schottky diode of the present invention.
Fig. 3 is a schematic diagram of a third step of the manufacturing method of the novel GaN junction barrier schottky diode of the present invention.
Fig. 4 is a schematic diagram showing a fourth step of the manufacturing method of the novel GaN junction barrier schottky diode of the present invention.
Fig. 5 is a schematic diagram showing a fifth step of the manufacturing method of the novel GaN junction barrier schottky diode of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
As shown in fig. 1, the novel GaN junction barrier schottky diode sequentially includes, from bottom to top: cathode, substrate, n+A type GaN epitaxial layer, an n-type GaN epitaxial layer, a high resistance region formed by annularly injecting plasma on the outer edge of the n-type GaN epitaxial layer, a comb-shaped p+A type GaN epitaxial layer and an anode. Wherein the substrate may be of a material: gallium nitride, silicon, and silicon carbide substrates. N is+Type GaN epitaxial layer, n-type GaN epitaxial layer, comb-shaped p-type GaN epitaxial layer and comb-shaped p+The growth method of the GaN epitaxial layer is organic chemical vapor deposition or hydride vapor phase epitaxy. In thatIn this embodiment, n is+The thickness of the GaN epitaxial layer is 2 μm, and the carrier concentration is about 1.5x1018cm-3(ii) a The thickness of the n-type GaN epitaxial layer is 23 μm, and the carrier concentration is about 8x1015cm-3(ii) a The thickness of the comb-shaped p-type GaN epitaxial layer is 500nm, and the carrier concentration is about 1.5x1018cm-3(ii) a Comb-shaped p+The thickness of the GaN epitaxial layer is 30nm, and the carrier concentration is about 1.5x1020cm-3. Wherein the thickness of the epitaxial layer and the concentration of the carriers can be properly adjusted and changed.
In a high resistance region formed by annularly injecting plasma H into the outer edge of the n-type GaN epitaxial layer2、N2F or Ar.
In the electrode material of the novel GaN junction barrier Schottky diode, the cathode is evaporated with a metal film by methods such as thermal evaporation, magnetron sputtering or electron beam evaporation, and the like, and the electrode is formed by a stripping process at 650 ℃ and N2And annealing under the environment. The electrode material type in the invention is Ni/Au, Pt and other electrode materials which can form Schottky type gold half contact with n-type GaN; the electrode material of the cathode of the device is Ti/Al, Ti/Al/Ni/Au and other materials capable of forming ohmic gold half-contact with the n-type GaN.
The manufacturing method of the barrier Schottky diode based on the novel GaN junction comprises the following steps:
the method comprises the following steps: as shown in FIG. 2, 2 μm n was sequentially grown on a double-side polished n-type highly doped self-supporting GaN substrate by organic chemical vapor deposition or hydride vapor phase epitaxy+Type GaN epitaxial layer, 23 μm n-type GaN epitaxial layer, 500 μm p-type GaN epitaxial layer, and 30 μm p+A type GaN epitaxial layer in which hydrido silane can be used as Si source for n-type dopants (donor) and cyclopentadienyl magnesium can be used as Mg source for p-type dopants (acceptor).
Step two: at said p+Growing a layer of 20 μm SiN on the upper surface of the GaN epitaxial layer by plasma enhanced chemical vapor deposition or atomic layer deposition to protect the surface of the structure, wherein the SiN may be SiO2Or Al2O3Replacement;
step three: preparing a cathode of an ohmic contact electrode on the back of the substrate through thermal evaporation, magnetron sputtering or electron beam evaporation, and adopting a TI/Al/Ti/Au metal film;
step four: passing Cl on the surface of the SiN2/SiCl4Dry etching to separate p-type GaN epitaxial layer and p+Preparing a ring-shaped comb structure from the GaN epitaxial layer, and removing the SiN layer by dry etching;
step five: a barrier layer is manufactured on the upper surface of the n-type GaN epitaxial layer through a photoetching process, and H is passed through2、N2F or Ar plasma is injected into the upper surface of the n-type GaN epitaxial layer to prepare a circular high-resistance region so as to form a terminal structure;
step six: in the high resistance region and comb-mounting p+And evaporating anode Ni (10nm)/Au (125nm) of the ohmic contact electrode on the type GaN epitaxial layer to complete the manufacturing method of the novel GaN junction barrier Schottky diode.
In this embodiment, n in the first step+Type GaN has a carrier concentration of about 1.5x1018cm-3(ii) a The carrier concentration of n-type GaN was about 8x1015cm-3(ii) a The carrier concentration of comb-shaped p-type GaN was about 1.5x1018cm-3(ii) a Comb-shaped p+Type GaN has a carrier concentration of about 1.5x1020cm-3

Claims (10)

1. Novel GaN junction barrier Schottky diode, its characterized in that, the diode includes by lower to last in proper order: cathode, substrate, n+A type GaN epitaxial layer, an n-type GaN epitaxial layer, a high resistance region formed by annularly injecting plasma on the outer edge of the n-type GaN epitaxial layer, a comb-shaped p+A type GaN epitaxial layer and an anode.
2. The novel GaN junction barrier schottky diode of claim 1 wherein the substrate is made of: gallium nitride, silicon, and silicon carbide substrates.
3. The novel GaN junction barrier schottky diode of claim 1Wherein n is+Type GaN epitaxial layer, n-type GaN epitaxial layer, comb-shaped p-type GaN epitaxial layer and comb-shaped p+The growth method of the GaN epitaxial layer is organic chemical vapor deposition or hydride vapor phase epitaxy.
4. The novel GaN junction barrier schottky diode of claim 1 wherein the n is+The thickness of the GaN epitaxial layer is 2 μm, and the carrier concentration is about 1.5x1018cm-3(ii) a The thickness of the n-type GaN epitaxial layer is 23 μm, and the carrier concentration is about 8x1015cm-3(ii) a The thickness of the comb-shaped p-type GaN epitaxial layer is 500nm, and the carrier concentration is about 1.5x1018cm-3(ii) a Comb-shaped p+The thickness of the GaN epitaxial layer is 30nm, and the carrier concentration is about 1.5x1020cm-3
5. The GaN junction barrier schottky diode of claim 1 wherein the plasma is N2Or Ar.
6. The GaN junction barrier schottky diode as claimed in claim 1, wherein the cathode is formed by evaporating a metal film by thermal evaporation, magnetron sputtering or electron beam evaporation, and forming an electrode by lift-off process at 650 ℃, N2And annealing under the environment.
7. The method for fabricating a novel GaN junction barrier schottky diode as claimed in claims 1 to 7, wherein the method comprises the steps of:
the method comprises the following steps: sequentially growing n on a substrate by organic chemical vapor deposition or hydride vapor phase epitaxy+Type GaN epitaxial layer, n-type GaN epitaxial layer, p-type GaN epitaxial layer, and p+A GaN epitaxial layer;
step two: at said p+Growing a layer of SiN on the upper surface of the GaN epitaxial layer through plasma enhanced chemical vapor deposition or atomic layer deposition;
step three: preparing a cathode of an ohmic contact electrode on the back of the substrate through thermal evaporation, magnetron sputtering or electron beam evaporation;
step four: etching the p-type GaN epitaxial layer and the p-type GaN epitaxial layer on the SiN surface by a dry method+Preparing a comb-mounted structure by using the GaN epitaxial layer, and then removing the SiN layer;
step five: preparing a circular high-resistance region on the upper surface of the n-type GaN epitaxial layer through photoetching and plasma injection;
step six: in the high resistance region and comb-mounting p+And evaporating the anode of the ohmic contact electrode on the GaN epitaxial layer to complete the manufacture method of the novel GaN junction barrier Schottky diode.
8. The method of claim 7, wherein n in the first step+The thickness of the GaN epitaxial layer is 2 μm, and the carrier concentration is about 1.5x1018cm-3(ii) a The thickness of the n-type GaN epitaxial layer is 23 μm, and the carrier concentration is about 8x1015cm-3(ii) a The thickness of the comb-shaped p-type GaN epitaxial layer is 500nm, and the carrier concentration is about 1.5x1018cm-3(ii) a Comb-shaped p+The thickness of the GaN epitaxial layer is 30nm, and the carrier concentration is about 1.5x1020cm-3
9. The method according to claim 7, wherein silane hydride is used as n in the first step+GaN-type doped Si source material, and cyclopentadienyl magnesium can be used as p+Type GaN doped Mg feedstock.
10. The method according to claim 7, wherein in the third step, the cathode is formed by evaporating a metal film by thermal evaporation, magnetron sputtering, electron beam evaporation, or the like, and the electrode is formed by a lift-off process at 650 ℃ and N2And annealing under the environment.
CN201911050585.7A 2019-10-31 2019-10-31 Novel GaN junction barrier Schottky diode and preparation method thereof Pending CN110752260A (en)

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CN111863936A (en) * 2020-06-03 2020-10-30 深圳大学 Gallium nitride-based junction barrier Schottky diode and preparation method thereof
CN113340897A (en) * 2021-06-15 2021-09-03 云南大学 In-situ photoelectric testing device

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CN111863936A (en) * 2020-06-03 2020-10-30 深圳大学 Gallium nitride-based junction barrier Schottky diode and preparation method thereof
CN111863936B (en) * 2020-06-03 2023-08-25 深圳市爱迪芯半导体有限公司 Gallium nitride-based junction barrier Schottky diode and preparation method thereof
CN113340897A (en) * 2021-06-15 2021-09-03 云南大学 In-situ photoelectric testing device

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Application publication date: 20200204