CN108878509B - Gallium nitride transistor and method for manufacturing same - Google Patents
Gallium nitride transistor and method for manufacturing same Download PDFInfo
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- CN108878509B CN108878509B CN201810873441.0A CN201810873441A CN108878509B CN 108878509 B CN108878509 B CN 108878509B CN 201810873441 A CN201810873441 A CN 201810873441A CN 108878509 B CN108878509 B CN 108878509B
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 124
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 124
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title description 18
- 239000002131 composite material Substances 0.000 claims abstract description 135
- 230000004888 barrier function Effects 0.000 claims abstract description 100
- 238000003780 insertion Methods 0.000 claims abstract description 64
- 230000037431 insertion Effects 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002019 doping agent Substances 0.000 claims description 34
- 239000000203 mixture Substances 0.000 claims description 19
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052799 carbon Inorganic materials 0.000 claims description 17
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 16
- 229910052749 magnesium Inorganic materials 0.000 claims description 16
- 239000011777 magnesium Substances 0.000 claims description 16
- 230000006911 nucleation Effects 0.000 claims description 16
- 238000010899 nucleation Methods 0.000 claims description 16
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 claims description 15
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 15
- 229910052790 beryllium Inorganic materials 0.000 claims description 15
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052791 calcium Inorganic materials 0.000 claims description 15
- 239000011575 calcium Substances 0.000 claims description 15
- 239000011701 zinc Substances 0.000 claims description 15
- 229910052725 zinc Inorganic materials 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 10
- 239000007924 injection Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 9
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 3
- 238000003475 lamination Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000008859 change Effects 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000012369 In process control Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000001017 electron-beam sputter deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000001534 heteroepitaxy Methods 0.000 description 1
- 238000010965 in-process control Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The application discloses a gallium nitride transistor and a manufacturing method thereof. The gallium nitride transistor includes: a substrate; a gallium nitride layer on the substrate; a barrier layer on the gallium nitride layer; at least one second composite stack on the barrier layer; and a gate electrode, a source electrode, and a drain electrode on the barrier layer and between the source electrode and the drain electrode, wherein the at least one second composite stack comprises a stacked second doped layer and a second insertion layer, a first portion of the drain electrode is in contact with the at least one second doped layer, and a second portion of the drain electrode is in contact with the barrier layer. The second composite lamination in the gallium nitride transistor enables the gallium nitride layer to be in an on state, holes are effectively injected in an off state, captured electrons are released, the dynamic on-resistance of the transistor is restrained from being increased, the stability of the dynamic resistance is improved, and the reliability of the gallium nitride transistor is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a gallium nitride transistor and a method of manufacturing the same.
Background
Compared with semiconductor materials such as silicon, gallium arsenide and the like, the wide-bandgap semiconductor material gallium nitride (GaN) has larger forbidden bandwidth (3.4 eV), stronger critical breakdown field strength and higher electron migration rate, is widely focused by researchers at home and abroad, and has great advantages and potential in the aspects of power electronic power devices and high-frequency power devices. As a typical representation of the third generation of wide bandgap semiconductor, the gallium nitride material has the advantages of large bandgap width, high critical breakdown electric field, high electron saturation drift velocity, high temperature resistance, radiation resistance and good chemical stabilityAnd the like, and simultaneously can form a material with high concentration (more than 10) with materials such as aluminum gallium nitrogen and the like due to the polarization effect of the gallium nitride material 13 cm -2 ) And high mobility (greater than 2000 cm) 2 The two-dimensional electron gas (2 DEG) of/V.s) is very suitable for preparing power switch devices, and becomes a research hot spot in the current power device field.
At present, a gallium nitride single crystal substrate is relatively difficult to obtain, and most of gallium nitride films are realized by carrying out heteroepitaxy on other substrates. Common substrates include silicon, sapphire, silicon carbide, and the like. Gallium nitride epitaxial materials typically have defect densities 3 to 4 orders of magnitude higher than silicon materials due to the large lattice and thermal adaptations between gallium nitride and the substrate. In addition, in order to achieve a high breakdown voltage, the high-resistance nitride layer is doped with carbon, iron or magnesium. The trap level formed by the above defects and impurities captures electrons at a high reverse voltage. When the device is turned on again, the on-resistance increases, affecting the stability and reliability of the device. In view of this problem, there is a mechanism to propose a gallium nitride-based transistor of a composite drain structure: and a hole injection region is connected to one end of the drain electrode, so that the on-resistance of the device is restrained from increasing. However, on one hand, the manufacturing method of the structure is difficult in process control and high in cost because the epitaxy is carried out after the barrier layer is precisely etched. On the other hand, the structure has larger leakage current between PN junctions, so that the leakage current of the grid electrode of the device is larger, which is a great difficulty in the prior art.
Disclosure of Invention
In view of this, the present disclosure provides a gallium nitride transistor and a method for manufacturing the same, which solves the problems of larger leakage current and unstable dynamic on-resistance of the gallium nitride transistor in the prior art.
According to an aspect of the present invention, there is provided a gallium nitride transistor including: a substrate; a gallium nitride layer on the substrate; a barrier layer on the gallium nitride layer; at least one second composite stack on the barrier layer; and a gate electrode, a source electrode, and a drain electrode on the barrier layer and between the source electrode and the drain electrode, wherein the at least one second composite stack comprises a stacked second doped layer and a second insertion layer, a first portion of the drain electrode and at least one of the second doped layers are in contact with each other, and a second portion of the drain electrode is in contact with the barrier layer.
Preferably, the gallium nitride transistor comprises one of the second composite stacks, the second insertion layer being located between the second doped layer and the barrier layer.
Preferably, the gallium nitride transistor includes a plurality of the second composite stacks stacked in order, in the second composite stack adjacent to the barrier layer, the second insertion layer is located between the second doping layer and the barrier layer, and in the adjacent two second composite stacks, the second doping layer of one of the second insertion layers is in contact with the other second insertion layer.
Preferably, the method further comprises: at least one first composite stack is located on the barrier layer, the at least one first composite stack including a stacked first doped layer and a first insertion layer, the gate electrode and at least one of the first doped layers being in contact with each other.
Preferably, the gallium nitride transistor comprises one of the first composite stacks, the first insertion layer being located between the first doped layer and the barrier layer.
Preferably, the gallium nitride transistor includes a plurality of the first composite stacks stacked in order, the first insertion layer is located between the first doping layer and the barrier layer in the first composite stack adjacent to the barrier layer, and the first doping layer of one of the adjacent two first composite stacks is in contact with the other first insertion layer.
Preferably, the second doped layer serves as a hole injection region.
Preferably, the first doped layer and the second doped layer are doped nitrides, and the first insertion layer and the second insertion layer are dielectric materials.
Preferably, the dopant distribution in the first doped layer and the second doped layer is any one of a composition fixation, a composition gradual change, and a composition abrupt change.
Preferably, the first doped layer comprises a p-type dopant.
Preferably, the first doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof.
Preferably, the second doped layer comprises a p-type dopant, and/or an n-type dopant.
Preferably, the second doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof, and/or any one selected from silicon, oxygen, or a combination thereof.
Preferably, the dopant of the second doped layer is selected from the p-type dopant, wherein the first composite stack and the second composite stack are formed in the same manufacturing step.
Preferably, the doping type and/or doping concentration of the second doped layer is set such that a channel in the gallium nitride layer below the second doped layer is in an on state under zero bias, and in a reverse off state the second doped layer injects holes into the channel in the gallium nitride layer.
Preferably, the gate electrode forms an ohmic contact or a schottky contact with the first doped layer.
Preferably, the source electrode and the drain electrode form ohmic contacts with the gallium nitride layer.
Preferably, the method further comprises: a nucleation layer on the substrate; and a buffer layer between the nucleation layer and the gallium nitride layer.
Preferably, the forbidden bandwidth of the barrier layer is larger than that of the gallium nitride layer.
Preferably, a two-dimensional electron gas exists between the gallium nitride and the barrier layer.
According to another aspect of the present invention, there is provided a method of manufacturing a gallium nitride transistor, comprising: forming a gallium nitride layer on a substrate; forming a barrier layer on the gallium nitride layer; forming at least one second composite stack on the barrier layer; and forming a gate electrode, a source electrode, and a drain electrode on the barrier layer, and the gate electrode is formed between the source electrode and the drain electrode, wherein the at least one second composite stack includes a stacked second doped layer and a second insertion layer, a first portion of the drain electrode and at least one of the second doped layers are in contact with each other, and a second portion of the drain electrode is in contact with the barrier layer.
Preferably, the step of forming at least one second composite stack comprises forming one of the second composite stacks, the step of forming one of the second composite stacks comprising: forming the second insertion layer on the barrier layer; and forming the second doping layer on the second insertion layer.
Preferably, the step of forming at least one second composite stack comprises forming a plurality of said second composite stacks, and the step of forming a plurality of said second composite stacks comprises stacking in sequence a plurality of said second composite stacks on said barrier layer, wherein in said second composite stack adjacent to said barrier layer, said second insertion layer is located between said second doping layer and said barrier layer, and in adjacent two said second composite stacks, said second doping layer of one is in contact with the other said second insertion layer.
Preferably, the method further comprises: at least one first composite stack is formed on the barrier layer, the at least one first composite stack including a stacked first doped layer and a first insertion layer, the drain electrode and the first doped layer being in contact with each other.
Preferably, the step of forming at least one first composite stack comprises forming one of the first composite stacks, the step of forming one of the first composite stacks comprising: forming the first insertion layer on the barrier layer; and forming the first doping layer on the first insertion layer.
Preferably, the step of forming at least one first composite stack comprises forming a plurality of the first composite stacks, and the step of forming a plurality of the first composite stacks comprises sequentially stacking a plurality of the first composite stacks on the barrier layer, wherein in the first composite stack adjacent to the barrier layer, the first insertion layer is located between the first doping layer and the barrier layer, and in two adjacent first composite stacks, the first doping layer of one of the first insertion layers is in contact with the other first insertion layer.
Preferably, the second doped layer serves as a hole injection region.
Preferably, the first doped layer and the second doped layer are doped nitrides, and the first insertion layer and the second insertion layer are dielectric materials.
Preferably, the dopant distribution in the first doped layer and the second doped layer is any one of a composition fixation, a composition gradual change, and a composition abrupt change.
Preferably, the first doped layer comprises a p-type dopant.
Preferably, the first doped layer and the second doped layer are doped with any one selected from magnesium, calcium, zinc beryllium, carbon or a combination thereof.
Preferably, the second doped layer comprises a p-type dopant, and/or an n-type dopant.
Preferably, the second doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof, and/or any one selected from silicon, oxygen, or a combination thereof.
Preferably, the first composite stack is formed in the same manufacturing step as the second composite stack, the dopant of the second doped layer being selected from the p-type dopants.
Preferably, the doping type and/or doping concentration of the second doped layer is set such that a channel in the gallium nitride layer below the second doped layer is in an on state under zero bias, and in a reverse off state the second doped layer injects holes into the channel in the gallium nitride layer.
Preferably, the gate electrode forms an ohmic contact or a schottky contact with the first doped layer.
Preferably, the source electrode and the drain electrode form ohmic contacts with the gallium nitride layer.
Preferably, before the step of forming the gallium nitride, the method further comprises: forming a nucleation layer on the substrate; and forming a buffer layer on the nucleation layer, wherein the gallium nitride layer is located on the buffer layer.
Preferably, the forbidden bandwidth of the barrier layer is larger than that of the gallium nitride layer.
Preferably, a two-dimensional electron gas exists between the gallium nitride layer and the barrier layer.
According to the gallium nitride transistor and the manufacturing method thereof of the embodiment of the disclosure, the gate leakage current is reduced by the first composite laminate layer arranged between the gate electrode and the barrier layer; by adding the second composite laminate at one end of the drain electrode close to the gate electrode, the drain electrode and the second composite laminate are contacted with each other and the barrier layer, and when the first composite laminate and the second composite laminate are manufactured in the same process step, the operation is simple, and the production cost is saved. Meanwhile, the second composite lamination is used as a hole injection layer, the doping type and/or doping concentration of the second doping layer are/is modulated, so that the gallium nitride layer is in an on state in a zero bias state, holes are effectively injected in an off state, captured electrons are released, the dynamic on-resistance of the gallium nitride transistor is restrained from being increased, the stability of the dynamic resistance is improved, and the stability and reliability of the gallium nitride transistor are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.
Fig. 1 shows a schematic structural diagram of a gallium nitride transistor according to an embodiment of the present disclosure.
Fig. 2 shows a schematic flow chart of manufacturing a gallium nitride transistor according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating a specific step of forming a first composite stack and a second composite stack for the fabrication of the gallium nitride transistor of fig. 2.
Fig. 4-7 illustrate side cross-sectional views of embodiments of the present disclosure in the fabrication of gallium nitride transistors.
Detailed Description
In order that the above-recited objects, features and advantages of the present disclosure will become more readily apparent, a more particular description of the disclosure will be rendered by reference to the appended drawings. Numerous specific details are set forth in the description in order to provide a thorough understanding of the present disclosure, but the present disclosure may be embodied in other ways than described herein, and persons skilled in the art will be able to make similar generalizations without departing from the spirit of the disclosure and therefore the present disclosure is not limited to the specific embodiments disclosed below. Next, the disclosure will be described in detail with reference to the schematic drawings, which are not to scale in the section view of the device structure for convenience of description, and which are merely examples, which should not limit the scope of protection of the disclosure herein. In addition, the three dimensional dimensions of length, width and depth should be included in actual manufacturing.
Fig. 1 shows a schematic structural diagram of a gallium nitride transistor according to an embodiment of the present disclosure.
As shown in fig. 1, a gallium nitride transistor of an embodiment of the present disclosure includes: the substrate 101, nucleation layer 102, buffer layer 103, gallium nitride layer 104, barrier layer 105, at least one first composite stack 210, at least one second composite stack 220, gate electrode 301, source electrode 302, and drain electrode 303. Wherein the first composite laminate 210 comprises: the stacked first doped layer 211 and first interposed layer 212, the second composite stack 220 includes: the stacked second doping layer 221 and second insertion layer 222. A two-dimensional electron gas exists between the gallium nitride layer 104 and the barrier layer 105.
A nucleation layer 102 is located on the substrate 101. A buffer layer 103 is located on nucleation layer 102. A gallium nitride layer 104 is located on the buffer layer 103. The barrier layer 105 is located on the gallium nitride layer 104, wherein the forbidden bandwidth of the barrier layer 105 is larger than the forbidden bandwidth of the gallium nitride layer 104.
The first composite stack 210 is located on the barrier layer 105, further, the first insertion layer 212 is located between the first doped layer 211 and the barrier layer 105, the first doped layer 211 is doped nitride, the first insertion layer 212 is a dielectric material, further, the dopant in the first doped layer 211 is distributed as any one of a fixed composition, a graded composition and a abrupt composition, and the first doped layer 211 comprises any one p-type dopant selected from magnesium, calcium, zinc beryllium, carbon or a combination. In some preferred embodiments, the first insertion layer 212 is located between at least two first doped layers 211.
The second composite stack 220 is located on the barrier layer 105, and further, the second doped layer 221 is used as a hole injection region, the second doped layer 221 is doped nitride, and the second insertion layer 222 is a dielectric material. Further, the dopant profile in the second doped layer 221 is any one of a composition fixation, a composition graded, and a composition abrupt change. The second doped layer 221 includes any p-type dopant selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof, and/or any n-type dopant selected from silicon, oxygen, or a combination thereof. The doping type and doping concentration of the second doping layer 221 are set such that the channel in the gallium nitride layer 104 located below the second doping layer 221 is in an on-state at zero bias, and in a reverse off-state the second doping layer 221 injects holes into the channel in the gallium nitride layer 104. In some preferred embodiments, the second insertion layer 222 is located between at least two second doped layers 221.
A gate electrode 301 is located on the first composite stack 210, a source electrode 302 is located on the barrier layer 105, and a drain electrode 303 is located on the second composite stack 220 and the barrier layer 105. Further, the gate electrode 301 is located between the source electrode 302 and the drain electrode 303, the gate electrode 301 and the first doped layer 211 are in contact with each other, the gate electrode 301 and the first doped layer 211 form an ohmic contact or a schottky contact, the source electrode 302 and the drain electrode 303 form an ohmic contact with the gallium nitride layer 104 by rapid thermal annealing (rapid thermal annealing, RTA), the first portion 303a of the drain electrode 303 and the second doped layer 221 are in contact with each other, the drain electrode 303 and the second doped layer 221 form an ohmic contact, and the second portion 303b of the drain electrode 303 is in contact with the barrier layer 105.
Fig. 2 shows a schematic flow chart of manufacturing a gallium nitride transistor according to an embodiment of the disclosure.
In step S01, a nucleation layer is formed on a substrate. As shown in fig. 4, the substrate 101 is cleaned and then a nucleation layer 102 is grown on the substrate 101 by metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) or molecular beam epitaxy (Molecular Beam Epitaxy, MBE) or other methods. The material of the substrate 101 may include silicon, silicon carbide, or sapphire, and the material of the nucleation layer 102 may include gallium nitride or aluminum nitride.
In step S02, a buffer layer is formed on the nucleation layer. As shown in fig. 4, a buffer layer 103 is grown on the nucleation layer 102, wherein the material of the buffer layer 103 may include carbon self-doped semi-insulating high resistance gallium nitride.
In step S03, a gallium nitride layer is formed on the buffer layer. As shown in fig. 4, a gallium nitride layer 104 is grown on the buffer layer 103, wherein the material of the gallium nitride layer 104 may include high mobility unintentionally doped gallium nitride.
In step S04, a barrier layer is formed on the gallium nitride layer. As shown in fig. 4, a barrier layer 105 is grown on the gallium nitride layer 104, wherein a two-dimensional electron gas exists between the gallium nitride layer 104 and the barrier layer 105, the forbidden band width of the barrier layer 105 is larger than that of the gallium nitride layer 104, and the material of the barrier layer 105 may include nitrides such as aluminum gallium nitride, indium aluminum gallium nitride, aluminum nitride, and the like with an aluminum composition of 5% to 30%.
In step S05, a first composite stack and a second composite stack are formed on the barrier layer. As shown in fig. 3, a first composite stack and a second composite stack may be formed on the barrier layer through steps S051 to S054, and as shown in fig. 6, the first composite stack 210 includes a stacked first doped layer 211 and a first insertion layer 212, the second composite stack 220 includes a stacked second doped layer 221 and a second insertion layer 222, wherein the second doped layer 221 serves as a hole injection region, and the first composite stack 210 and the second composite stack 220 are simultaneously formed on the barrier layer 105, i.e., the first doped layer 211 and the second doped layer 221, and the first insertion layer 212 and the second insertion layer 222 are respectively formed in the same step. Further, the step of forming the first composite laminate 210 includes: a first insertion layer 212 is formed on the barrier layer 105, and a first doping layer 211 is formed on the first insertion layer 212. In some preferred embodiments, the step of forming the first composite layup 210 comprises: a first insertion layer 212 is formed between at least two first doping layers 211. The step of forming the second composite laminate 220 includes: a second insertion layer 222 is formed on the barrier layer 105, and a second doping layer 221 is formed on the second insertion layer 222. In some preferred embodiments, the step of forming the second composite laminate 220 comprises: a second insertion layer 222 is formed between at least two second doping layers 221. Preferably, the first composite laminate is formed in the same manufacturing step as the second composite laminate.
Further, the first doped layer 211 and the second doped layer 221 are doped nitrides, and the first interposer 212 and the second interposer 222 are dielectric materials, respectively. The dopant profile in the first and second doped layers 211 and 221 is any one of a composition fixation, a composition gradual change, and a composition abrupt change. Further, after any p-type dopant including any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination is doped in the first doped layer 211 and the second doped layer 221, respectively, any p-type dopant including any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination, and/or any n-type dopant including any one selected from silicon, oxygen, or a combination thereof is doped in the second doped layer 221. The doping type and doping concentration of the second doping layer 221 are set such that the channel in the gallium nitride layer 104 located below the second doping layer 221 is in an on-state at zero bias, and in a reverse off-state the second doping layer 221 injects holes into the channel in the gallium nitride layer 104. Preferably, when the first composite stack and the second composite stack are formed in the same manufacturing step, the first doped layer and the second doped layer are doped with a p-type dopant comprising any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination, respectively.
Steps S051 to S054 will be described in detail below with reference to fig. 5A to 6.
In step S051, an insertion layer is formed on the barrier layer. As shown in fig. 5A, an interposer 202 is formed on the doped barrier layer 105, and the material of the interposer 202 includes aluminum nitride, silicon nitride, or the like.
In step S052, a doped layer is formed on the interposed layer. As shown in fig. 5A, a doped layer 201 is formed on the insertion layer 202, wherein the doped layer 201 includes: binary or multiple p-type nitrides of indium, gallium, aluminum, etc. with fixed, graded, abrupt components. In some preferred embodiments, the doping impurities of the p-type nitride include: magnesium, calcium, zinc beryllium, carbon, or combinations thereof.
As shown in fig. 5B, in the second embodiment of the present disclosure, on the barrier layer 105, the twice inserted layer 202 and the doped layer 201 are formed overlapping. As shown in fig. 5C, in the third embodiment of the present disclosure, the insertion layer 202 and the doped layer 201 are formed on the barrier layer 105 overlapping a plurality of times. Specifically, in the second composite stack adjacent to the barrier layer, the second insertion layer is located between the second doping layer and the barrier layer, and in two adjacent second composite stacks, the second doping layer of one of the second composite stacks is in contact with the other second insertion layer; in addition, in the first composite laminate adjacent to the barrier layer, the first insertion layer is located between the first doping layer and the barrier layer, and in the adjacent two first composite laminates, the first doping layer of one of the first insertion layers is in contact with the other first insertion layer. In the second and third embodiments, the thickness of each of the interposer layers 202 may be designed separately.
In step S053, a first composite stack and a second composite stack are formed. As shown in fig. 6, the doped layer 201 and the interposed layer 202 are subjected to steps such as photoresist coating, photolithography, etching, photoresist removal, and the like, so as to form a first composite stack 210 and a second composite stack 220, so that a portion of the surface of the barrier layer 105 is exposed.
In step S054, the doping concentration of the second doped layer is adjusted. Specifically, as shown in fig. 6, the second doped layer 221 is a hole injection region, the doping concentration of the second doped layer 221 is adjusted by secondary doping, for example, n-type doping can be performed by injecting silicon, oxygen or a combination thereof, and p-type doping can also be performed by injecting magnesium, calcium, beryllium zinc, carbon or a combination thereof, so that the two-dimensional electron gas formed in the gallium nitride layer 104 is in an on state under the condition of zero bias, and in a reverse off state, the second doped layer 221 can inject holes, so that the captured electrons are released, and the stability of the dynamic on resistance of the device is increased. In an alternative embodiment, the method of etching and thinning can be used instead of the method of adjusting the doping concentration.
In step S06, a source electrode is formed on the barrier layer. As shown in fig. 7, source metal is deposited on the barrier layer 105, a source metal contact region is opened by photoresist, and a source electrode 302 is formed on the barrier layer 105 by electron beam evaporation. The source metal material includes titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride, or an alloy combination thereof, and forms an ohmic contact between the source electrode 302 and the gallium nitride layer 104 by annealing.
In step S07, a gate electrode is formed on the first composite stack. As shown in fig. 7, gate metal is deposited on the first composite stack, the gate metal contact area is opened by photoresist, and electron beam evaporation is used to form a gate electrode 301 on the first doped layer 211. The gate electrode 301 and the first doping layer 211 are in contact with each other. The material of the gate metal includes titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or an alloy combination thereof, and ohmic contact or schottky contact is formed between the gate electrode 301 and the first doped layer 211 through high-temperature annealing.
In step S08, a drain electrode is formed on the barrier layer and the second composite stack with the gate electrode 301 between the source electrode 302 and the drain electrode 303. As shown in fig. 7, a drain metal is deposited on a portion of the barrier layer 105 and the second composite stack 220, a drain metal contact region is opened by photoresist coating, photolithography, and an electron beam evaporation or sputtering is used to form a composite drain electrode 303 on the second doped layer 221 and the barrier layer 105, the drain electrode 303 and the second doped layer 221 are in contact with each other, wherein the material of the drain metal includes titanium, aluminum, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or an alloy combination thereof, an ohmic contact is formed between the drain electrode 303 and the gallium nitride layer 104 through annealing, and an ohmic contact or schottky contact is formed between the drain electrode 303 and the second doped layer 221 through high temperature annealing.
According to the gallium nitride transistor of the embodiment of the present disclosure, a first composite stack layer is sandwiched between a gate electrode and a barrier layer, the first composite stack layer including a stacked first doping layer and a first insertion layer. The first insertion layer is made of dielectric materials, and can be used as a first doping layer etching stop layer and can effectively reduce gate leakage current.
In a preferred embodiment, the gallium nitride transistor further comprises a second composite stack comprising a stacked second doped layer and a second interposed layer on the barrier layer. The second interposer is composed of a dielectric material, for example. The drain electrode and the second doped layer are in contact with each other. The second doped layer is used as a hole injection layer, and the doping type and/or doping concentration of the second doped layer or the method of etching thinning is modulated, so that under zero bias, the gallium nitride layer is in an on state and can be effectively injected into holes in an off state, captured electrons are released, the dynamic on-resistance of the gallium nitride transistor is restrained from being increased, the stability of the dynamic resistance is improved, and the stability and reliability of the gallium nitride transistor are improved.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
These embodiments are not all details described in detail above in accordance with the present disclosure, nor are they intended to limit the disclosure to the particular embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, to thereby enable others skilled in the art to best utilize the disclosure and its modifications as are suited to the particular use contemplated. The present disclosure is limited only by the claims and the full scope and equivalents thereof.
Claims (38)
1. A gallium nitride transistor, comprising:
a substrate;
a gallium nitride layer on the substrate;
a barrier layer on the gallium nitride layer;
at least one second composite stack on the barrier layer; and
a gate electrode, a source electrode, and a drain electrode on the barrier layer, and the gate electrode is between the source electrode and the drain electrode,
wherein the at least one second composite stack comprises a stacked second doped layer and a second insertion layer, a first portion of the drain electrode is in contact with at least one of the second doped layers, a second portion of the drain electrode is in contact with the barrier layer, and the second doped layer serves as a hole injection region.
2. The gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises one of the second composite stacks, the second insertion layer being located between the second doped layer and the barrier layer.
3. The gallium nitride transistor of claim 1, wherein the gallium nitride transistor comprises a plurality of the second composite stacks, the plurality of second composite stacks being stacked in sequence,
in the second composite stack adjacent to the barrier layer, the second insertion layer is located between the second doped layer and the barrier layer,
in adjacent two of the second composite stacks, the second doped layer of one of the second composite stacks is in contact with the other of the second interposed layers.
4. The gallium nitride transistor of claim 1, further comprising: at least one first composite stack is located on the barrier layer, the at least one first composite stack including a stacked first doped layer and a first insertion layer, the gate electrode and at least one of the first doped layers being in contact with each other.
5. The gallium nitride transistor of claim 4, wherein the gallium nitride transistor comprises one of the first composite stacks, the first interposer layer being located between the first doped layer and the barrier layer.
6. The gallium nitride transistor of claim 4, wherein the gallium nitride transistor comprises a plurality of the first composite stacks, the plurality of first composite stacks stacked in sequence,
in the first composite stack adjacent to the barrier layer, the first insertion layer is located between the first doped layer and the barrier layer,
in adjacent two of the first composite stacks, the first doped layer of one of the first composite stacks is in contact with the other first interposed layer.
7. The gallium nitride transistor of claim 4, wherein the first and second doped layers are each doped nitride, and the first and second intervening layers are each dielectric material.
8. The gallium nitride transistor of claim 7, wherein the dopant profile in the first and second doped layers is any one of a fixed composition, a graded composition, and a abrupt composition.
9. The gallium nitride transistor of claim 7, wherein the first doped layer comprises a p-type dopant.
10. The gallium nitride transistor of claim 9 wherein the first doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination.
11. The gallium nitride transistor of claim 9, wherein the second doped layer comprises a p-type dopant, and/or an n-type dopant.
12. The gallium nitride transistor of claim 11 wherein the second doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof, and/or any one selected from silicon, oxygen, or a combination thereof.
13. The gallium nitride transistor of claim 11, wherein the dopant of the second doped layer is selected from the p-type dopant, wherein the first composite stack and the second composite stack are formed in the same fabrication step.
14. Gallium nitride transistor according to claim 12, wherein the doping type and/or doping concentration of the second doped layer is arranged such that the channel in the gallium nitride layer below the second doped layer is in an on-state at zero bias and in an inverted off-state the second doped layer injects holes into the channel in the gallium nitride layer.
15. The gallium nitride transistor of claim 4, wherein the gate electrode forms an ohmic or schottky contact with the first doped layer.
16. The gallium nitride transistor of claim 1, wherein the source electrode and the drain electrode form ohmic contacts with the gallium nitride layer.
17. A gallium nitride transistor according to any one of claims 1-16, further comprising:
a nucleation layer on the substrate; and
and a buffer layer between the nucleation layer and the gallium nitride layer.
18. The gallium nitride transistor of claim 17, wherein a forbidden bandwidth of the barrier layer is greater than a forbidden bandwidth of the gallium nitride layer.
19. The gallium nitride transistor of claim 18 wherein a two-dimensional electron gas is present between the gallium nitride and the barrier layer.
20. A method of fabricating a gallium nitride transistor, comprising:
forming a gallium nitride layer on a substrate;
forming a barrier layer on the gallium nitride layer;
forming at least one second composite stack on the barrier layer; and
forming a gate electrode, a source electrode, and a drain electrode on the barrier layer, and the gate electrode being formed between the source electrode and the drain electrode,
wherein the at least one second composite stack comprises a stacked second doped layer and a second insertion layer, a first portion of the drain electrode is in contact with at least one of the second doped layers, a second portion of the drain electrode is in contact with the barrier layer, and the second doped layer serves as a hole injection region.
21. The method of manufacturing of claim 20, wherein the step of forming at least one second composite laminate comprises forming one of the second composite laminates, the step of forming one of the second composite laminates comprising:
forming the second insertion layer on the barrier layer; and
forming the second doping layer on the second insertion layer.
22. The method of manufacturing of claim 20, wherein the step of forming at least one second composite stack comprises forming a plurality of the second composite stacks, the step of forming a plurality of the second composite stacks comprises sequentially stacking a plurality of the second composite stacks on the barrier layer,
wherein in the second composite stack adjacent to the barrier layer, the second insertion layer is located between the second doped layer and the barrier layer,
in adjacent two of the second composite stacks, the second doped layer of one of the second composite stacks is in contact with the other of the second interposed layers.
23. The manufacturing method of claim 20, further comprising:
at least one first composite stack is formed on the barrier layer, the at least one first composite stack including a stacked first doped layer and a first insertion layer, the drain electrode and the first doped layer being in contact with each other.
24. The method of manufacturing of claim 23, wherein the step of forming at least one first composite laminate comprises forming one of the first composite laminates, the step of forming one of the first composite laminates comprising:
forming the first insertion layer on the barrier layer; and
the first doped layer is formed on the first insertion layer.
25. The method of manufacturing of claim 23, wherein the step of forming at least one first composite stack comprises forming a plurality of the first composite stacks, the step of forming a plurality of the first composite stacks comprises sequentially stacking a plurality of the first composite stacks on the barrier layer,
wherein in the first composite stack adjacent to the barrier layer, the first insertion layer is located between the first doped layer and the barrier layer,
in adjacent two of the first composite stacks, the first doped layer of one of the first composite stacks is in contact with the other first interposed layer.
26. The method of manufacturing of claim 23, wherein the first doped layer and the second doped layer are each doped nitride, and the first interposer and the second interposer are each dielectric material.
27. The manufacturing method according to claim 26, wherein the dopant distribution in the first doped layer and the second doped layer is any one of a composition-fixed, a composition-graded, and a composition-abrupt.
28. The method of manufacturing of claim 26, wherein the first doped layer comprises a p-type dopant.
29. The manufacturing method according to claim 28, wherein each of the first doped layer and the second doped layer is doped with any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof.
30. The method of manufacturing of claim 28, wherein the second doped layer comprises a p-type dopant, and/or an n-type dopant.
31. The method of manufacturing of claim 30, wherein the second doped layer comprises any one selected from magnesium, calcium, zinc beryllium, carbon, or a combination thereof, and/or any one selected from silicon, oxygen, or a combination thereof.
32. The method of manufacturing according to claim 30, wherein the first composite stack and the second composite stack are formed in the same manufacturing step,
the dopant of the second doped layer is selected from the p-type dopant.
33. The method of manufacturing of claim 31, wherein the doping type and/or doping concentration of the second doped layer is set such that a channel in the gallium nitride layer below the second doped layer is in an on-state at zero bias and in an inverted off-state the second doped layer injects holes into the channel in the gallium nitride layer.
34. The method of manufacturing of claim 23, wherein the gate electrode forms an ohmic contact or a schottky contact with the first doped layer.
35. The manufacturing method according to claim 20, wherein the source electrode and the drain electrode form ohmic contacts with the gallium nitride layer.
36. The method of manufacturing according to any one of claims 20 to 35, wherein prior to the step of forming the gallium nitride, further comprising:
forming a nucleation layer on the substrate; and
a buffer layer is formed on the nucleation layer,
wherein the gallium nitride layer is positioned on the buffer layer.
37. The manufacturing method according to claim 36, wherein a forbidden bandwidth of the barrier layer is larger than a forbidden bandwidth of the gallium nitride layer.
38. The manufacturing method according to claim 37, wherein a two-dimensional electron gas exists between the gallium nitride layer and the barrier layer.
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