CN108878509A - gallium nitride transistor and its manufacturing method - Google Patents
gallium nitride transistor and its manufacturing method Download PDFInfo
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- CN108878509A CN108878509A CN201810873441.0A CN201810873441A CN108878509A CN 108878509 A CN108878509 A CN 108878509A CN 201810873441 A CN201810873441 A CN 201810873441A CN 108878509 A CN108878509 A CN 108878509A
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- gallium nitride
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- composite laminate
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 118
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 118
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 118
- 230000004888 barrier function Effects 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002019 doping agent Substances 0.000 claims description 32
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 17
- 229910052799 carbon Inorganic materials 0.000 claims description 17
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 16
- 229910052749 magnesium Inorganic materials 0.000 claims description 16
- 239000011777 magnesium Substances 0.000 claims description 16
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 claims description 15
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 15
- 229910052790 beryllium Inorganic materials 0.000 claims description 15
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910052791 calcium Inorganic materials 0.000 claims description 15
- 239000011575 calcium Substances 0.000 claims description 15
- 229910052725 zinc Inorganic materials 0.000 claims description 15
- 239000011701 zinc Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 14
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 9
- 230000035772 mutation Effects 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052733 gallium Inorganic materials 0.000 claims description 7
- 238000003780 insertion Methods 0.000 claims description 7
- 230000037431 insertion Effects 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000009826 distribution Methods 0.000 claims description 6
- 230000005465 channeling Effects 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 5
- 239000007789 gas Substances 0.000 claims description 3
- 238000010348 incorporation Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 description 15
- 238000000034 method Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 230000008859 change Effects 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 238000004026 adhesive bonding Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005566 electron beam evaporation Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum gallium nitrides Chemical class 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000009527 percussion Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
This application discloses a kind of gallium nitride transistor and its manufacturing methods.The gallium nitride transistor includes：Substrate；Gallium nitride layer is located on the substrate；Barrier layer is located on the gallium nitride layer；At least one second composite laminate is located on the barrier layer；And gate electrode, source electrode and drain electrode, on the barrier layer, and the gate electrode is between the source electrode and the drain electrode, wherein, at least one described second composite laminate includes the second doped layer stacked and the second insert layer, the first part of the drain electrode contacts with the second doped layer described at least one, and the second part of the drain electrode is contacted with the barrier layer.The second composite laminate in the gallium nitride transistor keeps gallium nitride layer in the conductive state, and it is efficiently injected into hole in off state, captured electronics is discharged, transistor dynamic on resistance is inhibited to increase, the stability for increasing dynamic electric resistor, improves the reliability of gallium nitride transistor.
Description
Technical field
This disclosure relates to semiconductor field, more particularly, to a kind of gallium nitride transistor and its manufacturing method.
Background technique
Compared with the semiconductor materials such as silicon, GaAs, semiconductor material with wide forbidden band gallium nitride (GaN) has bigger forbidden band
Width (3.4eV), stronger critical breakdown strength and higher electron transfer rate, have obtained the wide of domestic and international researchers
General concern has big advantage and potentiality in terms of power electronic power device and high-frequency power device.As the third generation
The Typical Representative of wide bandgap semiconductor, gallium nitride material not only have forbidden bandwidth is big, critical breakdown electric field is high, electronics saturation drift
The features such as moving big speed, high temperature resistant, good anti-radiation and chemical stability, simultaneously because the polarity effect of gallium nitride material, it can
To be formed with materials such as aluminum gallium nitrides there is high concentration (to be greater than 1013cm-2) and high mobility (be greater than 2000cm2/ Vs) two dimension
Electron gas (2DEG), is very suitable to prepare device for power switching, becomes the research hotspot of current power devices field.
Gallium nitride monocrystal substrate is more difficult to get at present, and most gallium nitride films are different by carrying out on other substrates
Matter extension is realized.Common substrate includes silicon, sapphire and silicon carbide etc..Since there are biggish between gallium nitride and substrate
Lattice adaptation and heat adaptation, the defect concentration of usual gallium nitride epitaxial materials 3 to 4 orders of magnitude higher than silicon materials.Furthermore
In order to realize high-breakdown-voltage, carbon, iron or magnesium doping are carried out in high resistant nitride layer.Due to disadvantages described above and impurity energy shape
At trap level under high back voltage, trap level can capture electronics.When device is again turned on, conducting resistance increases, shadow
The Stability and dependability of Chinese percussion instrument part.In response to this problem, mechanism proposes a kind of gallium nitride based transistor of compound drain electrode structure：
Hole injection region is accessed in drain electrode one end, suppression device conducting resistance increases.But on the one hand the structure manufacturing method due to
It needs using extension is carried out again after accurate etching barrier layer, technique controlling difficulty is big, at high cost.On the other hand the structure is due to PN
There are biggish leakage currents between knot, cause device grid leakage current larger, and presently, there are a great problem.
Summary of the invention
In view of this, being solved in the prior art present disclose provides a kind of gallium nitride transistor and its manufacturing method
The biggish problem of gallium nitride tube leakage current and dynamic on resistance instability problem.
According to an aspect of the present invention, a kind of gallium nitride transistor is provided, including：Substrate；Gallium nitride layer is located at described
On substrate；Barrier layer is located on the gallium nitride layer；At least one second composite laminate is located on the barrier layer；And grid
Pole electrode, source electrode and drain electrode, be located at the barrier layer on, and the gate electrode be located at the source electrode with
Between the drain electrode, wherein at least one described second composite laminate includes the second doped layer stacked and the second insertion
Layer, the first part of the drain electrode are in contact with each other with the second doped layer described at least one, and the second of the drain electrode
Part is contacted with the barrier layer.
Preferably, the gallium nitride transistor includes second composite laminate, and second insert layer is located at institute
It states between the second doped layer and the barrier layer.
Preferably, the gallium nitride transistor includes multiple second composite laminates, the multiple second composite laminate
It stacks gradually, in second composite laminate adjacent with the barrier layer, second insert layer is located at described second and mixes
Between diamicton and the barrier layer, in two adjacent second composite laminates, second doped layer of one of them
It is contacted with another second insert layer.
Preferably, further include：At least one first composite laminate, be located at the barrier layer on, it is described at least one first
Composite laminate includes the first doped layer and the first insert layer of stacking, the gate electrode and at least one described first doped layer
It is in contact with each other.
Preferably, the gallium nitride transistor includes first composite laminate, and first insert layer is located at institute
It states between the first doped layer and the barrier layer.
Preferably, the gallium nitride transistor includes multiple first composite laminates, the multiple first composite laminate
It stacks gradually, in first composite laminate adjacent with the barrier layer, first insert layer is located at described first and mixes
Between diamicton and the barrier layer, in two adjacent first composite laminates, first doped layer of one of them
It is contacted with another first insert layer.
Preferably, second doped layer is as hole injection region.
Preferably, first doped layer and second doped layer are respectively doped nitride, first insert layer
It is respectively dielectric material with second insert layer.
Preferably, the dopant distribution in first doped layer and second doped layer be component fix, component gradually
Any one of change and component mutation.
Preferably, first doped layer includes p-type dopant.
Preferably, first doped layer includes selected from any one of magnesium, calcium, beryllium zinc, carbon or combination.
Preferably, second doped layer includes p-type dopant and/or n-type dopant.
Preferably, second doped layer include any one of selected from magnesium, calcium, beryllium zinc, carbon or combination, and/or
Selected from any one of silicon, oxygen or combinations thereof.
Preferably, the dopant of second doped layer is selected from the p-type dopant, wherein first composite laminate
It is formed in same manufacturing step with second composite laminate.
Preferably, the doping type of second doped layer and/or doping concentration are set as being located at second doped layer
Channel in the gallium nitride layer of lower section is in the conductive state under zero-bias, and the second doped layer described in reverse blocking state is to institute
State the Channeling implantation hole in gallium nitride layer.
Preferably, the gate electrode and first doped layer form Ohmic contact or Schottky contacts.
Preferably, the source electrode and the drain electrode and the gallium nitride layer form Ohmic contact.
Preferably, further include：Nucleating layer is located on the substrate；And buffer layer, it is located at the nucleating layer and the nitrogen
Change between gallium layer.
Preferably, the forbidden bandwidth of the barrier layer is greater than the forbidden bandwidth of the gallium nitride layer.
Preferably, there are two-dimensional electron gas between the gallium nitride and the barrier layer.
According to another aspect of the present invention, a kind of manufacturing method of gallium nitride transistor is provided, including：Shape on substrate
At gallium nitride layer；Barrier layer is formed on the gallium nitride layer；At least one second composite laminate is formed on the barrier layer；
And gate electrode, source electrode and drain electrode are formed on the barrier layer, and the gate electrode be formed in it is described
Between source electrode and the drain electrode, wherein at least one described second composite laminate includes the second doped layer stacked
With the second insert layer, the first part of the drain electrode is in contact with each other with the second doped layer described at least one, the drain electrode
The second part of electrode is contacted with the barrier layer.
Preferably, the step of described at least one second composite laminate of formation include formed one it is described second compound folded
Layer, formed second composite laminate the step of include：Second insert layer is formed on the barrier layer；And
Second doped layer is formed in second insert layer.
Preferably, the step of described at least one second composite laminate of formation is compound folded including forming multiple described second
Layer, the step of forming multiple second composite laminates include stacking gradually that form multiple described second multiple on the barrier layer
Close lamination, wherein in second composite laminate adjacent with the barrier layer, second insert layer is located at described second
Between doped layer and the barrier layer, in two adjacent second composite laminates, second doping of one of them
Layer is contacted with another second insert layer.
Preferably, further include：Form at least one first composite laminate on the barrier layer, it is described at least one first
Composite laminate includes that the first doped layer stacked and the first insert layer, the drain electrode connect each other with first doped layer
Touching.
Preferably, the step of described at least one first composite laminate of formation include formed one it is described first compound folded
Layer, formed first composite laminate the step of include：First insert layer is formed on the barrier layer；And
First doped layer is formed in first insert layer.
Preferably, the step of described at least one first composite laminate of formation is compound folded including forming multiple described first
Layer, the step of forming multiple first composite laminates include stacking gradually that form multiple described first multiple on the barrier layer
Close lamination, wherein in first composite laminate adjacent with the barrier layer, first insert layer is located at described first
Between doped layer and the barrier layer, in two adjacent first composite laminates, first doping of one of them
Layer is contacted with another first insert layer.
Preferably, second doped layer is as hole injection region.
Preferably, first doped layer and second doped layer are respectively doped nitride, first insert layer
It is respectively dielectric material with second insert layer.
Preferably, the dopant distribution in first doped layer and second doped layer be component fix, component gradually
Any one of change and component mutation.
Preferably, first doped layer includes p-type dopant.
Preferably, first doped layer and second doped layer respectively mix include selected from magnesium, calcium, beryllium zinc,
Any one of carbon or combination.
Preferably, second doped layer includes p-type dopant and/or n-type dopant.
Preferably, second doped layer include any one of selected from magnesium, calcium, beryllium zinc, carbon or combination, and/or
Selected from any one of silicon, oxygen or combinations thereof.
Preferably, first composite laminate is formed in same manufacturing step with second composite laminate, and described
The dopant of two doped layers is selected from the p-type dopant.
Preferably, the doping type of second doped layer and/or doping concentration are set as being located at second doped layer
Channel in the gallium nitride layer of lower section is in the conductive state under zero-bias, and the second doped layer described in reverse blocking state is to institute
State the Channeling implantation hole in gallium nitride layer.
Preferably, the gate electrode and first doped layer form Ohmic contact or Schottky contacts.
Preferably, the source electrode and the drain electrode and the gallium nitride layer form Ohmic contact.
Preferably, before the step of forming the gallium nitride, further include：Nucleating layer is formed over the substrate；And
Buffer layer is formed on the nucleating layer, wherein the gallium nitride layer is located on the buffer layer.
Preferably, the forbidden bandwidth of the barrier layer is greater than the forbidden bandwidth of the gallium nitride layer.
Preferably, there are two-dimensional electron gas between the gallium nitride layer and barrier layer.
According to the gallium nitride transistor and its manufacturing method of the embodiment of the present disclosure, by being arranged in gate electrode and barrier layer
Between the first composite laminate reduce grid leakage current；By the way that the second composite laminate is added in drain electrode one end close to grid,
Drain electrode is in contact with each other with the second composite laminate, and contacts with barrier layer, when the first composite laminate and the second composite laminate exist
It is easy to operate when being made under the same processing step, save production cost.Meanwhile second composite laminate is injected as hole
Layer is realized under zero bias pressure condition, gallium nitride layer is in and leads by modulating the doping type and/or doping concentration of the second doped layer
Logical state, and it is efficiently injected into hole in off state, captured electronics is discharged, gallium nitride transistor dynamic on resistance is inhibited
Increase, increases the stability of dynamic electric resistor, improve the Stability and dependability of gallium nitride transistor.
Detailed description of the invention
In order to illustrate more clearly of the technical solution of the embodiment of the present disclosure, simple be situated between will be made to the attached drawing of embodiment below
It continues, it should be apparent that, the attached drawing in description below only relates to some embodiments of the present disclosure, rather than the limitation to the disclosure.
Fig. 1 shows the structural schematic diagram of the gallium nitride transistor of the embodiment of the present disclosure.
Fig. 2 shows the flow diagrams of the manufacture gallium nitride transistor of the embodiment of the present disclosure.
Fig. 3 shows the specific of the first composite laminate of formation and the second composite laminate that gallium nitride transistor is manufactured in Fig. 2
The schematic diagram of step.
Fig. 4 to Fig. 7 shows side cross-sectional view when embodiment of the present disclosure manufacture gallium nitride transistor.
Specific embodiment
To keep the above objects, features, and advantages of the disclosure more obvious and easy to understand, with reference to the accompanying drawing to the disclosure
Specific embodiment be described in detail.Elaborate in the de-scription many details in order to fully understand the disclosure, but
It is that the disclosure can also be implemented using other than the one described here other way, those skilled in the art can not disobey
Similar popularization is done in the case where back disclosure intension, therefore the disclosure is not limited by the specific embodiments disclosed below.Secondly,
Disclosure combination schematic diagram is described in detail, when the embodiment of the present disclosure is described in detail, for purposes of illustration only, indicating cuing open for device architecture
Face figure can disobey general proportion and make partial enlargement, and the schematic diagram is example, should not limit disclosure protection herein
Range.In addition, the three-dimensional space of length, width and depth should be included in actually manufacture.
Fig. 1 shows the structural schematic diagram of the gallium nitride transistor of the embodiment of the present disclosure.
As shown in Figure 1, the gallium nitride transistor of the embodiment of the present disclosure includes：Substrate 101, nucleating layer 102, buffer layer 103,
Gallium nitride layer 104, barrier layer 105, at least one first composite laminate 210, at least one second composite laminate 220, grid electricity
Pole 301, source electrode 302 and drain electrode 303.Wherein, the first composite laminate 210 includes：The first doped layer 211 stacked
With the first insert layer 212, the second composite laminate 220 includes：The second doped layer 221 stacked and the second insert layer 222.Gallium nitride
There are two-dimensional electron gas between layer 104 and barrier layer 105.
Nucleating layer 102 is located on substrate 101.Buffer layer 103 is located on nucleating layer 102.Gallium nitride layer 104 is located at buffer layer
On 103.Barrier layer 105 is located on gallium nitride layer 104, wherein the forbidden bandwidth of barrier layer 105 is greater than the taboo of gallium nitride layer 104
Bandwidth.
First composite laminate 210 is located on barrier layer 105, and further, the first insert layer 212 is located at the first doped layer
Between 211 and barrier layer 105, the first doped layer 211 is doped nitride, and the first insert layer 212 is dielectric material, further
Ground, the dopant distribution in the first doped layer 211 be component fix, any one of content gradually variational and component mutation, first mixes
Diamicton 211 includes any p-type dopant in magnesium, calcium, beryllium zinc, carbon or combination.In some preferred embodiments,
First insert layer 212 is between at least two first doped layers 211.
Second composite laminate 220 is located on barrier layer 105, and further, the second doped layer 221 is used as hole injection region,
Second doped layer 221 is doped nitride, and the second insert layer 222 is dielectric material.Further, in the second doped layer 221
Dopant distribution be component fix, any one of content gradually variational and component mutation.Second doped layer 221 include selected from magnesium, calcium,
Any p-type dopant in beryllium zinc, carbon or combination, and/or any n-type doping in silicon, oxygen or combinations thereof
Agent.The doping type and doping concentration of second doped layer 221 are set as being located at the gallium nitride layer 104 of 221 lower section of the second doped layer
In channel it is in the conductive state under zero-bias, in ditch of the second doped layer of reverse blocking state 221 into gallium nitride layer 104
Road injects hole.In some preferred embodiments, the second insert layer 222 is between at least two second doped layers 221.
Gate electrode 301 is located on the first composite laminate 210, and source electrode 302 is located on barrier layer 105, drain electrode
303 are located on the second composite laminate 220 and barrier layer 105.Further, gate electrode 301 is located at source electrode 302 and drain electrode
Between electrode 303, gate electrode 301 is in contact with each other with the first doped layer 211, gate electrode 301 and the formation of the first doped layer 211
Ohmic contact or Schottky contacts, source electrode 302 and drain electrode 303 pass through rapid thermal annealing (rapid thermal
Annealing, RTA) and the formation Ohmic contact of gallium nitride layer 104, the first part 303a and the second doped layer of drain electrode 303
221 are in contact with each other, and then make drain electrode 303 and the second doped layer 221 formation Ohmic contact, and second of drain electrode 303
303b is divided to contact with barrier layer 105.
Fig. 2 shows the flow diagrams of the manufacture gallium nitride transistor of the embodiment of the present disclosure.
In step S01, nucleating layer is formed on the substrate.As shown in figure 4, having after substrate 101 is cleaned up by metal
Chemical machine vapour deposition process (Metal Organic Chemical Vapor Deposition, MOCVD) or molecular beam epitaxy
(Molecular Beam Epitaxy, MBE) or other methods grow nucleating layer 102 on substrate 101.Wherein, substrate 101
Material may include silicon, silicon carbide or sapphire etc., and the material of nucleating layer 102 may include gallium nitride or aluminium nitride etc..
In step S02, buffer layer is formed on nucleating layer.As shown in figure 4, the grown buffer layer 103 on nucleating layer 102,
Wherein, the material of buffer layer 103 may include the semi-insulating high resistant gallium nitride of carbon auto-dope.
In step S03, gallium nitride layer is formed on the buffer layer.As shown in figure 4, the growing gallium nitride layer on buffer layer 103
104, wherein the material of gallium nitride layer 104 may include the gallium nitride of the unintentional doping of high mobility.
In step S04, barrier layer is formed on that gallium nitride layer.As shown in figure 4, growing barrier layer on gallium nitride layer 104
105, wherein there are two-dimensional electron gas between gallium nitride layer 104 and barrier layer 105, the forbidden bandwidth of barrier layer 105 is greater than nitrogen
Change the forbidden bandwidth of gallium layer 104, the material of barrier layer 105 may include aluminum gallium nitride, indium gallium aluminium of the aluminium component 5% to 30%
Nitrogen, aluminum nitride and other nitride.
In step S05, the first composite laminate and the second composite laminate are formed on barrier layer.As shown in figure 3, can pass through
Step S051 to S054 forms the first composite laminate and the second composite laminate on barrier layer, as shown in fig. 6, the first composite laminate
210 include the first doped layer 211 stacked and the first insert layer 212, and the second composite laminate 220 includes the second doped layer stacked
221 and second insert layer 222, wherein the second doped layer 221 is used as hole injection region, the first composite laminate 210 and second compound
Lamination 220 is formed simultaneously on barrier layer 105, i.e. the first doped layer 211 and the second doped layer 221, the first insert layer 212 and
Two insert layers 222 are formed in identical step respectively.Further, the step of the first composite laminate 210 of formation include：In gesture
The first insert layer 212 is formed in barrier layer 105, and the first doped layer 211 is formed in the first insert layer 212.In some preferred implementations
Example in, formed the first composite laminate 210 the step of include：The first insert layer is formed between at least two first doped layers 211
212.The step of forming the second composite laminate 220 include：The second insert layer 222 is formed on barrier layer 105, in the second insert layer
The second doped layer 221 is formed on 222.In some preferred embodiments, the step of the second composite laminate 220 of formation include：Extremely
The second insert layer 222 is formed between few two the second doped layers 221.Preferably, first composite laminate is answered with described second
Conjunction is stacked in same manufacturing step and is formed.
Further, the first doped layer 211 and the second doped layer 221 are respectively doped nitride, 212 He of the first insert layer
Second insert layer 222 is respectively dielectric material.Dopant distribution in first doped layer 211 and the second doped layer 221 is component
Any one of fixed, content gradually variational and component mutation.Further, distinguish in the first doped layer 211 and the second doped layer 221
Incorporation includes that any p-type dopant in magnesium, calcium, beryllium zinc, carbon or combination is mixed in the second doped layer 221 later
Enter including any p-type dopant in magnesium, calcium, beryllium zinc, carbon or combination, and/or in silicon, oxygen or combinations thereof
Any n-type dopant.The doping type and doping concentration of second doped layer 221 are set as being located under the second doped layer 221
Channel in the gallium nitride layer 104 of side is in the conductive state under zero-bias, in the second doped layer of reverse blocking state 221 to nitrogen
Change the Channeling implantation hole in gallium layer 104.Preferably, when the first composite laminate and second composite laminate are walked in same manufacture
When being formed in rapid, it includes selected from magnesium, calcium, beryllium zinc, carbon or combining that the first doped layer and the second doped layer mixs respectively
Any p-type dopant.
Step S051 to S054 is described in detail below in conjunction with Fig. 5 A to Fig. 6.
Insert layer is formed on step S051, barrier layer.As shown in Figure 5A, one layer is formed on doping potential barrier layer 105 to insert
Enter layer 202, the material of insert layer 202 includes aluminium nitride or silicon nitride etc..
In step S052, doped layer is formed in insert layer.As shown in Figure 5A, one layer of doping is formed in insert layer 202
Layer 201, wherein doped layer 201 includes：The binary such as indium, gallium, aluminium or polynary component fix, gradual change, mutation p-type nitridation
Object.In some preferred embodiments, the impurity of p-type nitride includes：Magnesium, calcium, beryllium zinc, carbon or combination.
As shown in Figure 5 B, in second embodiment of the present disclosure, on barrier layer 105, twice insertion layer is formed overlappingly
202 with doped layer 201.As shown in Figure 5 C, it in third embodiment of the present disclosure, is formed on barrier layer 105 repeatedly overlappingly
Insert layer 202 and doped layer 201.Specifically, in second composite laminate adjacent with the barrier layer, described second is inserted
Enter layer between second doped layer and the barrier layer, in two adjacent second composite laminates, wherein it
One second doped layer is contacted with another second insert layer；In addition, adjacent with the barrier layer described first
In composite laminate, first insert layer is between first doped layer and the barrier layer, described in adjacent two
In first composite laminate, first doped layer of one of them is contacted with another first insert layer.Wherein, second,
In 3rd embodiment, the thickness of every layer of insert layer 202 can be individually designed.
In step S053, the first composite laminate and the second composite laminate are formed.As shown in fig. 6, to doped layer 201 and insertion
Layer 202 carries out gluings, photoetching, etches, removes photoresist, and forms the first composite laminate 210 and second composite laminate 220, so that
The part of the surface of barrier layer 105 is exposed.
In step S054, the doping concentration of the second doped layer is adjusted.Specifically, as shown in fig. 6, the second doped layer 221 is
Hole injection region, by secondary doping adjust the second doped layer 221 doping concentration, such as with by injection silicon, oxygen or its
Combination carries out n-type doping, can also carry out injection magnesium, calcium, beryllium zinc, carbon or combination and carry out p-type doping, finally guarantee zero bias
Pressure keeps the two-dimensional electron gas formed in gallium nitride layer 104 in the conductive state, and in reverse blocking state, the second doped layer
221 can be injected hole, so that captured electronics discharges, increase the stability of device dynamic conducting resistance.In the reality of substitution
It applies in mode, the method for adjustment of doping concentration can also be replaced to realize by etching thinned method.
In step S06, source electrode is formed on barrier layer.As shown in fig. 7, source metal is deposited on barrier layer 105,
Source metal contact area is opened by gluing, photoetching, source electrode 302 is formed on barrier layer 105 using electron beam evaporation.
Wherein, the material of source metal includes titanium, aluminium, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or its alloy group
It closes, and makes to form Ohmic contact between source electrode 302 and gallium nitride layer 104 by annealing.
In step S07, gate electrode is formed on the first composite laminate.As shown in fig. 7, being deposited on the first composite laminate
Gate metal, by gluing, photoetching open gate metal contact region, using electron beam evaporation on the first doped layer 211 shape
At gate electrode 301.Gate electrode 301 is in contact with each other with the first doped layer 211.Wherein, the material of gate metal include titanium,
Aluminium, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or its alloy combination, gate electrode 301 and the first doped layer
Ohmic contact or Schottky contacts are formed by high annealing between 211.
In step S08, drain electrode is formed on barrier layer and the second composite laminate and gate electrode 301 is made to be located at source electrode
Between electrode 302 and drain electrode 303.As shown in fig. 7, the drain on part barrier layer 105 and the second composite laminate 220
Metal opens drain metal contacts region by gluing, photoetching, using electron beam evaporation or sputters at the second doped layer 221
With compound drain electrode 303 is formed on barrier layer 105, drain electrode 303 is in contact with each other with the second doped layer 221, wherein drain electrode
The material of metal includes titanium, aluminium, nickel, gold, silver, platinum, tungsten, copper, tantalum, molybdenum, titanium tungsten, titanium nitride or its alloy combination, drain electrode electricity
Ohmic contact is formed by annealing between pole 303 and gallium nitride layer 104, is passed through between drain electrode 303 and the second doped layer 221
High annealing forms Ohmic contact or Schottky contacts.
According to the open gallium nitride transistor for applying example of this hair, it is compound folded that first is accompanied between gate electrode and barrier layer
Layer, the first composite laminate include the first doped layer stacked and the first insert layer.First insert layer is for example made of dielectric material,
Can be used as the first doped layer etching cutoff layer can effectively reduce grid leakage current again.
In a preferred embodiment, which further includes the second composite laminate on the barrier layer, and second
Composite laminate includes the second doped layer stacked and the second insert layer.Second insert layer is for example made of dielectric material.Drain electrode electricity
Pole is in contact with each other with the second doped layer.Second doped layer is as hole injection layer, by the doping class for modulating the second doped layer
The method that type and/or doping concentration or etching are thinned, realizes under zero-bias, keeps gallium nitride layer in the conductive state and ending
State can be efficiently injected into hole, discharge captured electronics, and gallium nitride transistor dynamic on resistance is inhibited to increase, and increase dynamic
The stability of state resistance improves the Stability and dependability of gallium nitride transistor.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to embodiment of the disclosure, these embodiments details all there is no detailed descriptionthe, also not
Limiting the disclosure is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is the principle and practical application in order to preferably explain the disclosure, thus belonging to making
Technical field technical staff can be used using the disclosure and the modification on the basis of disclosure well.The disclosure is only by right
The limitation of claim and its full scope and equivalent.
Claims (40)
1. a kind of gallium nitride transistor, including：
Substrate；
Gallium nitride layer is located on the substrate；
Barrier layer is located on the gallium nitride layer；
At least one second composite laminate is located on the barrier layer；And
Gate electrode, source electrode and drain electrode are located on the barrier layer, and the gate electrode is located at the source electrode
Between electrode and the drain electrode,
Wherein, at least one described second composite laminate includes the second doped layer stacked and the second insert layer, the drain electrode electricity
The first part of pole contacts with the second doped layer described at least one, and the second part of the drain electrode connects with the barrier layer
Touching.
2. gallium nitride transistor according to claim 1, wherein the gallium nitride transistor includes one described second multiple
Lamination is closed, second insert layer is between second doped layer and the barrier layer.
3. gallium nitride transistor according to claim 1, wherein the gallium nitride transistor includes multiple described second multiple
Lamination is closed, the multiple second composite laminate stacks gradually,
In second composite laminate adjacent with the barrier layer, second insert layer be located at second doped layer and
Between the barrier layer,
In two adjacent second composite laminates, second doped layer of one of them and another second insertion
Layer contact.
4. gallium nitride transistor according to claim 1, wherein further include：At least one first composite laminate is located at institute
It states on barrier layer, at least one described first composite laminate includes the first doped layer stacked and the first insert layer, the grid
Electrode is in contact with each other with the first doped layer described at least one.
5. gallium nitride transistor according to claim 4, wherein the gallium nitride transistor includes one described first multiple
Lamination is closed, first insert layer is between first doped layer and the barrier layer.
6. gallium nitride transistor according to claim 4, wherein the gallium nitride transistor includes multiple described first multiple
Lamination is closed, the multiple first composite laminate stacks gradually,
In first composite laminate adjacent with the barrier layer, first insert layer be located at first doped layer and
Between the barrier layer,
In two adjacent first composite laminates, first doped layer of one of them and another first insertion
Layer contact.
7. gallium nitride transistor according to claim 1, wherein second doped layer is as hole injection region.
8. gallium nitride transistor according to claim 4, wherein first doped layer and second doped layer difference
For doped nitride, first insert layer and second insert layer are respectively dielectric material.
9. gallium nitride transistor according to claim 8, wherein in first doped layer and second doped layer
Dopant distribution be component fix, any one of content gradually variational and component mutation.
10. gallium nitride transistor according to claim 8, wherein first doped layer includes p-type dopant.
11. gallium nitride transistor according to claim 10, wherein first doped layer includes being selected from magnesium, calcium, beryllium
Any one of zinc, carbon or combination.
12. gallium nitride transistor according to claim 10, wherein second doped layer includes p-type dopant, and/
Or n-type dopant.
13. gallium nitride transistor according to claim 12, wherein second doped layer includes being selected from magnesium, calcium, beryllium
Any one of zinc, carbon or combination, and/or selected from any one of silicon, oxygen or combinations thereof.
14. gallium nitride transistor according to claim 12, wherein the dopant of second doped layer is selected from the p
Type dopant, wherein first composite laminate is formed in same manufacturing step with second composite laminate.
15. gallium nitride transistor according to claim 13, wherein the doping type of second doped layer and/or mix
Miscellaneous concentration be set as be located at second doped layer below gallium nitride layer in channel it is in the conductive state under zero-bias,
Channeling implantation hole of second doped layer described in reverse blocking state into the gallium nitride layer.
16. gallium nitride transistor according to claim 1, wherein the gate electrode is formed with first doped layer
Ohmic contact or Schottky contacts.
17. gallium nitride transistor according to claim 1, wherein the source electrode and the drain electrode with it is described
Gallium nitride layer forms Ohmic contact.
18. gallium nitride transistor according to any one of claims 1 to 17, wherein further include：
Nucleating layer is located on the substrate；And
Buffer layer, between the nucleating layer and the gallium nitride layer.
19. gallium nitride transistor according to claim 18, wherein the forbidden bandwidth of the barrier layer is greater than the nitridation
The forbidden bandwidth of gallium layer.
20. gallium nitride transistor according to claim 19, wherein there are two between the gallium nitride and the barrier layer
Dimensional electron gas.
21. a kind of manufacturing method of gallium nitride transistor, including：
Gallium nitride layer is formed on the substrate；
Barrier layer is formed on the gallium nitride layer；
At least one second composite laminate is formed on the barrier layer；And
Form gate electrode, source electrode and drain electrode on the barrier layer, and the gate electrode be formed in it is described
Between source electrode and the drain electrode,
Wherein, at least one described second composite laminate includes the second doped layer stacked and the second insert layer, the drain electrode electricity
The first part of pole contacts with the second doped layer described at least one, and the second part of the drain electrode connects with the barrier layer
Touching.
22. manufacturing method according to claim 21, wherein the step of described at least one second composite laminate of formation wraps
Include to form second composite laminate, formed second composite laminate the step of include：
Second insert layer is formed on the barrier layer；And
Second doped layer is formed in second insert layer.
23. manufacturing method according to claim 21, wherein the step of described at least one second composite laminate of formation wraps
Include to form multiple second composite laminates, formed multiple second composite laminates the step of include on the barrier layer according to
Secondary stacking forms multiple second composite laminates,
Wherein, in second composite laminate adjacent with the barrier layer, second insert layer is located at described second and mixes
Between diamicton and the barrier layer,
In two adjacent second composite laminates, second doped layer of one of them and another second insertion
Layer contact.
24. manufacturing method according to claim 21, further includes：
At least one first composite laminate is formed on the barrier layer, at least one described first composite laminate includes stacking
First doped layer and the first insert layer, the drain electrode are in contact with each other with first doped layer.
25. manufacturing method according to claim 24, wherein the step of described at least one first composite laminate of formation wraps
Include to form first composite laminate, formed first composite laminate the step of include：
First insert layer is formed on the barrier layer；And
First doped layer is formed in first insert layer.
26. manufacturing method according to claim 24, wherein the step of described at least one first composite laminate of formation wraps
Include to form multiple first composite laminates, formed multiple first composite laminates the step of include on the barrier layer according to
Secondary stacking forms multiple first composite laminates,
Wherein, in first composite laminate adjacent with the barrier layer, first insert layer is located at described first and mixes
Between diamicton and the barrier layer,
In two adjacent first composite laminates, first doped layer of one of them and another first insertion
Layer contact.
27. manufacturing method according to claim 21, wherein second doped layer is as hole injection region.
28. manufacturing method according to claim 24, wherein first doped layer and second doped layer are respectively
Doped nitride, first insert layer and second insert layer are respectively dielectric material.
29. manufacturing method according to claim 28, wherein mixing in first doped layer and second doped layer
Miscellaneous dose be distributed as component fix, any one of content gradually variational and component mutation.
30. manufacturing method according to claim 28, wherein first doped layer includes p-type dopant.
31. manufacturing method according to claim 30, wherein distinguish in first doped layer and second doped layer
Incorporation includes selected from any one of magnesium, calcium, beryllium zinc, carbon or combination.
32. manufacturing method according to claim 30, wherein second doped layer includes p-type dopant and/or N-shaped
Dopant.
33. manufacturing method according to claim 32, wherein second doped layer include selected from magnesium, calcium, beryllium zinc,
Any one of carbon or combination, and/or selected from any one of silicon, oxygen or combinations thereof.
34. manufacturing method according to claim 32, wherein first composite laminate and second composite laminate exist
It is formed in same manufacturing step,
The dopant of second doped layer is selected from the p-type dopant.
35. manufacturing method according to claim 33, wherein the doping type of second doped layer and/or doping are dense
It is in the conductive state under zero-bias to spend the channel for being set as being located in the gallium nitride layer below second doped layer, reversed
Channeling implantation hole of second doped layer described in off state into the gallium nitride layer.
36. manufacturing method according to claim 21, wherein the gate electrode and first doped layer form ohm
Contact or Schottky contacts.
37. manufacturing method according to claim 21, wherein the source electrode and the drain electrode and the nitridation
Gallium layer forms Ohmic contact.
38. according to any manufacturing method of claim 21 to 37, wherein before the step of forming the gallium nitride,
Further include：
Nucleating layer is formed over the substrate；And
Buffer layer is formed on the nucleating layer,
Wherein, the gallium nitride layer is located on the buffer layer.
39. the manufacturing method according to claim 38, wherein the forbidden bandwidth of the barrier layer is greater than the gallium nitride layer
Forbidden bandwidth.
40. manufacturing method according to claim 39, wherein there are Two-dimensional electrons between the gallium nitride layer and barrier layer
Gas.
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