CN106876471B - Dual trench UMOSFET device - Google Patents

Dual trench UMOSFET device Download PDF

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CN106876471B
CN106876471B CN201710208837.9A CN201710208837A CN106876471B CN 106876471 B CN106876471 B CN 106876471B CN 201710208837 A CN201710208837 A CN 201710208837A CN 106876471 B CN106876471 B CN 106876471B
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source
layer
gate
drift region
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CN106876471A (en
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汤晓燕
陈辉
宋庆文
张艺蒙
张玉明
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Xian University of Electronic Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The invention relates to a dual trench UMOSFET device. The device comprises a substrate region (1); the drift region (2), the epitaxial layer (3) and the source region (4) are sequentially stacked on the upper surface of the substrate region (1); the grid electrode is arranged in the drift region (2), the epitaxial layer (3) and the source region (4) and is positioned in the middle position of the double-groove UMOSFET device; the gate dielectric protection region (5) is arranged in the drift region (2) and is positioned below the gate; the source electrode (10) is arranged in the drift region (2), the epitaxial layer (3) and the source region layer (4) and is positioned at the position close to two sides of the double-groove UMOSFET device; the source groove corner protection region (6) is arranged in the drift region (2) and is positioned below the source electrode (10); and the drain electrode (11) is arranged on the lower surface of the substrate region (1). According to the invention, the Schottky contact is formed on the interfaces of the source electrode, the drift region and the epitaxial layer, so that the problem of 'power-on degradation' of the body diode is avoided, the number of additional Schottky diodes is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced.

Description

dual trench UMOSFET device
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a double-groove UMOSFET device.
Background
The wide band gap semiconductor material SiC has the excellent physical and chemical characteristics of larger forbidden band width, higher critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity and the like, and is suitable for manufacturing high-temperature, high-voltage, high-power and anti-irradiation semiconductor devices. In the field of power electronics, power MOSFETs have been widely used, and have the characteristics of simple gate drive, short switching time, and the like. Compared with the MOSFET with a transverse structure, the UMOSFET with the vertical structure has the advantages of small on-resistance and small cell size, and has wide application prospect.
However, in UMOSFETs, the electric field concentration at the trench gate corners can easily cause premature breakdown of the oxide layer there, which is even more severe for SiC materials. A layer of P + type doping area, namely a P + grid oxygen protection area, is designed at the bottom of the grid groove, so that a peak electric field at the bottom of the groove is transferred to a PN junction formed by the P + grid oxygen protection area and an N-drift area from a grid oxide layer, and the reliability problem caused by the grid oxygen electric field is further relieved. And the UMOSFET with the double-groove structure is used for further improving the breakdown characteristic of the device by notching the source electrode, wherein the depth of the region extending into the N-drift region is greater than the depth of the gate oxide in the N-drift region, and the electric field at the oxide layer is transferred to the corner of the source groove due to the existence of the source groove. Meanwhile, when a body diode of the MOSFET, which is used as a freewheeling path to continuously pass forward current, is used as a power switch in the converter, the MOSFET generates a "power-on degradation" phenomenon, which increases the on-resistance and the forward-conduction voltage drop of the diode and causes a reliability problem.
Therefore, in practical applications, a schottky diode with a turn-on voltage lower than that of a body diode is generally connected in parallel across the source and drain of the device to provide a free-wheeling path. It is clear that this approach greatly increases the complexity and cost of the circuit design.
disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a double-groove UMOSFET device.
Specifically, an embodiment of the present invention provides a dual-trench UMOSFET device, including:
A substrate region 1;
the drift region 2, the epitaxial layer 3 and the source region 4 are sequentially stacked on the upper surface of the substrate region 1;
The grid electrode is arranged in the drift region 2, the epitaxial layer 3 and the source region 4 and is positioned in the middle of the double-groove UMOSFET device;
the gate dielectric protection region 5 is arranged in the drift region 2 and is positioned below the gate;
The source electrode 10 is arranged in the drift region 2, the epitaxial layer 3 and the source region layer 4 and is positioned at the positions close to two sides of the double-groove UMOSFET device;
A source trench corner protection region 6, which is arranged in the drift region 2 and is located below the source electrode 10;
And the drain electrode 11 is arranged on the lower surface of the substrate region 1.
In one embodiment of the invention, the substrate region 1 is an N-type SiC material with a thickness of 200 μm to 500 μm and a doping concentration of 5 × 1018cm-3～1×1020cm-3And the doping ions are nitrogen ions.
In one embodiment of the invention, the drift region 2 is an N-type SiC material with a thickness of 10 μm to 20 μm and a doping concentration of 1 × 1015cm-3～6×1015cm-3And the doping ions are nitrogen ions.
In one embodiment of the present invention, the epitaxial layer 3 is a P-type SiC material with a thickness of 1 μm to 1.5 μm and a doping concentration of 1 × 1017cm-3The doping ions are aluminum ions.
In one embodiment of the invention, the source region 4 is an N-type SiC material with a thickness of 0.5 μm and a doping concentration of 5 × 1018cm-3And the doping ions are nitrogen ions.
in one embodiment of the present invention, the gate comprises a gate dielectric layer 7 and a gate layer 8; the gate dielectric layer 7 is SiO2A material having a thickness of 100 nm; the gate layer 8 is a ploy-Si material with a thickness of 2.4 μm and a width of 1.3 μm.
In one embodiment of the present invention, the gate dielectric protection region 5 is doped P-type with a doping concentration of 3 × 1018cm-3the doping ions are aluminum ions and the thickness thereof is 0.5 μm.
In one embodiment of the present invention, the source electrode 10 is made of Ti, Ni or Au material, and the drain electrode 11 is made of Ti, Ni or Au material.
In one embodiment of the present invention, the source trench corner protection region 6 is doped P-type with a doping concentration of 3 × 1018cm-3The doping ions are aluminum ions and the thickness thereof is 0.5 μm.
In one embodiment of the present invention, the dual trench UMOSFET device further comprises a gate electrode 9 and a passivation layer; wherein the passivation layer is disposed on the upper surface of the source region 4, and the gate electrode 9 is disposed in the passivation layer and connected to the gate electrode.
According to the embodiment, the Schottky contact is formed on the interface of the source electrode, the drift region and the epitaxial layer to replace an external Schottky diode to be used as a follow current path, so that the problem of 'power-on degradation' of a body diode is solved, the additional Schottky diode is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a dual-trench UMOSFET device according to an embodiment of the present invention;
Fig. 2 a-2 k are schematic diagrams of a process of a dual-trench UMOSFET device according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a dual-trench UMOSFET device according to an embodiment of the present invention. The dual trench UMOSFET device of the present invention comprises:
A substrate region 1;
The drift region 2, the epitaxial layer 3 and the source region 4 are sequentially stacked on the upper surface of the substrate region 1;
The grid electrode is arranged in the drift region 2, the epitaxial layer 3 and the source region 4 and is positioned in the middle of the double-groove UMOSFET device;
The gate dielectric protection region 5 is arranged in the drift region 2 and is positioned below the gate;
The source electrode 10 is arranged in the drift region 2, the epitaxial layer 3 and the source region layer 4 and is positioned at the positions close to two sides of the double-groove UMOSFET device;
A source trench corner protection region 6, which is arranged in the drift region 2 and is located below the source electrode 10;
And the drain electrode 11 is arranged on the lower surface of the substrate region 1.
Optionally, the substrate region 1 is an N-type SiC material with a thickness of 200 μm to 500 μm and a doping concentration of 5 × 1018cm-3～1×1020cm-3And the doping ions are nitrogen ions.
Optionally, the drift region 2 is an N-type SiC material with a thickness of 10 μm to 20 μm and a doping concentration of 1 × 1015cm-3～6×1015cm-3and the doping ions are nitrogen ions.
Optionally, the epitaxial layer 3 is a P-type SiC material, and has a thickness of 1 μm to 1.5 μm and a doping concentration of 1 × 1017cm-3The doping ions are aluminum ions.
Optionally, the source region 4 is an N-type SiC material with a thickness of 0.5 μm and a doping concentration of 5 × 1018cm-3And the doping ions are nitrogen ions.
Optionally, the gate comprises a gate dielectric layer 7 and a gate layer 8; the gate dielectric layer 7 is SiO2A material having a thickness of 100 nm; the gate layer 8 is a ploy-Si material with a thickness of 2.4 μm and a width of 1.3 μm.
Optionally, the gate dielectric protection region 5 is doped P-type with a doping concentration of 3 × 1018cm-3The doping ions are aluminum ions and the thickness thereof is 0.5 μm.
Optionally, the source electrode 10 is made of Ti, Ni or Au material, and the drain electrode 11 is made of Ti, Ni or Au material.
Optionally, the source trench corner protection region 6 is doped P-type with a doping concentration of 3 × 1018cm-3The doping ions are aluminum ions and the thickness thereof is 0.5 μm.
Optionally, the dual trench UMOSFET device further comprises a gate electrode 9 and a passivation layer; wherein the passivation layer is disposed on the upper surface of the source region 4, and the gate electrode 9 is disposed in the passivation layer and connected to the gate electrode.
Preferably, the depth of the source trench (i.e., source) is greater than the depth of the gate trench (i.e., gate), and the width of the source trench is equal to the width of the P + source trench corner protection region 6; the width of the gate groove is equal to the width of the P + gate oxide protection region 5, the interface between the source electrode 10 and the drift region 2 and the epitaxial layer 3 is Schottky contact, and the rest is ohmic contact.
Alternatively, the source trench depth is 3 μm and the gate trench depth is 2.5 μm, formed by ICP etching. The widths of the source trench and the source trench corner protection region 6 are 1 μm, respectively, and the widths of the gate trench and the gate dielectric protection region (e.g., gate oxide protection region) 5 are 1.5 μm, respectively.
Depositing field oxide layer or Si3N4The layer is used as a passivation layer, and the passivation layer is etched to form an electrode hole. The gate electrode 9, the drain electrode 11 and the source electrode 10 and their schottky contacts are formed by electron beam evaporation of metal.
According to the embodiment of the invention, the Schottky diode is introduced into the source groove to replace an externally-connected Schottky diode as a follow current path, so that the problem of 'power-on degradation' of the body diode is avoided, the extra Schottky diode is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced.
Example two
Referring to fig. 2a to fig. 2k, fig. 2a to fig. 2k are schematic process diagrams of a dual-trench UMOSFET device according to an embodiment of the present invention, and the method includes the following steps:
Step a, epitaxially growing an N-drift region 2 on an N-type SiC substrate 1, as shown in fig. 2 a.
Firstly, the thickness is 200 μm, the nitrogen ion doping concentration is 5 × 1018cm-3The N-type SiC substrate of (1) was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 10 μm and a nitrogen ion doping concentration of 1X 10 over the entire SiC substrate 115cm-3N-drift region 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.
And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 2 b.
A layer of thickness is grown on the N-drift region 21 μm, Al ion doping concentration of 1 × 1017cm-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.
and c, epitaxially growing an N + source region layer 4 as shown in FIG. 2 c.
A layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 318cm-3n + source region layer 4. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.
And d, etching to form a gate groove as shown in FIG. 2 d.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6And O248sccm and 12sccm, respectively.
And e, performing multiple times of Al ion self-alignment injection in the N-drift region 2 by using the etching mask of the gate trench, as shown in FIG. 2 e.
The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2Is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The injection temperature of the P + gate oxide protection region 5 is 650 ℃.
Step f, etching to form a source groove as shown in FIG. 2 f.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6And O248sccm and 12sccm, respectively.
And g, carrying out multiple times of Al ion self-alignment injection in the N-drift region 2 by utilizing the etching mask of the source groove, as shown in figure 2 g.
Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2Is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.
And cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.
Step h, preparing the groove gate dielectric 7 by using SiO as a material2As shown in fig. 2 h.
Preparation of SiO by dry oxygen process at 1150 deg.C2The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO2Roughness of the film surface.
Step i, preparing a poly Si gate as shown in FIG. 2 i.
And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.
Step j, preparing a passivation layer as shown in fig. 2 j.
Depositing a layer of field oxygen or Si on the surface of the device3N4Layer, photoresist-coated lithography, etching the passivation layer to form electrode contactsAnd (4) hole drilling, finally removing the glue and cleaning.
Step k, preparing the electrode, as shown in fig. 2 k.
Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.
And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift region 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift region 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.
EXAMPLE III
Referring again to fig. 2 a-2 k, the preparation method may further include the following steps:
Step a, epitaxially growing an N-drift region 2 on an N-type SiC substrate 1, as shown in fig. 2 a.
Firstly, the thickness is 500 μm, the doping concentration of nitrogen ion is 1 × 1020cm-3The N-type SiC substrate 1 was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 20 μm and a nitrogen ion doping concentration of 3X 10 over the entire SiC substrate 115cm-3N-drift region 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.
And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 2 b.
A layer with the thickness of 1.5 μm and the Al ion doping concentration of 1 × 10 is grown on the N-drift region 217cm-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.
And c, epitaxially growing an N + source region layer 4 as shown in FIG. 2 c.
A layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 318cm-3N + source region layer 4. The process conditions are as follows: the temperature is 1600 ℃, the pressure is 100mbar, the reaction gases are silane and propane, and the carrier gas is pure hydrogenThe impurity source is liquid nitrogen.
And d, etching to form a gate groove as shown in FIG. 2 d.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6And O248sccm and 12sccm, respectively.
And e, performing multiple times of Al ion self-alignment injection in the N-drift region 2 by using the etching mask of the gate trench, as shown in FIG. 2 e.
The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The injection temperature of the P + gate oxide protection region 5 is 650 ℃.
Step f, etching to form a source groove as shown in FIG. 2 f.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6and O248sccm and 12sccm, respectively.
And g, carrying out multiple times of Al ion self-alignment injection in the N-drift region 2 by utilizing the etching mask of the source groove, as shown in figure 2 g.
Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2Is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.
and cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.
Step h, preparing the groove gate dielectric 7 by using SiO as a material2As shown in fig. 2 h.
Preparation of SiO by dry oxygen process at 1150 deg.C2the thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO2roughness of the film surface.
Step i, preparing a poly Si gate as shown in FIG. 2 i.
And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.
Step j, preparing a passivation layer as shown in fig. 2 j.
Depositing a layer of field oxygen or Si on the surface of the device3N4and coating glue and photoetching, corroding the passivation layer to form an electrode contact hole, and finally removing the glue and cleaning.
step k, preparing the electrode, as shown in fig. 2 k.
Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.
And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift region 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift region 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.
Example four
Referring again to fig. 2 a-2 k, the preparation method may further include the following steps:
Step a, epitaxially growing an N-drift region 2 on an N-type Si substrate 1, as shown in fig. 2 a.
Firstly, the thickness is 300 μm, the doping concentration of nitrogen ion is 1 × 1019cm-3The N-type SiC substrate of (1) was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 15 μm and a nitrogen ion doping concentration of 6X 10 over the entire SiC substrate 115cm-3N-drift region 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.
And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 2 b.
A layer with the thickness of 1.3 μm and the Al ion doping concentration of 1 × 10 is grown on the N-drift region 217cm-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.
And c, epitaxially growing an N + source region layer 4 as shown in FIG. 2 c.
a layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 318cm-3n + source region layer 4.
The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.
And d, etching to form a gate groove as shown in FIG. 2 d.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6And O248sccm and 12sccm, respectively.
And e, performing multiple times of Al ion self-alignment injection in the N-drift region 2 by using the etching mask of the gate trench, as shown in FIG. 2 e.
The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 1013cm-2、4.69×1013cm-2、3.27×1013cm-2And 2.97X 1013cm-2Is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The injection temperature of the P + gate oxide protection region 5 is 650 ℃.
Step f, etching to form a source groove as shown in FIG. 2 f.
Firstly, magnetron sputtering a layerThe Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF6And O248sccm and 12sccm, respectively.
And g, carrying out multiple times of Al ion self-alignment injection in the N-drift region 2 by utilizing the etching mask of the source groove, as shown in figure 2 g.
Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 1013cm-2、4.69×1013cm-2、3.27×1013cm-2and 2.97X 1013cm-2Is implanted into the implanted region of the N-drift region 2 in four times to a depth of 0.5 μm and a concentration of 3 × 1018cm-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.
And cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.
Step h, preparing a groove grid mediumMass 7, the material used is SiO2As shown in fig. 2 h.
Preparation of SiO by dry oxygen process at 1150 deg.C2The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO2Roughness of the film surface.
step i, preparing a poly Si gate as shown in FIG. 2 i.
And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.
Step j, preparing a passivation layer as shown in fig. 2 j.
depositing a layer of field oxygen or Si on the surface of the device3N4And coating glue and photoetching, corroding the passivation layer to form an electrode contact hole, and finally removing the glue and cleaning.
Step k, preparing the electrode, as shown in fig. 2 k.
Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.
And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift region 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift region 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.
In summary, the present disclosure describes embodiments of a dual-trench UMOSFET device and a method for manufacturing the same according to embodiments of the present disclosure with specific examples, and the descriptions of the above embodiments are only used to help understanding the method and the core concept of the present disclosure; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.

Claims (10)

1. A dual trench UMOSFET device, comprising:
A substrate region (1);
The drift region (2), the epitaxial layer (3) and the source region (4) are sequentially stacked on the upper surface of the substrate region (1);
The grid electrode is arranged in the drift region (2), the epitaxial layer (3) and the source region (4) and is positioned in the middle position of the double-groove UMOSFET device;
The gate dielectric protection region (5) is arranged in the drift region (2) and is positioned below the gate;
The source electrode (10) is arranged in the drift region (2), the epitaxial layer (3) and the source region layer (4) and is positioned at the position close to two sides of the double-groove UMOSFET device, the depth of the source electrode (10) is greater than that of the grid electrode, the interface between the source electrode (10) and the drift region (2) and the epitaxial layer (3) is Schottky contact, and the rest is ohmic contact;
the source groove corner protection region (6) is arranged in the drift region (2) and is positioned below the source electrode (10);
And the drain electrode (11) is arranged on the lower surface of the substrate region (1).
2. The dual-tub UMOSFET device of claim 1, characterized in that the substrate region (1) is an N-type SiC material with a thickness of 200 to 500 μm and a doping concentration of 5 x 1018cm-3～1×1020cm-3And the doping ions are nitrogen ions.
3. The dual-trench UMOSFET device of claim 1, wherein said drift region (2) is an N-type SiC material with a thickness of 10-20 μm and a doping concentration of 1 x 1015cm-3～6×1015cm-3And the doping ions are nitrogen ions.
4. The dual-trench UMOSFET device according to claim 1, wherein said epitaxial layer (3) is a P-type SiC material having a thickness of1-1.5 μm with a doping concentration of 1 × 1017cm-3The doping ions are aluminum ions.
5. The dual-trench UMOSFET device of claim 1, wherein said source region (4) is an N-type SiC material with a thickness of 0.5 μm and a doping concentration of 5 x 1018cm-3And the doping ions are nitrogen ions.
6. The dual-tub UMOSFET device of claim 1, wherein the gate comprises a gate dielectric layer (7) and a gate layer (8); the gate dielectric layer (7) is SiO2A material having a thickness of 100 nm; the gate layer (8) is a ploy-Si material, and has a thickness of 2.4 μm and a width of 1.3 μm.
7. The dual-tub UMOSFET device of claim 6, wherein said gate dielectric protection region (5) is P-doped with a doping concentration of 3 x 1018cm-3The doping ions are aluminum ions and the thickness thereof is 0.5 μm.
8. The dual trench UMOSFET device of claim 1, wherein the source (10) is of Ti, Ni or Au material and the drain (11) is of Ti, Ni or Au material.
9. The dual trench UMOSFET device of claim 1, wherein the source trench corner protection region (6) is P-doped with a doping concentration of 3 x 1018cm-3The doping ions are aluminum ions and the thickness thereof is 0.5 μm.
10. The dual trench UMOSFET device of claim 1, further comprising a gate electrode (9) and a passivation layer; the passivation layer is arranged on the upper surface of the source region (4), and the gate electrode (9) is arranged in the passivation layer and connected with the gate electrode.
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CN102403315A (en) * 2010-09-07 2012-04-04 株式会社东芝 Semiconductor device
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