CN116190420B - Fast recovery diode structure and preparation method thereof - Google Patents
Fast recovery diode structure and preparation method thereof Download PDFInfo
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- 238000011084 recovery Methods 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 48
- 238000005468 ion implantation Methods 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 7
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- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
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Abstract
The invention provides a fast recovery diode structure and a preparation method thereof.A penetrating heavily doped P column region is formed in a middle doped N-type drift region, so that a horizontal PN junction is formed in the N-type drift region, and the N-type drift region has high resistivity when the diode is turned off reversely, so that the diode bears higher reverse bias voltage; when the diode is conducted in the forward direction, the doping concentration of the N-type drift region can be recovered rapidly, so that the resistivity of the diode is reduced to obtain lower forward voltage drop, and the loss of the device is reduced; when the diode is in forward conduction, the lightly doped N well region is positioned below the P type heavily doped region, so that the P type heavily doped region can be isolated, the distribution state of current carriers is finally improved, and when the diode is in reverse bias, a current channel between the lightly doped N well region and the trench gate is reversely shaped into a P type, so that the P type heavily doped region is communicated with the P type lightly doped region, and the reverse surge resistance of the device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a fast recovery diode structure and a preparation method thereof.
Background
The IGBT (Insulated Gate Bipolar Transistor ) is a composite full-control voltage-driven power semiconductor device composed of a bipolar triode and an insulated gate field effect transistor, and has the advantages of high input impedance of the metal-oxide semiconductor field effect transistor and low conduction voltage drop of the power transistor. IGBTs are typically used with FRDs (Fast Recovery Diode, fast recovery diodes) that mainly play a role in freewheeling, clamping, and buffering in the circuit.
In the practical use process of the existing IGBT, a diode matched with the IGBT is usually of a P-I-N structure, wherein I is an N drift region, a larger doping concentration difference can be formed between the I drift region and a low-doped P emission region due to higher resistivity of the N drift region, voltage resistance is higher when the width of the N drift region is wider, but larger forward voltage drop is caused at the same time, loss in conduction is increased, a device softness of the diode is insufficient in the switching process due to a heavily-doped P emitter, current oscillation is easily damaged in the reverse recovery process, and surge current resistance of the diode is insufficient due to the low-doped P emission region, so that failure risk is increased.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to a fast recovery diode structure and a method for manufacturing the same, which are used to solve the problems of the prior art that the diode can reduce forward voltage drop, reduce conduction loss, and have appropriate softness and higher reliability when being used in combination with an IGBT.
To achieve the above and other related objects, the present invention provides a fast recovery diode structure comprising:
a cathode metal layer;
the N-type substrate is positioned above the cathode metal layer and connected with the cathode metal layer;
the N-type drift region is positioned above the N-type substrate and connected with the N-type substrate;
the P-type lightly doped region is positioned above the N-type drift region and is connected with the N-type drift region;
the trench gate comprises a gate electrode and a gate oxide dielectric layer wrapping the gate electrode, the trench gate is positioned in the P-type lightly doped region, and the depth of the trench gate is smaller than that of the P-type lightly doped region;
the lightly doped N well region is positioned in the region between the two groove gates, and the depth of the lightly doped N well region is smaller than that of the groove gates;
the P-type heavily doped region is positioned in the lightly doped N well region, the side part of the P-type heavily doped region is connected with the trench gate, and the depth of the P-type heavily doped region is smaller than that of the lightly doped N well region;
and the anode metal layer is positioned above the P-type lightly doped region and is respectively connected with the tops of the P-type lightly doped region, the lightly doped N well region and the P-type heavily doped region.
Optionally, the N-type drift region includes a middle-doped N-type drift region and a lightly-doped N-type drift region, wherein the middle-doped N-type drift region is far away from the N-type substrate, and a heavily-doped P-pillar region penetrating the middle-doped N-type drift region is formed in the middle-doped N-type drift region.
Optionally, the doping concentration of the medium doped N-type drift region is 1E15cm -3 ～1E17cm -3 The doping concentration of the lightly doped N-type drift region is 1E11cm -3 ～1E14cm -3 The doping concentration of the heavily doped P column region is 1E16cm -3 ～1E18cm -3 。
Optionally, the doping concentration of the P-type lightly doped region is smaller than the doping concentration of the P-type heavily doped region.
Optionally, the N-type substrate is heavily doped and has a doping concentration of 1E17cm -3 ～1E20cm -3 。
Optionally, the thickness of the gate oxide dielectric layer is
The application also provides a preparation method of the fast recovery diode, which comprises the following steps:
providing an N-type substrate, wherein the N-type substrate comprises a front surface and a back surface which are oppositely arranged, an N-type drift region is formed on the front surface of the N-type substrate, and the N-type drift region comprises a lightly doped N-type drift region and a medium doped N-type drift region;
forming a P-type lightly doped region above the N-type drift region;
performing ion implantation on the P-type lightly doped region to form a lightly doped N well region;
etching the P-type lightly doped region to form trench gates on two sides of the lightly doped N well region respectively, wherein the trench gates comprise grid electrodes and gate oxide dielectric layers wrapping the grid electrodes, and the depth of the lightly doped N well region is smaller than that of the trench gates;
performing ion implantation on the lightly doped N well region to form a P-type heavily doped region with the side part connected with the trench gate, wherein the depth of the P-type heavily doped region is smaller than that of the lightly doped N well region;
depositing metal above the P-type lightly doped region to form an anode metal layer, wherein the anode metal layer is positioned above the P-type lightly doped region and is respectively connected with the tops of the P-type lightly doped region, the lightly doped N well region and the P-type heavily doped region;
and carrying out a thinning process on the N-type substrate and depositing metal on the back surface of the N-type substrate to form a cathode metal layer.
Optionally, the heavily doped P-pillar region is formed at the same time as the middle doped N-type drift region, and the heavily doped P-pillar region penetrates through the middle doped N-type drift region.
Optionally, the ion implantation dosage of the P-type lightly doped region is 1E13cm -2 The ion implantation dosage of the P-type heavily doped region is 1E14cm -2 ～1E16cm -2 The ion implantation dosage of the lightly doped N well region is 1E14cm -2 ～1E16cm -2 。
Alternatively, the thickness of the anode metal layer is 4 μm to 6 μm, and the thickness of the cathode metal layer is 1 μm to 3 μm.
As described above, the fast recovery diode structure and the preparation method thereof have the following beneficial effects compared with the prior art:
1) The formed lightly doped N well region can improve the concentration gradient distribution of carriers in the N type drift region, so that the softness of the device is improved.
2) When the diode bears reverse bias, the N-type groove between the P-type heavy doping region and the P-type light doping region is reversely formed into a P-type, so that a current channel is formed, the P-type heavy doping region and the P-type light doping region are communicated with each other, the doping concentration of the P-type light doping region can be increased, and the reverse surge resistance of the device is improved; when the diode is conducted in the forward direction, the N-type groove is not in an inversion mode, so that the P-type heavily doped region does not influence the doping concentration of the P-type lightly doped region, and the device is ensured to have enough softness.
3) The heavily doped P column region is formed in the middle doped N type drift region, so that a horizontal P+N junction is formed, the contact area of a PN junction is increased, the antistatic capability of the device is improved, carriers in the middle doped N type drift region are consumed by the horizontal P+N junction when the diode is turned off, and an N type drift region with high resistivity is formed, so that the device has higher voltage withstand capability and returns to the original doping concentration when being turned on in the forward direction, the drift region has higher doping level when the diode is turned on in the forward direction, and lower forward voltage drop is further obtained to reduce the loss of the device.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a fast recovery diode structure according to the present invention.
Fig. 2 is a schematic cross-sectional view of an N-type substrate in the structure of the fast recovery diode of the present invention.
Fig. 3 is a schematic cross-sectional view illustrating the formation of an N-type drift region and a heavily doped P-pillar region in the structure of the fast recovery diode of the present invention.
Fig. 4 is a schematic cross-sectional view illustrating a P-type lightly doped region formed in the structure of the fast recovery diode according to the present invention.
Fig. 5 is a schematic cross-sectional view illustrating a structure of forming a lightly doped N-well region in the fast recovery diode of the present invention.
Fig. 6 is a schematic cross-sectional view illustrating a trench formed in a structure of a fast recovery diode according to the present invention.
Fig. 7 is a schematic cross-sectional view showing the formation of a trench gate in the structure of the fast recovery diode of the present invention.
Fig. 8 is a schematic cross-sectional view illustrating the formation of a P-type heavily doped region in the structure of the fast recovery diode according to the present invention.
Fig. 9 is a schematic cross-sectional view of a fast recovery diode structure according to the present invention.
Fig. 10 is a schematic cross-sectional view of a fast recovery diode structure according to a second embodiment of the invention.
Description of element reference numerals
101 N-type substrate
102 N-type drift region
1021. Lightly doped N-type drift region
1022. Middle doped N-type drift region
103. Heavily doped P column region
104 P-type lightly doped region
105. Trench gate
1051. Grid electrode
1052. Gate oxide dielectric layer
106. Groove(s)
107. Lightly doped N well region
108 P-type heavily doped region
109. Anode metal layer
110. Cathode metal layer
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
Please refer to fig. 1 to 10. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
As shown in fig. 1, a flowchart of a method for manufacturing a fast recovery diode according to an embodiment of the present application is shown, where the method includes the following steps:
s1: providing an N-type substrate 101, wherein the N-type substrate 101 comprises a front surface and a back surface which are oppositely arranged, an N-type drift region 102 is formed on the front surface of the N-type substrate 101, and the N-type drift region 102 comprises a lightly doped N-type drift region 1021 and a medium doped N-type drift region 1022;
s2: forming a P-type lightly doped region 104 above the N-type drift region 102;
s3: ion implantation is carried out on the P-type lightly doped region 104 to form a lightly doped N well region 107;
s4: etching the P-type lightly doped region 104 to form trench gates 105 on two sides of the lightly doped N well region 107, wherein the trench gates 105 comprise a gate 1051 and a gate oxide dielectric layer 1052 wrapping the gate 1051, and the depth of the lightly doped N well region 107 is smaller than that of the trench gates 105;
s5: ion implantation is carried out on the lightly doped N well region 107 to form a P type heavily doped region 108 with the side part connected with the trench gate 105, and the depth of the P type heavily doped region 108 is smaller than that of the lightly doped N well region 107;
s6: depositing metal above the P-type lightly doped region 104 to form an anode metal layer 109, wherein the anode metal layer 109 is positioned above the P-type lightly doped region 104 and is respectively connected with the tops of the P-type lightly doped region 104, the lightly doped N well region 107 and the P-type heavily doped region 108;
s7: the N-type substrate 101 is thinned and metal is deposited on the back side of the N-type substrate 101 to form the cathode metal layer 110.
The following describes the preparation method of the fast recovery diode with reference to the accompanying drawings, specifically as follows:
in step S1, referring to fig. 1 to 3, an N-type substrate 101 is provided, the N-type substrate 101 includes a front surface and a back surface disposed opposite to each other, and an N-type drift region 102 is formed on the front surface of the N-type substrate 101, and the N-type drift region 102 includes a lightly doped N-type drift region 1021 and a middle doped N-type drift region 1022.
Specifically, as shown in fig. 2, in the embodiment of the present invention, a silicon substrate is selected as the N-type substrate 101, and an N-type drift region 102 is formed on the N-type substrate 101, where the N-type drift region 102 includes a lightly doped N-type drift region 1021 and a moderately doped N-type drift region 1022. Wherein the middle doped N-type drift region 1022 is disposed far from the N-type substrate 101, and the doping concentration of the middle doped N-type drift region 1022 is 1E15cm -3 ～1E17cm -3 The lightly doped N-type drift region 1021 is arranged close to the N-type substrate 101 and has a doping concentration of 1E11cm -3 ～1E14cm -3 。
Alternatively, as shown in fig. 2, in the embodiment of the present invention, the N-type substrate 101 is an N-type silicon substrate, the type of the N-type substrate 101 may be other types well known in the art, which is not limited in this application, and the ion doping concentration of the N-type substrate 101 is 1E17cm -3 ～1E20cm -3 For example, the doping concentration of the N-type substrate 101 may be selected to be 1E17cm according to design requirements -3 、1E18cm -3 、1E19cm -3 Or 1E20cm -3 。
As an example, the formation of the middle-doped N-type drift region 1022 may further include a step of forming the heavily doped P-pillar region 103 by a multi-layer epitaxy process and the heavily doped P-pillar region penetrates the middle-doped N-type drift region.
Specifically, as shown in fig. 3, in the embodiment of the present invention, the middle doped N-type drift region 1022 is located above the lightly doped N-type drift region 1021, and the heavily doped P-pillar regions 103 are formed in the middle doped N-type drift region 1022 at alternating intervals and uniformly arranged. Optionally, the heavily doped P-pillar region 103 has a boron ion doping concentration of 1.0x10 16 cm -3 ～1.0×10 18 cm -3 。
Specifically, in the embodiment of the present invention, the heavily doped P column regions 103 are alternately formed in the middle doped N-type drift region 1022 through heteroepitaxial growth, and the adjacent middle doped N-type drift region 1022 and heavily doped P column regions 103 form a p+n junction in the horizontal direction, thereby forming a super junction structure. When the diode is turned off reversely due to the super junction structure, the depletion regions are formed at the two sides of the middle doped N-type drift region 1022 at the same time, so that carriers in the middle doped N-type drift region 1022 are depleted, the resistivity of the diode is improved, and the voltage withstand capability of the diode is finally improved; when the diode is in forward conduction, the P-type lightly doped region 104 and the N-type substrate 101 can both inject carriers into the N-type drift region 102, so that the doping concentration of the N-type drift region 102 is quickly recovered, and the resistivity can be reduced to obtain lower forward voltage drop, thereby achieving the purpose of reducing the loss of the device.
In step S2, referring to fig. 1 and 4, a P-type lightly doped region 104 is formed above the N-type drift region 102.
Specifically, as shown in fig. 4, in the embodiment of the present invention, a lightly doped N-type drift region 1021 is formed above an N-type drift region 102, and then an ion implantation process is performed on the lightly doped N-type drift region 1021 to form a P-type lightly doped region 104, wherein the boron ion implantation concentration of the P-type lightly doped region 104 is 1E13cm -2 . The P-type lightly doped region 104 can control the junction depth of the P-type lightly doped region 104 by controlling the implantation energy and the subsequent junction pushing temperature and time in the ion implantation process, which are well known to those skilled in the art and will not be described herein.
In step S3, referring to fig. 1 and 5, ion implantation is performed on the P-type lightly doped region 104 to form a lightly doped N-well region 107.
Optionally, in the embodiment of the present invention, ion implantation is performed on the middle position region of the P-type lightly doped region 104, so as to form a lightly doped N-well region 107, where the phosphorus ion implantation concentration of the lightly doped N-well region 107 is 1E14cm -2 ～1E16cm -2 . Lightly doped N well region 107 can control the lightly doped N well by controlling the implantation energy in the ion implantation process and the parameters such as the subsequent junction pushing temperature and timeThe junction depth of region 107, a process well known to those skilled in the art, is not described in detail herein.
Specifically, as shown in fig. 5, in the embodiment of the present invention, a first mask (not shown) is formed on top of the P-type lightly doped region 104 by a deposition method, where the first mask is an ion implantation mask of the lightly doped N-well region 107, and the first mask is removed after the lightly doped N-well region 107 is formed. Then, an ion implantation process is used to form the lightly doped N-well region 107, wherein the lightly doped N-well region 107 is flush with the top of the P-type lightly doped region 104, and the depth of the lightly doped N-well region 107 is smaller than the depth of the P-type lightly doped region 104, i.e. the lightly doped N-well region 107 and the N-type drift region 102 are not contacted with each other.
In step S4, referring to fig. 1 and 6, the P-type lightly doped region 104 is etched to form trench gates 105 on both sides of the lightly doped N-well region 107, the trench gates 105 include a gate 1051 and a gate oxide dielectric layer 1052 surrounding the gate 1051, and the depth of the lightly doped N-well region 107 is smaller than the depth of the trench gates 105.
Specifically, as shown in fig. 6, after the lightly doped N-well region 107 is formed, a second mask is formed again on top of the P-type lightly doped region 104, and then the P-type lightly doped region 104 is etched to form the trench 106, wherein the depth of the trench 106 is smaller than the depth of the P-type lightly doped region 104 and larger than the depth of the lightly doped N-well region 107. In the embodiment of the present invention, the number of trenches 106 is 2, and the trenches are respectively located at two sides of the lightly doped N-well region 107 and connected to the lightly doped N-well region 107, further, as shown in fig. 7, a gate oxide dielectric layer 1052 is formed on the inner wall of the trench 106, wherein the thickness of the gate oxide dielectric layer 1052 is as followsThe trench 106 is then filled with polysilicon to form the gate 1051, and further, the excess polysilicon needs to be removed by a CMP process after forming the gate 1051 so that the gate 1051 is flush with the top of the P-type lightly doped region 104.
In this embodiment, before the CMP process is performed on the gate 1051, the second mask is also removed by an etching process, then a gate oxide dielectric layer 1052 is formed above the P-type lightly doped region 104, and the gate oxide dielectric layer 1052 outside the trench 106 is etched away so that the gate oxide dielectric layer 1052 completely encapsulates the gate 1051, so that the gate 1051 and the gate oxide dielectric layer 1052 together form the trench gate 105, and since the depth of the trench 106 is smaller than the depth of the P-type lightly doped region 104, the depth of the lightly doped N-well region 107 is smaller than the depth of the formed trench gate 105, and in addition, the gate 1051 is connected to the anode metal layer 109 through an external driver, and the nature of the driver is a resistor, so that when the diode is in a reverse bias state, an induced current is generated under the action of a voltage of a change in the gate capacitance, and a negative gate voltage is generated by the induced current flowing through the driver.
In step S5, referring to fig. 1 and 8, ion implantation is performed on the lightly doped N-well region 107 to form a P-type heavily doped region 108 with a side connected to the trench gate 105, and the depth of the P-type heavily doped region 108 is smaller than that of the lightly doped N-well region 107.
Optionally, an ion implantation process is performed on top of the lightly doped N-well region 107 and an anneal is performed, thereby forming a P-type heavily doped region 108, the P-type heavily doped region 108 being located in a region between the two trench gates 105 and the sides of the P-type heavily doped region 108 being connected to the trench gates 105.
Specifically, as shown in fig. 8, a third mask is formed again on top of the lightly doped N-well region 107, where the third mask is an implantation mask of the P-type heavily doped region 108, and is removed in the subsequent process, and an ion implantation process is used to form the P-type heavily doped region 108 in the lightly doped N-well region 107, in this embodiment, the number of the P-type heavily doped regions 108 is 2, the P-type heavily doped region 108 includes a top and a side, where the top of the P-type heavily doped region 108 is flush with the lightly doped N-well region 107, the side of the P-type heavily doped region 108 is connected with the trench gate 105, and the ion implantation concentration of the P-type heavily doped region 108 is 1E14cm -2 ～1E16cm -2 And the depth of the P-type heavily doped region 108 is less than the depth of the trench gate 105. Since the gate electrode 1051 is connected to the anode metal layer 109 by an external driver, which is essentially a resistor, the driver can regulate the voltage applied to the gate electrode 1051. When the diode is in a reverse bias state, the gate capacitance generates sense under the action of the changed voltageThe induced current flowing through the driver generates a negative gate voltage, so that the gate 1051 adsorbs carriers of the lightly doped N-well region 107 to the surface of the gate oxide dielectric layer 1052 under the action of the negative gate voltage, and the contact area between the lightly doped N-well region 107 and the trench gate 105 is reversely shaped into a P-type, so that the P-type heavily doped region 108 is communicated with the P-type lightly doped region 104, and the softness and reverse surge resistance of the device are improved. When the diode is in the on state, the contact area between the lightly doped N-well region 107 and the trench gate 105 is not inverted to be P-type, and the lightly doped N-well region 107 is located below the P-type heavily doped region 108, so that the P-type heavily doped region 108 can be blocked to improve the carrier distribution state.
In step S6, referring to fig. 1 and 9, an anode metal layer 109 is formed by depositing metal on the P-type lightly doped region 104, and the anode metal layer 109 is located on the P-type lightly doped region 104 and is connected to the tops of the P-type lightly doped region 104, the lightly doped N-well region 107 and the P-type heavily doped region 108, respectively.
Specifically, as shown in fig. 9, in the present embodiment, a metal is deposited over the P-type lightly doped region 104 to form an anode metal layer 109, wherein the anode metal layer 109 is connected to the top of the P-type lightly doped region 104, the lightly doped N-well region 107, and the P-type heavily doped region 108, and the thickness of the anode metal layer 109 is 4 μm to 6 μm, for example, may be 4 μm, 5 μm, or 6 μm.
In step S7, referring to fig. 1 and 9, a thinning process is performed on the N-type substrate 101 and a metal is deposited on the back surface of the N-type substrate 101 to form a cathode metal layer 110.
Specifically, as shown in fig. 9, in the present embodiment, a thinning process is performed on the back surface of the N-type substrate 101, and then a metal is deposited on the back surface of the N-type substrate 101 to form a cathode metal layer 110, where the cathode metal layer 110 is connected to the back surface of the N-type substrate 101, and the thickness of the cathode metal layer 110 is 1 μm to 3 μm, for example, may be 1 μm, 2 μm or 3 μm.
Example two
As shown in fig. 10, the present embodiment provides a fast recovery diode structure, including: a cathode metal layer 110; an N-type substrate 101, the N-type substrate 101 being located above the cathode metal layer 110 and connected to the cathode metal layer 110; an N-type drift region 102, the N-type drift region 102 being located above the N-type substrate 101 and connected to the N-type substrate 101; the P-type lightly doped region 104, the P-type lightly doped region 104 is located above the N-type drift region 102 and is connected with the N-type drift region 102; the trench gate 105 comprises a gate 1051 and a gate oxide dielectric layer 1052 wrapping the gate 1051, the trench gate 105 is positioned in the P-type lightly doped region 104, and the depth of the trench gate 105 is smaller than the depth of the P-type lightly doped region 104; lightly doped N-well region 107, lightly doped N-well region 107 being located in the region between two trench gates 105, and the depth of lightly doped N-well region 107 being less than the depth of trench gates 105; the P-type heavily doped region 108 is positioned in the lightly doped N well region 107, the side part of the P-type heavily doped region 108 is connected with the trench gate 105, and the depth of the P-type heavily doped region 108 is smaller than that of the lightly doped N well region 107; the anode metal layer 109 is located above the P-type lightly doped region 104 and is connected to the top of the P-type lightly doped region 104, the lightly doped N-well region 107 and the P-type heavily doped region 108, respectively.
Optionally, the N-type drift region includes a middle-doped N-type drift region and a lightly-doped N-type drift region, wherein the middle-doped N-type drift region is far away from the N-type substrate and a heavily-doped P-pillar region penetrating the middle-doped N-type drift region is formed in the middle-doped N-type drift region.
Optionally, the doping concentration of the medium doped N-type drift region is 1E15cm -3 ～1E17cm -3 The doping concentration of the lightly doped N-type drift region is 1E11cm -3 ～1E14cm -3 The doping concentration of the heavily doped P column region is 1E16cm -3 ～1E18cm -3 。
The doping concentration of the P-type lightly doped region is smaller than that of the P-type heavily doped region.
Optionally, the N-type substrate is heavily doped with a doping concentration of 1E17cm -3 ～1E20cm -3 。
Optionally, the thickness of the gate oxide dielectric layer is
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
In summary, in the fast recovery diode structure of the present invention, the penetrating heavily doped P column region is formed in the middle doped N type drift region, so that the middle doped N type drift region and the adjacent heavily doped P column region form a p+n junction, and when the diode is turned off in a reverse direction, carriers in the middle doped N type drift region are depleted, so that the diode is transformed into a high resistance region, and can bear a higher reverse voltage; when the diode is in forward conduction, the P-type lightly doped region and the heavily doped N-type substrate can both inject carriers into the N-type drift region, so that the doping concentration of the middle doped N-type drift region is quickly recovered, and the lower resistivity is converted back to obtain lower forward voltage drop, thereby achieving the purpose of reducing the loss of the device; through the lightly doped N well region formed between the trench gates and the P-type heavily doped region formed in the lightly doped N well region, a current channel can be formed between the P-type heavily doped region and the P-type lightly doped region, so that when the diode is in a reverse bias state, the grid electrode adsorbs carriers of the lightly doped N well region to the surface of the gate oxide dielectric layer under the action of negative grid voltage, the region, in contact with the trench gates, of the lightly doped N well region is reversely formed into a P-type, the P-type heavily doped region is communicated with the P-type lightly doped region, the doping concentration of a P-type emitter is correspondingly improved, the reverse surge resistance of the device is improved, when the diode is in a conducting state, the region, in contact with the trench gates, of the lightly doped N well region is not reversely formed into a P-type, and the lightly doped N well region is positioned below the P-type heavily doped region, so that the P-type heavily doped region can be blocked, and the distribution state of the carriers can be improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. A fast recovery diode structure, the diode structure comprising:
a cathode metal layer;
the N-type substrate is positioned above the cathode metal layer and connected with the cathode metal layer;
the N-type drift region is positioned above the N-type substrate and connected with the N-type substrate, and comprises a middle-doped N-type drift region and a light-doped N-type drift region, wherein the middle-doped N-type drift region is far away from the N-type substrate, and a heavy-doped P column region penetrating through the middle-doped N-type drift region is formed in the middle-doped N-type drift region;
the P-type lightly doped region is positioned above the N-type drift region and is connected with the N-type drift region;
the trench gate comprises a gate electrode and a gate oxide dielectric layer wrapping the gate electrode, the trench gate is positioned in the P-type lightly doped region, and the depth of the trench gate is smaller than that of the P-type lightly doped region;
the lightly doped N well region is positioned in the region between the two groove gates, and the depth of the lightly doped N well region is smaller than that of the groove gates;
the P-type heavily doped region is positioned in the lightly doped N well region, the side part of the P-type heavily doped region is connected with the trench gate, and the depth of the P-type heavily doped region is smaller than that of the lightly doped N well region;
and the anode metal layer is positioned above the P-type lightly doped region and is respectively connected with the tops of the P-type lightly doped region, the lightly doped N well region and the P-type heavily doped region.
2. The diode structure of claim 1, wherein: the doping concentration of the middle doped N-type drift region is 1E15cm -3 ～1E17cm -3 The doping concentration of the lightly doped N-type drift region is 1E11cm -3 ～1E14cm -3 The sum ofThe doping concentration of the heavily doped P column region is 1E16cm -3 ～1E18cm -3 。
3. The diode structure of claim 1, wherein: the doping concentration of the P-type lightly doped region is smaller than that of the P-type heavily doped region.
4. The diode structure of claim 1, wherein: the N-type substrate is heavily doped and has a doping concentration of 1E17cm -3 ～1E20cm -3 。
5. The diode structure of claim 1, wherein: the thickness of the gate oxide dielectric layer is 500A-2000A.
6. The preparation method of the fast recovery diode is characterized by comprising the following steps of:
providing an N-type substrate, wherein the N-type substrate comprises a front surface and a back surface which are oppositely arranged, an N-type drift region is formed on the front surface of the N-type substrate, the N-type drift region comprises a lightly doped N-type drift region and a medium doped N-type drift region, a heavily doped P column region is formed while the medium doped N-type drift region is formed, and the heavily doped P column region penetrates through the medium doped N-type drift region;
forming a P-type lightly doped region above the N-type drift region;
performing ion implantation on the P-type lightly doped region to form a lightly doped N well region;
etching the P-type lightly doped region to form trench gates on two sides of the lightly doped N well region respectively, wherein the trench gates comprise grid electrodes and gate oxide dielectric layers wrapping the grid electrodes, and the depth of the lightly doped N well region is smaller than that of the trench gates;
performing ion implantation on the lightly doped N well region to form a P-type heavily doped region with the side part connected with the trench gate, wherein the depth of the P-type heavily doped region is smaller than that of the lightly doped N well region;
depositing metal above the P-type lightly doped region to form an anode metal layer, wherein the anode metal layer is positioned above the P-type lightly doped region and is respectively connected with the tops of the P-type lightly doped region, the lightly doped N well region and the P-type heavily doped region;
and carrying out a thinning process on the N-type substrate and depositing metal on the back surface of the N-type substrate to form a cathode metal layer.
7. The method of manufacturing according to claim 6, wherein: the ion implantation dosage of the P-type lightly doped region is 1E13cm -2 The ion implantation dosage of the P-type heavily doped region is 1E14cm -2 ～1E16cm -2 The ion implantation dosage of the lightly doped N well region is 1E14cm -2 ～1E16cm -2 。
8. The method of manufacturing according to claim 6, wherein: the thickness of the anode metal layer is 4-6 mu m, and the thickness of the cathode metal layer is 1-3 mu m.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129798A (en) * | 2008-11-28 | 2010-06-10 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| CN102593154A (en) * | 2012-02-29 | 2012-07-18 | 电子科技大学 | Trench gate diode with P-type buried layer structure |
| CN103441151A (en) * | 2013-08-27 | 2013-12-11 | 无锡市芯茂微电子有限公司 | Low forward voltage drop diode |
| JP2016195271A (en) * | 2016-07-04 | 2016-11-17 | 三菱電機株式会社 | Semiconductor device |
| CN111048594A (en) * | 2019-11-13 | 2020-04-21 | 电子科技大学 | SiC power device integrated with fast recovery diode |
| CN111430453A (en) * | 2020-03-11 | 2020-07-17 | 上海擎茂微电子科技有限公司 | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof |
| CN114300543A (en) * | 2022-03-10 | 2022-04-08 | 安建科技(深圳)有限公司 | Electron extraction type freewheeling diode device and preparation method thereof |
| CN114551589A (en) * | 2022-04-26 | 2022-05-27 | 安建科技(深圳)有限公司 | Power semiconductor device and preparation method thereof |
| CN115312591A (en) * | 2022-10-10 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Fast recovery diode and preparation method thereof |
-
2023
- 2023-02-24 CN CN202310166781.0A patent/CN116190420B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010129798A (en) * | 2008-11-28 | 2010-06-10 | Sanken Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| CN101976687A (en) * | 2010-10-21 | 2011-02-16 | 电子科技大学 | Fast recovery metal oxide semiconductor diode with low power consumption |
| CN102593154A (en) * | 2012-02-29 | 2012-07-18 | 电子科技大学 | Trench gate diode with P-type buried layer structure |
| CN103441151A (en) * | 2013-08-27 | 2013-12-11 | 无锡市芯茂微电子有限公司 | Low forward voltage drop diode |
| JP2016195271A (en) * | 2016-07-04 | 2016-11-17 | 三菱電機株式会社 | Semiconductor device |
| CN111048594A (en) * | 2019-11-13 | 2020-04-21 | 电子科技大学 | SiC power device integrated with fast recovery diode |
| CN111430453A (en) * | 2020-03-11 | 2020-07-17 | 上海擎茂微电子科技有限公司 | RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof |
| CN114300543A (en) * | 2022-03-10 | 2022-04-08 | 安建科技(深圳)有限公司 | Electron extraction type freewheeling diode device and preparation method thereof |
| CN114551589A (en) * | 2022-04-26 | 2022-05-27 | 安建科技(深圳)有限公司 | Power semiconductor device and preparation method thereof |
| CN115312591A (en) * | 2022-10-10 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Fast recovery diode and preparation method thereof |
Non-Patent Citations (1)
| Title |
|---|
| New 1200 V power modules with sophisticated trench gate IGBT and superior soft recovery diode;H. Iwamoto, et al.;IEEE;20020806;28-33 * |
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