CN108010964B - IGBT device and manufacturing method thereof - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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Abstract
An IGBT device and a manufacturing method thereof belong to the field of semiconductor devices. The IGBT device comprises an insulated gate field effect tube and a Schottky barrier diode positioned at a drain region of the insulated gate field effect tube, wherein the Schottky barrier diode and the insulated gate field effect tube are compounded through a shared N-drift region, an emitter junction of the IGBT device is formed in the Schottky barrier diode through Schottky barrier contact, an emitter electrode of the IGBT is positioned on the upper surface of the insulated gate field effect tube, and a collector electrode of the IGBT is positioned on the lower surface of the Schottky barrier diode. The IGBT device provided by the invention is formed by combining an MOS tube with a Schottky barrier diode, and the improved performance is obtained by conducting modulation on a drift region in the MOS by utilizing minority carriers in the Schottky barrier diode.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to an IGBT device and a manufacturing method thereof.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar junction Transistor) and MOSFET (Insulated Gate field effect Transistor, MOS for short). One conventional IGBT device structure is shown in fig. 1, where a P-N junction is added to the drain side of a MOS device 1. Since IGBTs are typically N-channel enhancement type, only P-type region 203 is added relative to MOS devices. The P-type region 203 is typically formed by ion implantation of shallow level impurities such as boron, aluminum, gallium, etc., and annealed to form a heavily doped P-type region 203(P + layer) instead of bit doping.
For an IGBT device, when the channel of MOS device 1 is turned on under gate bias, the resulting current flows through P-type region 203, thereby forward biasing P-type region 203. P-type region 203 injects minority carrier holes through field stop layer 204 into N-drift region 104 of MOS device 1; because of the injection of minority carrier holes, the N-drift region 104 of the MOS device 1 is subjected to conductance modulation, the resistance of the N-drift region 104 is reduced, and the IGBT has the characteristics of large current and low voltage drop. The minority carrier injection ratio gamma of the P-N junction is mainly related to the impurity concentration and concentration gradient on both sides of the P-N junction.
Schottky barrier diodeThe device is formed by metal silicide and silicon which are formed under a certain temperature atmosphere when metal is contacted with semiconductor materials such as silicon materials. The impurity concentration of the silicon material is 1E 15-1E 17cm-3The metal forming the silicide includes Ti, Ni, Pt, Cr, Co, Cu, NixPt (1-x), etc. For an N-type silicon schottky barrier diode, the forward conduction voltage drop is relatively low, around 0.3V, while the voltage drop for a P-N diode is typically around 0.7V. In the schottky barrier diode, when it is turned on in the forward direction, most of the carrier electrons in silicon pass through the barrier region and enter the metal silicide, and since the accumulation of electrons does not occur in the metal silicide, the majority of the electrons (electrons) flowing in directly flow as a drift current. The schottky barrier diode has better high frequency characteristics than the P-N junction diode.
Disclosure of Invention
Based on the defects in the prior art, the invention provides an IGBT device and a preparation method thereof, which aim to improve and even solve the problems of low turn-off speed, low working frequency and high turn-on voltage of the conventional IGBT device.
The invention is realized by the following steps:
in a first aspect of the present invention, an IGBT device is provided.
The IGBT device comprises an insulated gate field effect tube and a Schottky barrier diode positioned at a drain region of the insulated gate field effect tube, wherein the Schottky barrier diode and the insulated gate field effect tube are compounded through a shared N-drift region, and an emitter junction of the IGBT device is formed in the Schottky barrier diode through Schottky barrier contact.
In a second aspect of the present invention, a method of manufacturing the above-described IGBT device is provided.
The method for manufacturing the IGBT device comprises the following steps:
the method comprises the following steps of forming a Schottky barrier diode on the lower surface of a substrate of the MOS device, wherein the method for forming the Schottky barrier diode comprises the following steps:
forming a metal silicide and a collector metal layer on the back of a field stop layer of the MOS device from top to bottom;
wherein the field stop layer is formed by ion implantation on the back of the semiconductor substrate of the MOS device.
The embodiment of the invention has the following beneficial effects:
the IGBT device provided by the embodiment of the invention adopts a composite structure of the field effect transistor and the Schottky barrier diode, and the minority carrier injection ratio gamma of the Schottky barrier diode is reduced along with the reduction of the current density, so that the IGBT device provided by the invention has a faster turn-off speed when the current of the IGBT is reduced, and the working frequency of the device is improved. The forward voltage of the schottky barrier diode is reduced, so that the schottky barrier diode has a lower turn-on voltage compared with a conventional IGBT device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 is a schematic structural diagram of a conventional IGBT device;
fig. 2 is a schematic structural diagram of a first IGBT device with a schottky barrier collector according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a trench formed by etching in an N-type epitaxial wafer according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a gate oxide layer formed by oxidation of the N-type epitaxial wafer shown in FIG. 3;
FIG. 5 is a schematic structural diagram showing a process of removing polysilicon on the surface of the gate oxide layer in FIG. 4 by dry etching and forming gate polysilicon on the surface of the gate oxide layer in the trench;
FIG. 6 is a schematic structural diagram showing that boron implantation is carried out on the N-type epitaxial wafers on two sides of the groove based on the structure of FIG. 5, and a P well region is formed through high-temperature diffusion;
FIG. 7 is a schematic structural diagram of the P well region being implanted with arsenic and boron ions to form a P + layer and an N + source region, respectively, based on FIG. 6;
FIG. 8 is a schematic view of a structure based on the deposition of the oxide insulating layer of FIG. 7;
FIG. 9 is a schematic diagram showing the structure of FIG. 8 etched to expose the P + layer and the side surface of the N + source region;
FIG. 10 is a schematic view showing a structure of depositing aluminum metal to form emitter metal based on FIG. 9;
FIG. 11 is a schematic diagram showing the formation of a field stop layer by phosphorus ion implantation of the N-type epitaxial wafer of FIG. 10;
FIG. 12 shows a schematic of the structure of the field stop layer of FIG. 11 sputtered to form a barrier metal;
FIG. 13 is a schematic view of the structure of FIG. 12 based on the metal layer deposited by sputtering or evaporation and then subjected to silicidation to form metal silicide and collector metal;
fig. 14 shows a schematic structural diagram of a second IGBT device according to an embodiment of the present invention;
fig. 15 shows a schematic structural diagram of a third IGBT device according to an embodiment of the present invention.
Icon: 1-a MOS device; a 2-Schottky barrier diode; 101-emitter metal; 102-P + layer; 103-P well region; 104-N-drift region; 202-collector metal; 203-P type region; 204-N + field stop layer; a 105-N + source region; 106-an insulating layer; 107 a-gate oxide layer; 107 b-gate polysilicon; 107-trenches; 201-metal silicide; 206-barrier metal; 205-insulating barrier layer.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only illustrative of the present invention and should not be construed as limiting the scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.
The following is a detailed description of the IGBT device and the manufacturing method according to the embodiment of the present invention:
in the present embodiment, a new IGBT device is provided that has a schottky barrier collector. The IGBT device is formed by compounding a field effect transistor and a Schottky barrier diode.
Referring to fig. 2, in the present embodiment, the IGBT device includes a MOS device 1 and a schottky barrier diode 2. The semiconductor material constituting the MOS device 1 and the schottky barrier diode 2 may be a silicon material, or may be another semiconductor material such as SiC or GaN. The MOS device 1 may be a planar gate structure or a trench gate structure, and may be a vertical structure or a lateral structure. The metal material forming the schottky barrier diode 2 may be a barrier metal such as Ti, TiN, Ni, Pt, Cr, Co, Cu, NixPt (1-x), and the like. In an alternative example of the present invention, the metal material forming the schottky barrier diode 2 and the semiconductor material (e.g., silicon material) form a metal compound (metal silicide 201).
Wherein the MOS device 1 has therein an N-drift region 104. A trench 107 is formed in the N-drift region 104 from the upper surface, and the trench 107 penetrates into the inside of the N-drift region. Further, the trench 107 may be vertically deep from the upper surface of the N-drift region 104.
A gate oxide layer 107a is provided in the trench 107. A gate oxide layer 107a overlies the trench 107 and contacts the bottom and sidewalls of the trench 107, and the gate oxide layer 107a also overlies the upper surface of the N-drift region 104. Therefore, the gate oxide layer 107a has a trench inner region layer and a trench outer region layer. The gate oxide layer 107a is a thin layer and the thickness of the gate oxide layer 107a is much smaller than the thickness of the N-drift region 104.
A gate polysilicon 107b is formed in the trench 107. The gate polysilicon 107b is in contact with the gate oxide layer 107a, thereby realizing that the gate polysilicon 107b is separated from the N-drift region 104, more specifically the sidewalls and bottom wall of the trench 107, by the gate oxide layer 107 a. Further, the gate polysilicon 107b is not protruded out of the trench 107, i.e., the upper surface of the gate polysilicon 107b is within the trench 107.
P-well regions 103 are formed in the N-drift region 104, and the P-well regions 103 are located on both sides of the trench 107.
The MOS device 1 has an ohmic contact trench extending vertically from one partial region (a part of the trench outer region layer) of the portion of the gate oxide layer 107a located outside the trench 107 to the inside of the MOS device 1 and passing through a part of the N + source region 105 until reaching a part of the upper surface of the P + layer 102.
An insulating layer 106 is formed on the upper surface of the MOS device 1 provided with the ohmic contact trench. The insulating layer 106 contacts the upper surface of the gate polysilicon 107b and contacts the portion of the gate oxide layer 107a remaining outside the trench 107 and after forming the ohmic contact trench.
On the upper surface of the MOS device 1 there is an emitter metal 101. The lower surface of emitter metal 101 is in ohmic contact with a portion of the upper surface of P + layer 102 in P well region 103 and the side surface of N + source region 105. Further, in the emitter metal 101, the gate polysilicon 107b is isolated from the emitter metal 101 by the insulating layer 106 and the gate oxide layer 107 a.
Below the N-drift region 104 is an N + field stop layer 204 with a collector metal 202 below the N + field stop layer 204.
Below the N-drift region 104 of the MOS device 1 there is a schottky barrier diode 2 (schottky barrier diode). In the schottky barrier diode 2, there is a metal silicide 201, an N + field stop layer 204 is provided on the metal silicide 201, and the lower surface of the metal silicide 201 is in contact with a collector metal 202.
In the metal-semiconductor junction of the schottky barrier diode, when the semiconductor material is selected from a silicon semiconductor material, the metal may be adopted as the metal compound. In the present embodiment, the metal-semiconductor junction is formed by contacting the silicon semiconductor material with the metal silicide 201 through the Schottky barrier, and the impurity concentration of the side of the silicon semiconductor material contacting the metal silicide 201 is less than 1E17cm-3To ensure a schottky contact rather than an ohmic contact. In addition, as a more preferable option, the impurity concentration of the silicon semiconductor material on the side in contact with the metal silicide 201 is smaller than the impurity concentration on the side away from the metal silicide 201. Thus, in some examples, the schottky barrierThe diode is formed by Schottky contact between metal silicide and doped semiconductor.
The method for manufacturing the IGBT device with the Schottky barrier collector provided by the embodiment comprises the following steps:
step 1: using an N-type epitaxial wafer (an N-drift region 104 is formed in the final IGBT device), trench etching is performed using an oxide or a photoresist or the like as a mask film to form a trench 107, see fig. 3.
Step 2: a sacrificial oxidation process is performed to remove the etching damage of the trench 107, and then oxidation is performed to form a gate oxide layer 107a, see fig. 4.
And step 3: the gate polysilicon 107b is deposited and doped with phosphorus impurities, and after annealing, the polysilicon on the surface is removed by dry etching, that is, the polysilicon on the upper surface of the N-type epitaxial wafer is removed, and the polysilicon deposited in the trench 107 is remained, as shown in fig. 5.
And 4, step 4: performing boron implantation, and forming a P well region 103 by high temperature diffusion, see fig. 6;
and 5: performing arsenic ion implantation with energy of 120KeV, performing boron ion implantation by photolithography to form N + source region 105 and P + layer 102 in P well region 103, and depositing (depositing) oxide such as TEOS (tetraethoxysilane) to form insulating layer 106, as shown in fig. 7 and 8;
step 6: after annealing, the insulating layer 106 and part of the N + source region 105 are etched and etched by using a photolithography process, and the side surfaces of the P + layer 102 and the N + source region 105 are exposed, as shown in fig. 9;
and 7: depositing metal aluminum containing 1% silicon to form emitter metal 101, see fig. 10;
and 8: and thinning the back of the silicon chip, and removing a damaged layer and a distorted layer generated in the back thinning process by wet etching.
And step 9: performing back implantation on a high-energy phosphorus ion silicon wafer to form an N + field stop layer 204, referring to FIG. 11;
step 10: the barrier metal 206 is sputtered by using platinum or NiPt alloy as a metal source, referring to FIG. 12, then metal layers of Ti, Ni and Ag are deposited by using a sputtering or evaporation process, and the barrier metal 206 is subjected to a silicification reaction by using a vacuum alloying process at 300-550 ℃ to form a metal silicide 201 and a collector metal 202 layer, referring to FIG. 13.
Referring to fig. 2, the IGBT device with a schottky barrier collector according to the embodiment of the present invention is formed by combining a MOS device 1 and a schottky barrier diode 2. The Schottky barrier diode 2 is arranged on the side of the drain region of the MOS device 1, and the N-drift region 104 of the Schottky barrier diode 2 is shared with the N-drift region 104 of the MOS device 1.
The IGBT device provided by the embodiment of the invention has the following working modes:
when the emitter metal 101 of the IGBT device is grounded, the collector metal 202 is applied with a positive voltage, and the gate polysilicon 107b is connected with the positive voltage, the IGBT device is conducted in the forward direction.
When the IGBT device is turned on in the forward direction, a current flows through the schottky barrier diode 2, and the schottky barrier region injects minority carrier holes into the N-drift region 104 through the N + field stop layer 204, and the minority carrier holes perform conductivity modulation on the N-drift region 104, so that the resistance of the N-drift region 104 is reduced.
The current density flowing through the schottky barrier region is increased due to the decrease of the resistance of the N-drift region 104, and as the current density is increased, the current density of minority carrier holes injected into the N-drift region 104 by the schottky barrier diode 2 through the N + field stop layer 204 is increased, so that the device rapidly enters a low-resistance conduction state.
In the on state, a part of the minority carrier holes in the N-drift region 104 are stored without being recombined in time, and most of the minority carrier holes are formed by injecting the schottky barrier diode 2.
When the voltage of the gate polysilicon 107b is reduced to the turn-on voltage, the current of the MOS device 1 is rapidly reduced, and the current flowing through the schottky barrier is also rapidly reduced. Due to the reduction of the density of the current flowing through the schottky barrier, the density of minority carrier holes injected into the N-drift region 104 through the N + field stop layer 204 is also rapidly reduced at the same time, and after the holes stored in the N-drift region 104 disappear by recombination, the IGBT device enters a blocking state.
The conventional IGBT device is composed of a BJT (bipolar junction transistor) and a MOS (insulated gate field effect transistor) in a composite mode, and an emitting junction of the BJT is a P-N junction. In the IGBT device provided by the embodiment of the invention, the emitter junction is realized in a Schottky barrier contact mode.
In a modified example of the present invention, two kinds of IGBT device examples as shown in fig. 14 and 15 are provided. The MOS device 1 in the IGBT device with schottky barrier collector has been described in detail above, and please refer to the above description.
The IGBT device shown in fig. 14 and 15 is mainly different from the IGBT device shown in fig. 2 in the improvement of the schottky barrier diode 2.
For example, in the schottky barrier diode 2 (the silicon semiconductor material and the metal silicide form a metal-semiconductor junction), the contact of the upper surface of the metal silicide 201 with the N + field stop layer 204 is not full contact, and the barrier region area in the schottky barrier diode 2 can be reduced by the above design. This can be achieved by adjusting the shape and size of the metal silicide 201. In such an example, the schottky barrier contact region of the schottky barrier diode 2 may be formed in a shape of a small island, a net, a stripe, or the like.
In some alternative examples, as shown in fig. 14, the metal silicide 201 is structured and dimensioned in combination with the barrier material to contact the N + field stop layer 204 together. In such an example, for example, a blocking region designed in a shape of a small island, a net, a stripe, or the like is also present in the schottky barrier diode.
For example, in the IGBT device shown in fig. 14, the metal silicide 201 is in contact with the N + field stop layer 204 in common with an insulating barrier layer 205 (which may be silicon oxide or the like) forming the barrier region. A collector metal 202 overlies the insulating barrier 205 and the metal suicide 201. The manufacturing process of the IGBT device is substantially the same as that of steps 1 to 10, and mainly a step of forming the insulating barrier layer 205 is added between step 9 and step 10. The method of forming the insulating barrier layer 205 is as follows: after the foregoing step 9 is performed, the insulating barrier layer 205 is deposited by an APCVD process, and then the insulating barrier layer 205 is selectively etched by a photolithography process to form a desired shape, and the method of performing the foregoing step 10 is continued.
In addition, as an alternative, the island-shaped, net-shaped or strip-shaped pores of the barrier layer may be uniformly distributed, or may be non-uniformly distributed, for example, the pores may be distributed according to a certain rule. By providing the blocking layer, the area of the metal silicide 201 in contact with the N + field stop layer 204 is reduced, and the current density flowing through the schottky barrier diode 2 is increased, thereby increasing the injection ratio γ of minority carriers.
In addition, the method for changing the injection ratio γ of the minority carrier may also adopt the metal silicide compounds with different barrier heights, or change the impurity concentration of the N-type silicon in contact with the metal silicide 201, or adopt the combination of the metal silicide 201 with different barrier heights and different impurity concentrations of the N-type silicon to adjust the injection ratio γ of the minority carrier.
Wherein the impurity concentration of the N-type silicon in contact with the metal silicide 201 is changed mainly by making the impurity doping concentration in the N + field stop layer 204 varied rather than uniform. Still further, an alternative approach is: in the N + field stop layer 204, the impurity concentration of a region in contact with the metal silicide 201 is lower than the impurity concentration far from the metal silicide 201.
Some methods of changing the injection ratio γ of minority carriers (minority carriers) are given above only as examples, and in other examples of the present invention, other methods known to the inventors may be adopted for adjustment.
Fig. 15 shows another IGBT device according to the invention, which is an IGBT embodiment of the reverse conducting schottky barrier collector region. This schottky barrier collector IGBT device also includes a MOS device 1 and a schottky barrier diode 2, and shares an N-drift region 104. The structure of the MOS device 1 is as described above. The schottky barrier diode 2 has a metal silicide 201 therein, and the metal silicide 201 is not in contact with the N + field stop layer 204 over the metal silicide 201 in its entire area, but in contact with a part of the N + field stop layer 204. In other words, the entire upper surface and the entire sidewalls of the metal silicide 201 are in contact with only a portion of the N + field stop layer 204. In addition, the collector metal 202 covers a portion of the lower surface of the N + field stop layer 204 and the metal silicide 201.
In the IGBT device shown in fig. 15, the process of forming the metal silicide 201 in contact with part of the N + field stop layer 204 may be performed after the step 9, a selective implantation window is performed by using a photolithography process, and then the energy is 50KeV and the dose is 1E14cm-3The above phosphorus ion implantation is performed by continuing the method of step 10.
Because the phosphorus implantation is performed by high-concentration shallow implantation, the impurity concentration on the surface of the N + field stop layer 204 is more than 1E19cm-3Thereby forming an ohmic contact with the metal silicide 201. It should be noted that the phosphorus ion implantation window may be island-shaped, net-shaped or stripe-shaped, and may be uniformly distributed, or may be non-uniformly distributed, such as being distributed by changing the pore size according to a certain rule.
The collector metal 202 is in partial ohmic contact with the N + field stop layer 204. The IGBT in which a P-N diode D1 is formed between an emitter metal 101 and a collector metal 202 of the IGBT device, and a P-well region 103 and an N-drift region 104 form a reverse conducting schottky barrier collector region is a schottky barrier diode-based reverse conducting IGBT device. The Reverse Conducting type IGBT device may be referred to as Reverse Conducting IGBT (RC-IGBT), short Anode IGBT (SA-IGBT), short collector IGBT, short Anode IGBT, and the like. When the reverse-conducting IGBT device bears pressure reversely, the diode is conducted.
While particular embodiments of the present invention have been illustrated and described, it would be obvious that various other changes and modifications can be made without departing from the spirit and scope of the invention. It is therefore intended to cover in the appended claims all such changes and modifications that are within the scope of this invention.
Claims (6)
1. An IGBT device, characterized in that the IGBT device comprises an insulated gate field effect tube and a Schottky barrier diode positioned at a drain region of the insulated gate field effect tube, the Schottky barrier diode and the insulated gate field effect tube are compounded through a shared N-drift region, an emitting junction of the IGBT device is formed in the Schottky barrier diode through Schottky barrier contact, an emitting electrode of the IGBT is positioned at the upper surface of the insulated gate field effect tube, and a collecting electrode of the IGBT is positioned at the lower surface of the Schottky barrier diode;
the Schottky barrier diode further comprises a metal silicide, an N + field stop layer and an insulating barrier layer, wherein the upper surface of the N + field stop layer is completely contacted with the N-drift region, the whole upper surface and the whole side wall of the metal silicide are contacted with a part of the N + field stop layer, the metal silicide is also contacted with the insulating barrier layer and a collector respectively, and the collector and the field stop layer form ohmic contact.
2. The IGBT device according to claim 1, wherein the semiconductor material in the schottky barrier diode and the semiconductor material in the insulated gate field effect transistor are each independently selected from a silicon material comprising any one of amorphous silicon, single crystal silicon, and polycrystalline silicon, or silicon carbide, or gallium nitride.
3. The IGBT device of claim 1, wherein the insulated gate field effect transistor is a planar gate structure, or a trench gate structure, or a vertical structure, or a lateral structure.
4. The IGBT device of claim 1, wherein in the metal-semiconductor junction of the schottky barrier diode, the schottky contact region is in the shape of a small island, a net, or a stripe.
5. The IGBT device of claim 1, wherein in the metal-semiconductor junction of the schottky barrier diode, the semiconductor material is doped and the concentration of impurities adjacent to the metal side is less than the concentration of impurities away from the metal side.
6. The IGBT device of claim 5, wherein said IGBT device is characterized in thatIn the metal-semiconductor junction of the Schottky barrier diode, the doping concentration of the semiconductor material on the side adjacent to the metal is less than 1017/cm3。
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| CN109671626B (en) * | 2018-12-12 | 2021-09-28 | 吉林华微电子股份有限公司 | IGBT device with negative feedback capacitor and manufacturing method |
| CN111341662B (en) * | 2020-03-04 | 2023-09-29 | 吉林华微电子股份有限公司 | Groove gradient side oxygen structure, preparation method thereof and semiconductor device |
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