CN108010964A - A kind of IGBT device and manufacture method - Google Patents
A kind of IGBT device and manufacture method Download PDFInfo
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- CN108010964A CN108010964A CN201711245096.8A CN201711245096A CN108010964A CN 108010964 A CN108010964 A CN 108010964A CN 201711245096 A CN201711245096 A CN 201711245096A CN 108010964 A CN108010964 A CN 108010964A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 9
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 36
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- 229920005591 polysilicon Polymers 0.000 claims description 18
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
A kind of IGBT device and manufacture method, belong to field of semiconductor devices.IGBT device includes isolated gate FET, the Schottky-barrier diode positioned at isolated gate FET drain region, Schottky-barrier diode and isolated gate FET are combined by shared N drift regions, an emitter junction of IGBT device is formed by Schottky Barrier Contact in Schottky-barrier diode, the emitter of IGBT is located at the upper surface of isolated gate FET, collector is located at the lower surface of Schottky-barrier diode.IGBT device provided by the invention is formed using the structure type of metal-oxide-semiconductor combination Schottky-barrier diode, and conductive modulation is carried out to the drift region in MOS using few son in Schottky-barrier diode, obtains improved performance.
Description
Technical field
The present invention relates to field of semiconductor devices, in particular to a kind of IGBT device and manufacture method.
Background technology
Insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), is (double by BJT
Polar form triode) and MOSFET (insulating gate type field effect tube, abbreviation MOS) compositions compound full-control type voltage driven type power half
Conductor device.A kind of existing conventional IGBT device structure in the drain electrode side of MOS device 1 as shown in Figure 1, increase P-N junction.Cause
IGBT is usually that N-channel is enhanced, so only increasing p type island region 203 relative to MOS device.The formation of p type island region 203 is usual
By shallow level impurity such as boron, aluminium, gallium Plasma inpouring, the 203 (P+ of p type island region for substituting the heavy doping that position is adulterated is formed after annealing
Layer).
For IGBT device, when the raceway groove of MOS device 1 is opened under gate bias, the electric current of formation flows through p type island region 203, from
And to the forward bias of p type island region 203.Minority is injected in p type island region 203 by field stop layer 204 to the N- drift regions 104 of MOS device 1
Carrier hole；Because of the injection in minority carrier hole, conductance modulation is formed to the N- drift regions 104 of MOS device 1, is reduced
The resistance of N- drift regions 104, makes IGBT possess high-current low-voltage drop feature.The Minority carrier injection of P-N junction it is main than γ with
The impurity concentration and concentration gradient of P-N junction both sides are related.
Schottky-barrier diode, is that metal is contacted with semi-conducting material such as silicon materials, is formed under certain temperature atmosphere
A kind of device for being formed of metal silicide and silicon.The impurity concentration of silicon materials is in 1E15-1E17cm-3Scope, forms silication
The metal of thing has Ti, Ni, Pt, Cr, Co, Cu, NixPt (1-x) etc..For N-type Schottky barrier diode, forward conduction pressure
Drop is than relatively low, and in 0.3V or so, and the pressure drop of P-N diode is usually in 0.7V or so.During forward conduction, for Schottky barrier
For diode, the majority carrier electronics in silicon is crossed barrier region and is entered in metal silicide, and in metal silicide not
The accumulation of electronics can be formed, therefore more sub (electronics) that flow into are directly becoming drift current and flow away.Therefore Schottky barrier two
Pole pipe has more preferable high frequency characteristics than P-N junction diode.
The content of the invention
Based on deficiency of the prior art, the present invention proposes a kind of IGBT device and preparation method thereof, to improve, even
Solve the problems, such as that turn-off speed existing for existing IGBT device is slow, working frequency is low, cut-in voltage is high.
What the present invention was realized in：
A kind of the first aspect of the present invention, there is provided IGBT device.
IGBT device includes isolated gate FET, the Schottky-barrier diode positioned at isolated gate FET drain region,
Schottky-barrier diode and isolated gate FET are compound by shared N- drift regions, lead in Schottky-barrier diode
Cross the emitter junction that Schottky Barrier Contact forms IGBT device.
A kind of the second aspect of the present invention, there is provided method for manufacturing above-mentioned IGBT device.
The method for manufacturing above-mentioned IGBT device comprises the following steps：
The substrate lower surface for being included in MOS device forms Schottky-barrier diode, forms Schottky-barrier diode
Method includes：
Metal silicide sum aggregate electrode metal layer is from top to bottom formed at the field stop layer back side of MOS device；
Wherein, field stop layer is formed at the Semiconductor substrate back side of MOS device by ion implanting.
The beneficial effect of the embodiment of the present invention：
IGBT device provided in an embodiment of the present invention uses field-effect tube and Schottky-barrier diode composite construction, and by
In Schottky-barrier diode Minority carrier injection than γ, reduce with the reduction of current density, therefore in the present invention
The IGBT electric currents of offer have faster turn-off speed when declining, so that the working frequency of device is improved.Due to Xiao Te
The forward voltage drop of base barrier diode is low, so having lower cut-in voltage compared with conventional IGBT device.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described.
Fig. 1 is the structure diagram of conventional IGBT device；
Fig. 2 is the IGBT device structure schematic diagram of the first Schottky barrier collector provided in an embodiment of the present invention；
Fig. 3 is the structure diagram for forming groove in the embodiment of the present invention by etching in N-type epitaxial wafer；
Fig. 4 is shown to be aoxidized to form the structure diagram of gate oxide in the N-type epitaxial wafer shown in Fig. 3；
Fig. 5 shows the polysilicon that gate oxide surface in Fig. 4 is removed using dry etching, and gate oxidation in the trench
Layer surface forms the structure diagram of gate polysilicon；
Fig. 6 shows that carrying out boron to the N-type epitaxial wafer of groove both sides based on Fig. 5 is injected into and through High temperature diffusion formation p-well
The structure diagram in area；
Fig. 7 represents that carried out arsenic and boron ion injection respectively to p-well region based on Fig. 6 is shown with the structure for forming P+ layers and N+ source regions
It is intended to；
Fig. 8 is the structure diagram based on Fig. 7 deposited oxide insulating layers；
Fig. 9 shows the structure diagram performed etching to Fig. 8 to expose P+ layers and N+ source regions side surface；
Figure 10 represents to be deposited metallic aluminium based on Fig. 9 to form the structure diagram of emitter metal；
Figure 11 represents that phosphonium ion is carried out to the N-type epitaxial wafer in Figure 10 injects the structure diagram to form a stop layer；
Figure 12 shows the structure diagram for being sputtered to the field stop layer in Figure 11 and forming barrier metal；
Figure 13 is represented based on Figure 12 using sputtering or evaporation deposition metal layer, then carries out silicification reaction, forms metal silication
The structure diagram of thing and collector electrode metal；
Figure 14 shows the structure diagram of second of IGBT device provided in an embodiment of the present invention；
Figure 15 shows the structure diagram of the third IGBT device provided in an embodiment of the present invention.
Icon：1-MOS devices；2- Schottky-barrier diodes；101- emitter metals；102-P+ layers；103-P well regions；
104-N- drift regions；202- collector electrode metals；203-P types area；204-N+ stop layers；105-N+ source regions；106- insulating layers；
107a- gate oxides；107b- gate polysilicons；107- grooves；201- metal silicides；206- barrier metals；205- insulation barriers
Layer.
Embodiment
Embodiment of the present invention is described in detail below in conjunction with embodiment, but those skilled in the art will
Understand, the following example is merely to illustrate the present invention, and is not construed as limiting the scope of the invention.It is not specified in embodiment specific
Condition person, the condition suggested according to normal condition or manufacturer carry out.Reagents or instruments used without specified manufacturer, is
The conventional products that can be obtained by commercially available purchase.
It is specifically described below for the IGBT device and manufacture method of the embodiment of the present invention：
In the present embodiment, there is provided a kind of new IGBT device, this IGBT device have Schottky barrier collector.Institute
The IGBT device stated is combined by field-effect tube and Schottky-barrier diode.
Refering to Fig. 2, in the present embodiment, IGBT device includes MOS device 1 and Schottky-barrier diode 2.Form MOS devices
The semi-conducting material of part 1 and Schottky-barrier diode 2 can be other semiconductor materials such as silicon materials or SiC, GaN
Material.MOS device 1 can be planar gate structure or trench gate structure, can be vertical stratification or transversary.Form Xiao Te
The metal material of base barrier diode 2 can be the barrier metals such as Ti, TiN, Ni, Pt, Cr, Co, Cu, NixPt (1-x).At this
In a kind of optional example of invention, the metal material and semi-conducting material (such as silicon materials) shape of Schottky-barrier diode 2 are formed
Into metallic compound (metal silicide 201).
Wherein, there is N- drift regions 104 in MOS device 1.N- drift regions 104 are inwardly formed groove 107 by upper surface, and
Groove 107 is deeply to the inside of N- drift regions.Further, groove 107 can be by N- drift regions 104 upper surface vertically
It is deeply internal.
There is gate oxide 107a in groove 107.Gate oxide 107a is covered in groove 107, and with the bottom of groove 107
Wall and side wall contact, and gate oxide 107a is also covered in the upper surface of N- drift regions 104.Therefore, gate oxide 107a has
There are region layer and the outer region layer of groove in groove.Gate oxide 107a is a thin layer, and the thickness of gate oxide 107a is much smaller than N-
The thickness of drift region 104.
Formed with gate polysilicon 107b in groove 107.Gate polysilicon 107b is contacted with gate oxide 107a, so as to fulfill grid
The side wall and bottom wall of polysilicon 107b and N- drift regions 104-be more specifically groove 107-by gate oxide 107a intervals
Open.Further, gate polysilicon 107b is not protruded into outside groove 107, i.e. the upper surface of gate polysilicon 107b is in groove
In 107.
N- drift regions 104 have been internally formed p-well region 103, and p-well region 103 is positioned at the both sides of groove 107.
P+ layers 102 and N+ source regions 105 are respectively provided with the p-well region 103 of any side of groove 107.Wherein, N+ source regions
105 whole upper surfaces are located at the part outside groove 107 with gate polysilicon 107b and contact." gate polysilicon 107b is located at groove 107
Outer part " is the region of gate polysilicon 107b and the upper surface of N- drift regions 104.The one of the lower surface of N+ source regions 105
Part and whole upper surfaces of P+ layers 102, another part of the lower surface of N+ source regions 105 and the portion of upper surface of p-well region 103 connect
Touch.
MOS device 1 has Ohmic contact groove, and Ohmic contact groove is located at the portion outside groove 107 from gate oxide 107a
The subregion (part for the outer region layer of groove) divided extends across N+ source regions 105 to 1 internal vertical of MOS device
Part is until reach a part for the upper surface of P+ layers 102.
Insulating layer 106 is formed in the upper surface for being provided with the MOS device 1 of Ohmic contact groove.It is more that insulating layer 106 contacts grid
The upper surface of crystal silicon 107b, and it is outer positioned at groove 107 with gate oxide 107a and remaining after Ohmic contact groove by being formed
Part contact.
There is emitter metal 101 in the upper surface of MOS device 1.In the lower surface of emitter metal 101 and p-well region 103
P+ layers 102 the part of upper surface and the side surface Ohmic contact of N+ source regions 105.Further, in emitter metal 101
In, gate polysilicon 107b is isolated by insulating layer 106 and gate oxide 107a with emitter metal 101.
It is N+ stop layers 204 below N- drift regions 104, there is collector gold below N+ stop layers 204
Belong to 202.
There is Schottky-barrier diode 2 (Schottky-barrier diode) below the N- drift regions 104 of MOS device 1.
There is metal silicide 201 in Schottky-barrier diode 2, be N+ stop layers 204 above metal silicide 201,
The lower surface of metal silicide 201 is contacted with collector electrode metal 202.
In the metal-semiconductor junction of Schottky-barrier diode, when semi-conducting material selects silicon semiconductor material, gold
Category can be adopted as metallic compound.In the present embodiment, metal-semiconductor junction is by silicon semiconductor material and metal silicide
201 by Schottky Barrier Contact formed, and silicon semiconductor material contacted with metal silicide 201 side impurity concentration want
Less than 1E17cm-3, to ensure being Schottky contacts rather than Ohmic contact.In addition, as a kind of preferred selection, silicon half
Conductor material contacts the impurity concentration of side with metal silicide 201, and to be less than the impurity away from 201 side of metal silicide dense
Degree.Therefore, in some instances, Schottky-barrier diode passes through schottky junctions using metal silicide and the semiconductor of doping
Touch and formed.
IGBT device manufacture method provided in this embodiment with Schottky barrier collector comprises the following steps：
Step 1：Using N-type epitaxial wafer (formed with N- drift regions 104 in final IGBT device), using oxide or
Photoresist etc. carries out etching groove as masking film, groove 107 is formed, refering to Fig. 3.
Step 2：The etching injury that sacrificial oxidation process removes groove 107 is carried out, oxidation is then carried out and forms gate oxide
107a, refering to Fig. 4.
Step 3：Carry out the deposition of gate polysilicon 107b and carry out phosphorus impurities doping, table is removed using dry etching after annealing
The polysilicon in face, that is, remove the polysilicon of the phosphorus doping of the upper surface of N-type epitaxial wafer, and retains the phosphorus being deposited in groove 107
DOPOS doped polycrystalline silicon, refering to Fig. 5.
Step 4：Boron injection is carried out, by High temperature diffusion, p-well region 103 is formed, refering to Fig. 6；
Step 5：Carry out energy and carry out photoetching process progress boron ion injection again for the injection of 120KeV arsenic ions with p-well region
N+ source regions 105 and P+ layers 102 are formed in 103, the oxides such as (deposition) TEOS (tetraethoxysilane) is then deposited and forms insulation
Layer 106, refering to Fig. 7 and Fig. 8；
Step 6：After annealing, using photoetching process, photoetching and etching insulating layer 106 and part N+ source regions 105, expose P+ layers
102 and N+ source regions, 105 side surface, refering to Fig. 9；
Step 7：Metallic aluminium of the deposit containing 1% silicon, forms emitter metal 101, refering to Figure 10；
Step 8：Silicon chip back side is thinned, the damaging layer and distortion layer produced during removing thinning back side with wet etching.
Step 9：Injected using high energy phosphonium ion silicon chip back side, N+ stop layers 204 are formed, refering to Figure 11；
Step 10：Metal platinum or NiPt alloy are used as source metal, barrier metal 206 is sputtered, refering to Figure 12, then uses
Sputtering or evaporation technology deposited metal Ti, Ni, Ag, silicon is carried out using 300 DEG C of -550 DEG C of vacuum alloying technology barrier metals 206
Change reaction, 202 layers of metal silicide 201 and collector electrode metal are formed, refering to Figure 13.
Referring to Fig. 2, the IGBT device provided in an embodiment of the present invention with Schottky barrier collector by MOS device 1 with
2 compound composition of Schottky-barrier diode.Wherein, Schottky-barrier diode 2 is in the drain region side of MOS device 1, Schottky gesture
The N- drift regions 104 of diode 2 are built to share with the N- drift regions 104 of MOS device 1.
A kind of operating mode of IGBT device provided in an embodiment of the present invention is as follows：
When IGBT device emitter metal 101 is grounded, collector electrode metal 202 plus positive voltage, gate polysilicon 107b connect positive electricity
Press, then IGBT device forward conduction.
In the case of IGBT device forward conduction, electric current flows through Schottky-barrier diode 2, and Schottky barrier area passes through
For N+ stop layers 204 to 104 injected minority carrier hole of N- drift regions, minority carrier hole carries out N- drift regions 104
Conductance modulation, reduces by 104 resistance of N- drift regions.
Make the current density for flowing through Schottky barrier area increase because 104 resistance of N- drift regions reduces, with current density
Increase, Schottky-barrier diode 2 are close to 104 injected minority carrier hole current of N- drift regions by N+ stop layers 204
Degree increase, and then device rapidly enters low-resistance conducting state.
In the on-state, the minority carrier hole in N- drift regions 104, a part be without in time it is not compound fall and
Store, be largely that Schottky-barrier diode 2 injects the composition just to come.
After gate polysilicon 107b voltages are reduced to cut-in voltage, 1 electric current rapid decrease of MOS device, flows through Schottky gesture
Building electric current also quickly reduces.Due to flowing through the reduction of Schottky barrier current density, N- drifts are injected into by N+ stop layers 204
The minority carrier hole density moved in area 104 is also quick at the same time to be reduced, and the hole that N- drift regions 104 store is disappeared by compound
After mistake, IGBT device enters blocking state.
Conventional IGBT device is by BJT (double pole triode) and MOS (insulating gate type field effect tube) is compound forms, and wherein
The emitter junction of BJT be P-N junction.In IGBT device provided in an embodiment of the present invention, emitter junction uses Schottky Barrier Contact side
Formula is realized.
In the improvement example of the present invention, there is provided two kinds of IGBT device examples as shown in Figure 14 and Figure 15.Wherein, Xiao
MOS device 1 refers to described above in above narration in detail in the IGBT device of special base potential barrier collector.
The main distinction of the IGBT device shown in IGBT device and Fig. 2 shown in Figure 14 and Figure 15 is, Schottky barrier
The improvement of diode 2.
(silicon semiconductor material and metal silicide form metal-partly lead for example, in the Schottky-barrier diode 2
Body knot), making the upper surface of metal silicide 201, to be contacted with N+ stop layers 204 be not Full connected, the design more than,
Can reduce the barrier region area in Schottky-barrier diode 2.This usually can be to metal silicide 201 shape, ruler
It is very little to could be adjusted to realize.In such an example, the Schottky Barrier Contact area of Schottky-barrier diode 2 can be produced
Into shapes such as island shape, netted or bar shapeds.
In some optional examples, as shown in figure 14, the structure snd size of metal silicide 201 are adjusted and combine stop
Material, so as to together be contacted with N+ stop layers 204.In such an example, for example, also existing in Schottky-barrier diode
It is designed to the Resistance of the shapes such as island shape, netted or bar shaped.
For example, in the IGBT device shown in Figure 14, metal silicide 201 and the insulation barrier 205 for forming Resistance
(material can be Si oxide etc.) contacts with N+ stop layers 204 jointly.Collector electrode metal 202 is covered in insulation barrier
205 and metal silicide 201 under.Manufacture craft of IGBT device is roughly the same with abovementioned steps 1~10 in this, mainly
The step of forming insulation barrier 205 is added between step 9 and step 10.The method for forming insulation barrier 205 is as follows：
After foregoing step 9 is implemented, insulation barrier 205 is deposited using APCVD techniques, then insulation is hindered using photoetching process
205 making choice property of barrier etch to form desired shape, after continue to implement the method for foregoing step 10.
In addition, as a kind of alternative scheme, the island shape on above-described barrier layer, netted or cylindrical void can be with
It is uniformly distributed, can not also be uniformly distributed, such as changing pore size according to certain rule is distributed.By setting barrier layer to subtract
Lack the area that metal silicide 201 is contacted with N+ stop layers 204, and then increase the electricity for flowing through Schottky-barrier diode 2
γ is compared in current density, the injection for improving minority carrier.
In addition, the metallic silicon of different barrier heights can also be used by changing method of the injection than γ of few sub- carrier
Compound, or change the impurity concentration of N-type silicon being in contact with metal silicide 201 and be changed, or use different height gesture
The mode that metal silicide 201 is combined from different N-type silicon impurities concentration is built, compares γ to adjust less the injection of sub- carrier.
Wherein, the impurity concentration for the N-type silicon being in contact with metal silicide 201 is changed mainly by making N+ stop layers
Impurity doping concentration in 204 is change rather than uniform.For further, a kind of optional method is：In N+
In the stop layer 204 of field, the impurity concentration in the region being in contact with metal silicide 201 is less than the miscellaneous of remote metal silicide 201
Matter concentration.
It is merely possible to exemplarily give some methods of injection than γ for changing few sub (minority carrier) above,
In other examples of the present invention, it can also be adjusted using other methods known for inventor.
Figure 15 shows another IGBT device in the present invention, this is a kind of inverse conductivity type Schottky barrier collecting zone
The embodiment of IGBT.The IGBT device of this Schottky barrier collector also includes MOS device 1 and Schottky-barrier diode
2, and share N- drift regions 104.1 structure of MOS device therein refers to foregoing teachings.In the Schottky-barrier diode 2
In there is metal silicide 201, and metal silicide 201 is not all of area and the N+ fields end above metal silicide 201
Only layer 204 contacts, but is contacted with part N+ stop layer 204.In other words, whole upper surfaces of metal silicide 201 and complete
Portion's side wall is only contacted with a part for N+ stop layers 204.In addition, N+ 204 Hes of stop layer of 202 covering part of collector electrode metal
The lower surface of metal silicide 201.
In the IGBT device shown in Figure 15, the work of the metal silicide 201 contacted with part N+ stop layer 204 is formed
Process can inject window, then carry out energy and be after the abovementioned steps 9 of implementation using making choice property of photoetching process
50KeV dosage is 1E14cm-3Above phosphonium ion injects, after the method for step 10 that continues to implement realize.
Because carrying out phosphorus injection by the way of high concentration shallow implant, by follow-up vacuum alloying technology, in N+ terminations
204 surface impurity concentration of layer are more than 1E19cm-3, so as to form Ohmic contact with metal silicide 201.It should be pointed out that phosphorus
Ion implanting window can be island shape, netted or bar shape, can be uniformly distributed, can not also be uniformly distributed, such as according to
Certain rule changes pore size and is distributed.
202 part of collector electrode metal and N+ 204 Ohmic contacts of stop layer.IGBT device emitter metal 101 with
Between collector electrode metal 202, p-well region 103 forms P-N diode D1 with N- drift regions 104, and then forms inverse conductivity type Schottky gesture
The IGBT of collecting zone is built, is a kind of inverse conductivity type IGBT device based on Schottky-barrier diode.Inverse conductivity type IGBT device can be with
It can be referred to as Reverse Conducting IGBT (RC-IGBT), Shorted Anode IGBT (SA-IGBT), current collection
Extremely short road IGBT, anode in short circuit IGBT etc..During inverse conductivity type IGBT device reverse pressure-bearing, diode current flow.
Although being illustrated and the invention has been described with specific embodiment, but will be appreciated that without departing substantially from the present invention's
Many other change and modification can be made in the case of spirit and scope.It is, therefore, intended that in the following claims
Including belonging to all such changes and modifications in the scope of the invention.
Claims (10)
1. a kind of IGBT device, it is characterised in that the IGBT device includes isolated gate FET, positioned at the insulated gate field
The Schottky-barrier diode in effect pipe drain region, the Schottky-barrier diode and the isolated gate FET are by sharing
N- drift regions it is compound, form the one of the IGBT device by Schottky Barrier Contact in the Schottky-barrier diode
A emitter junction, the emitter of the IGBT is located at the upper surface of the isolated gate FET, collector is located at Schottky barrier
The lower surface of diode.
2. IGBT device according to claim 1, it is characterised in that the semiconductor material in the Schottky-barrier diode
Semi-conducting material in material, the isolated gate FET separately selects silicon materials, or carborundum, or gallium nitride, institute
Stating silicon materials includes any of non-crystalline silicon, monocrystalline silicon, polysilicon.
3. IGBT device according to claim 1, it is characterised in that the isolated gate FET is planar gate structure,
Or trench gate structure, or vertical stratification, or transversary.
4. IGBT device according to claim 1, it is characterised in that the metal material in the Schottky-barrier diode
It is barrier metal, the barrier metal includes metal simple-substance or metallic compound；
Preferably, the metal simple-substance includes any of Ti, Ni, Pt, Cr, Co, Cu, the metallic compound include TiN,
NixPt(1-x), metal silicide；
It is highly preferred that in the Schottky-barrier diode, metal-semiconductor junction is made of silicon and metallic compound, described
Metallic compound includes metal silicide.
5. IGBT device according to claim 1, it is characterised in that in metal-half of the Schottky-barrier diode
In conductor knot, Schottky contact region is in island shape, netted or bar shaped.
6. IGBT device according to claim 5, it is characterised in that the metal of the Schottky-barrier diode-partly lead
In body knot, barrier layer is formed between collector and semiconductor；
Preferably, the barrier layer extends to the following table with metal in the metal-semiconductor junction of the Schottky-barrier diode
The part contact in face；
It is highly preferred that the barrier layer extend to in the metal-semiconductor junction of the Schottky-barrier diode metal it is upper
The part contact on surface；
Most preferably, the barrier layer is insulating layer, forms the material of the insulating layer and includes Si oxide.
7. IGBT device according to claim 1, it is characterised in that in metal-half of the Schottky-barrier diode
In conductor knot, semi-conducting material be by doping treatment, and the impurity concentration of adjacent metal side be less than it is miscellaneous away from metal side
Matter concentration.
8. IGBT device according to claim 7, it is characterised in that in metal-half of the Schottky-barrier diode
In conductor knot, doping concentration of the semi-conducting material in adjacent metal side is less than 10-17/cm3。
9. IGBT device according to claim 1, it is characterised in that in metal-half of the Schottky-barrier diode
In conductor knot, Schottky contact region is in island shape, netted or bar shaped, and field of the part of the collector with being formed at semiconductor
Stop layer forms Ohmic contact.
A kind of 10. method for making IGBT device, it is characterised in that the substrate lower surface for being included in MOS device forms Schottky
Barrier diode, forming the method for the Schottky-barrier diode includes：
Metal silicide sum aggregate electrode metal layer is from top to bottom formed at the field stop layer back side of the MOS device；
The field stop layer is formed at the Semiconductor substrate back side of the MOS device by ion implanting.
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