CN206574721U - A kind of double trench MOSFET devices of SiC of integrated schottky diode - Google Patents
A kind of double trench MOSFET devices of SiC of integrated schottky diode Download PDFInfo
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Abstract
The utility model discloses a kind of double trench MOSFET devices of SiC of integrated schottky diode, two grooves are provided with the primitive cell structure of the double trench MOSFET device active areas of the SiC, the gate groove at primitive cell structure center and the peripheral source groove of gate groove are provided in respectively；The bottom surrounding of gate groove and source groove has carried out the doping with drift region films of opposite conductivity；The central area of channel bottom in source, is provided with Schottky contacts, forms the Schottky diode being electrically connected with source electrode；Channel bottom surrounding and drift region films of opposite conductivity doped region formation Ohmic contact in source；The depth of two grooves is both greater than the p bases.The application realizes the shielding to mos gate, increases the reliability of grid using source and the double groove structures of grid, and in the bottom surrounding progress and the doping of drift region films of opposite conductivity of gate groove bottom and source groove.The electric field of base can be shielded simultaneously, the break-through of base is prevented；And it is integrated with the MPS Schottky diodes with high surge capacity.
Description
Technical field
The utility model belongs to semiconductor applications, and in particular to a kind of SiC of integrated schottky diode is double groove-shaped
MOSFET element.
Background technology
The U-shaped groove MOSFETs of SiC (UMOSFET) have many advantages, and such as p bases can be eliminated with being epitaxially-formed
The influence that imperfect tape comes during ion implanting formation p bases, with more preferable mos gate quality and channel mobility, and more holds
Channel length easy to control.In addition, the primitive cell structure (elementary cell of composition device active region) of trench MOSFET can be accomplished
Smaller, current density is higher, especially for the expensive price of SiC material, can significantly reduce chip cost.But UMOSFET
There is channel bottom electric field concentration, so that the problem of gate medium poor reliability.As shown in figure 1, being a kind of conventional n-channel
The schematic diagram of UMOSFET primitive cell structures, in the off case, the high pressure being added in drain electrode will be acted on drift layer, groove
The A points of bottom will be place that electric field is most concentrated, and the electric-field intensity in medium is 2-3 times in SiC, causes channel bottom
Gate medium is easily breakdown, poor reliability.
On the other hand, under many applicable cases, such as in full-bridge application, transistor needs one afterflow two of inverse parallel
Pole pipe works together, such as silicon IGBT module conventional at present, and all inverse parallel silicon fast recovery diodes are used as fly-wheel diode.Such as
Fruit is integrated with fly-wheel diode in a device, then the integrated level and reliability of chip are not only increased, while also effective
Reduce chip cost.
Utility model content
For problems of the prior art, the purpose of this utility model is to provide a kind of integrated schottky diode
The double trench MOSFET devices of SiC, it efficiently solves problems of the prior art.
To achieve the above object, the utility model uses following technical scheme：
A kind of double trench MOSFET devices of SiC of integrated schottky diode, the double trench MOSFET devices of the SiC
The primitive cell structure of active area sequentially consists of drain electrode, n+ substrates, cushion, n- drift layers, p bases and n++ layers；In primitive unit cell
Two grooves are provided with structure, the gate groove at primitive cell structure center and the peripheral source ditch of the gate groove are provided in respectively
Groove；The bottom surrounding of the gate groove and source groove has carried out the doping with drift region films of opposite conductivity；In source trench bottom
The central area in portion, is provided with Schottky contacts, forms the Schottky diode being electrically connected with source electrode；In source channel bottom surrounding
With drift region films of opposite conductivity doped region formation Ohmic contact；The depth of two grooves is both greater than the p bases.
Further, the gate groove Xia p+ areas are to suspend, i.e., be not electrically connected with source electrode.
Further, the gate groove Xia p+ areas are electrically connected with source electrode and the p bases.
Further, the doping concentration of the p bases is in 1E15-5E17cm-3Between, the thickness of p bases is 0.2-3 μm.
Further, described n++ layers doping concentration is more than 1E19cm-3, n++ layers of thickness is 0.2-2 μm.
Further, region below the p bases and between the gate groove, the channel bottom doping depth of source groove
Doping concentration is than n- drift floor heights.
Further, the wall doping that the p-type doped region of the channel bottom of the source groove passes through source groove with the p bases
It is electrically connected, i.e. source electrode is also electrically connected with p bases.
A kind of method of the double trench MOSFET devices of SiC for preparing integrated schottky diode, methods described is included such as
Lower step：
1) cushion, n- drift layers, p bases and n++ layers are sequentially prepared on substrate；
2) patterned first mask layer on surface of SiC is done, is deposited with CVD method, and the side of chemical wet etching is then used again
Method formation SiO2Figure；With ICP method etching SiC grooves, source, gate groove are formed；Also knot termination environment and scribe area are entered simultaneously
Row etching；
3) the second mask layer on surface of SiC is done, as the mask being subsequently implanted into, carries out Al ion implantings, in source groove
Side wall and the formation doping of bottom surrounding, the direction of injection is the direction that inclination angle is set perpendicular to wafer direction and band one；Injection
After the completion of remove the second mask layer；
4) the 3rd mask layer on surface of SiC is done, the method that photoetching is used after the completion of deposit is used as the in other region glue
Four mask layers formation covering protection, and in gate groove unglazed photoresist, while also forming the glue of field limiting ring form in knot termination environment
Mask；ICP anisotropic etchings are used, the SiO of gate groove bottom is removed2Medium, and continue to retain the SiO of gate trench sidewall2It is situated between
Matter, protection gate groove area；Al ion implantings, form p+ doping in gate groove bottom；Photoresist and SiO are removed after the completion of injection2
Medium, and carry out RCA cleanings；In one layer of graphite linings of surface deposition, high temperature activation anneal is carried out；Use O2、N2Plasma etching or
Person removes graphite linings with thermal oxidation process；
5) cleaned with RCA and BOE, carry out sacrifice oxidation；One layer of SiO is grown with the method for thermal oxide2, gone with BOE corrosion
Remove；The method growth gate dielectric layer of reusable heat oxidation, again in NO or N after oxidation2O or POCl3Annealed in atmosphere；Formed sediment with CVD method
Product highly doped polysilicon, or undoped polycrystal is first deposited, then form DOPOS doped polycrystalline silicon with the method for injection and annealing；With
Polysilicon fills gate groove, and surface is planarized；With the method formation glue mask of photoetching, the polycrystalline outside gate groove is etched away
Silicon, forms polycrystal grid；
6) deposit isolation passivation layer, removes source groove and the medium of ohmic contact regions with the method for chemical wet etching, retains
Medium on gate polysilicon, formation grid are isolated with source.Metal ohmic contact is deposited in source ohmic contact regions, Europe is overleaf deposited
Nurse contacting metal, carries out rapid thermal annealing in a vacuum or inert atmosphere, forms source, leakage Ohmic contact respectively；
7) with PVD methods deposit schottky metal, the method etched again with photoetching is removed outside source groove and ohmic contact regions
The metal in other regions, then thermal annealing is carried out, the Schottky contacts of source channel bottom intermediate region are formed, it is high simultaneously for periphery
Doping p+ areas can form Ohmic contact；
8) thick electrode metal is done, source electrode is electrically connected with schottky metal, electrode briquetting metal passes through above primitive unit cell
Isolate passivation layer and gate isolation；Do thick electrode metal in the back side；The thick passivation layer of last layer, and windowing are finally done, is exposed
Source, the weld zone of grid voltage block metal.
Further, step 1) in the substrate to be highly doped low-resistance n+ layer, concentration is more than 1E18cm-3, it is described slow
The thickness for rushing layer is 1-2 μm；The concentration of the drift layer is in 1E14-1E17cm-3Between, thickness is more than 5 μm；The p bases
Doping concentration is in 1E15-5E17cm-3Between, thickness is 0.2-3 μm；Described n++ layers concentration is more than 1E19cm-3, thickness is more than
0.2μm。
First mask layer described in further, it is characterised in that step 2) is SiO2, thickness is 2-4 μm, the source, grid
The depth of groove is more than the thickness sum of n++ layers and p bases, is 1-4 μm；The width of gate groove is 0.5-2 μm, the width of source groove
Spend for 2.5-10 μm, use SiO2Mask etching SiC selection is compared more than 3.
Further, step 3) described in doped region concentration be more than 1E18cm-3, surface concentration is more than 1E19cm-3, depth is
More than 0.35 μm.
Further, step 4) in gate groove bottom formed p+ doping concentrations be more than 1E18cm-3, depth is more than 0.35 μ
m；The thickness of the graphite linings is 10-100nm；The annealing temperature of high temperature activation anneal is more than 1600 DEG C, and the time is more than 3 minutes.
Further, step 5) in thermal oxide method growth SiO2Thickness is 10-100nm；The temperature of thermal oxide is
Between 1200 DEG C -1500 DEG C, thermal oxide is in O2Carried out in atmosphere.
Further, step 6) described in isolation passivation layer be using CVD method deposit SiO2Or SiOxNy layers, thickness
More than 0.5 μm；The annealing temperature of rapid thermal annealing is between 900-1100 DEG C, the time is between 1 minute to 15 minutes；Source, leakage
Metal ohmic contact be Ni or Ti/Ni.
Further, step 7) described in schottky metal be Ti, Mo, Ni or Pt；The annealing temperature of thermal annealing is 400-600
DEG C, the time is 5-30 minutes.
Further, step 8) described in thick passivation layer be SiO2、Si3N4Or polyimides.
Further, step 1) described in also have one layer JFET layers between n- drift regions and the p bases, it is described JFET layers
Concentration is less than 1E18cm-3, higher than n- drift region, thickness is equal to p bases to the distance of p+ areas junction depth under gate groove.
The utility model has following advantageous effects：
The application is carried out with floating using source and the double groove structures of grid, and in the bottom surrounding of gate groove bottom and source groove
The doping of area's films of opposite conductivity is moved, the shielding to mos gate is realized, increases the reliability of grid.The electricity of base can be shielded simultaneously
, prevent the break-through of base.Schottky contacts are done in the central area of source channel bottom, are adulterated with periphery films of opposite conductivity
Region forms Ohmic contact, the integrated MPS Schottky diodes with high surge capacity.
Brief description of the drawings
Fig. 1 is the primitive unit cell planar structure schematic diagram of UMOSFET in the prior art；
Fig. 2 is the primitive unit cell planar structure schematic diagram of MOSFET element of the present utility model；
Fig. 3 is that the active area of the utility model embodiment is the device plane schematic diagram of hexagonal primitive unit cell close-packed configuration；
Fig. 4 is the circuit diagram of the utility model MOSFET element；
Fig. 5 is extension material structure schematic diagram in the utility model MOSFET element preparation process；
Fig. 6 is the primitive unit cell planar structure schematic diagram after SiC etching grooves in the utility model MOSFET element preparation process；
Fig. 7 is the primitive unit cell planar structure signal after source groove ion implanting in the utility model MOSFET element preparation process
Figure；
Fig. 8 is the primitive unit cell planar structure signal after gate groove ion implanting in the utility model MOSFET element preparation process
Figure；
Fig. 9 illustrates for the primitive unit cell planar structure formed in the utility model MOSFET element preparation process after polysilicon gate
Figure；
Figure 10 is the primitive unit cell planar structure after formation source, leakage Ohmic contact in the utility model MOSFET element preparation process
Schematic diagram；
Figure 11 shows to form the primitive unit cell planar structure of schottky junctions after touch in the utility model MOSFET element preparation process
It is intended to；
Figure 12 is the primitive unit cell planar structure schematic diagram after the completion of prepared by the utility model MOSFET element.
Embodiment
Below, refer to the attached drawing, is more fully illustrated to the utility model, is shown shown in the drawings of of the present utility model
Example property embodiment.However, the utility model can be presented as a variety of multi-forms, it is not construed as being confined to what is described here
Exemplary embodiment.And these embodiments are to provide, so that the utility model is fully and completely, and will be of the present utility model
Scope fully conveys to one of ordinary skill in the art.
As shown in Fig. 2 the utility model provides a kind of double trench MOSFET devices of the SiC of integrated schottky diode
Part, the primitive cell structure of the double trench MOSFET device active areas of the SiC sequentially consists of drain electrode, n+ substrates, cushion, n-
Drift layer, p bases and n++ layers；Two grooves are provided with primitive cell structure, the grid ditch at primitive cell structure center is provided in respectively
The peripheral source groove of groove and gate groove；The bottom surrounding of gate groove and source groove has been carried out and drift region films of opposite conductivity
Doping, on the one hand can with gate groove bottom doping together with shield grid, source channel bottom electric field, reduce electric field concentrate,
Reliability is provided；On the other hand the insertion pn diode sections of integrated Schottky diode are also served as, possess high antisurge energy
Power；The central area of channel bottom in source, is provided with Schottky contacts, forms the Schottky diode being electrically connected with source electrode；
Source channel bottom surrounding and drift region films of opposite conductivity doped region formation Ohmic contact；The depth of two grooves is both greater than institute
State p bases；The depth of gate groove and source groove can unanimously can also be inconsistent, preferably both depth are consistent, are easy in device
Step etching is formed simultaneously in part manufacturing process.
Grid groove Xia p+ areas are to suspend in one embodiment of the present utility model, i.e., be not electrically connected with source electrode.This practicality
Grid groove Xia p+ areas are electrically connected with source electrode and p bases in another new embodiment, because grid groove is all connection, are passed through
Subregion grid groove also carries out side wall injection, completes p+ with p bases so as to be electrically connected with source electrode, and the grid of this subregion are not
Work again.
The base layer (being p base layers for n-type MOSFET, be identical reason to p-type MOSFET) of device is used
It is epitaxially-formed, therefore with extraordinary quality of materials and point-device thickness and doping concentration, it is high-quality beneficial to making
The mos gate structure of amount.Doping concentration is in 1E15-5E17cm-3Between, according to threshold voltage designs.Base layer thickness is more than 0.2 μ
M, preferably between 0.2-3 μm, too thin easy break-through is too thick to increase channel length and resistance.
N++ layers above p bases are as source conductive layer, and doping concentration is more than 1E19cm-3Between, thickness is more than 0.2 μm,
Preferably between 0.2-2 μm.The too thin easy break-through of Ohmic contact of thickness, it is too thick to increase conducting resistance and the depth of etching groove
And difficulty.
N- layers below p bases as device pressure-resistant drift layer, its doping concentration, thickness according to device design it is pressure-resistant
Ability is determined, design is optimized by being minimized in certain resistance to pressure conducting resistance.Such as 1200V devices, concentration can be with
For 5-8E15cm-3, thickness can be 10-15 μm.Region below p bases between channel bottom doping depth, adulterates dense
Spend the drift layer that can also compare slightly higher, such as can be 1E16-1E17cm-3Between, main purpose is can to reduce electronics warp
Cross after raceway groove preferably to spread to drift layer all directions, reduce conducting resistance.The doping concentration of n+ substrates is more than 1E18cm-3。
The p-type doped region of channel bottom is electrically connected with p base layers by the wall doping of source groove, therefore, source electrode
Also it is electrically connected simultaneously with p bases, it is to avoid parasitic npn-structure.The p of source channel bottom surrounding is doped to high concentration of p-type area, is beneficial to
With metal formation Ohmic contact, it is connected with the Schottky contacts at center, together form the pole of Schottky two of embedded pn diodes
Pipe.
As shown in figure 3, wherein AA ' cross section structure schematic diagrams are Fig. 1.The planar structure of primitive unit cell can for rectangle, bar shaped,
The various forms such as hexagon.Simple be arranged in parallel of primitive unit cell forms the active area of a device, and arrangement mode can be simple
Arrangement, or the form such as solid matter, atomic structural arrangement.Meanwhile, whole device is by active area, knot termination environment and scribe line area
Composition, and grid, source electrode on the active area to each primitive unit cell enters row metal extraction respectively, does corresponding briquetting metal, is beneficial to
The follow-up package application of device.This is known to industry engineer, not indicate that on schematic diagram.
As shown in figure 4, MOSFET constitutes antiparallel circuit structure with Schottky diode, realize in a chip
It is integrated.The power density and reliability of device can be effectively increased, the module of encapsulation or the volume and expense of system is reduced.
It is comparatively the also referred to as first doping and second that n-type doping and the p-type mentioned in the utility model, which are adulterated,
Doping, that is, n-type exchanges equally applicable to device with p-type.
Device architecture is applicable not only to SiC in the utility model, is also equally applicable to Si, GaN, Ga2O3Deng semiconductor material
Material, but preparation method is different.
SiC MOSFET structures of the present utility model, the transistor arrangement controlled available for other MOS, such as IGBT.In MOS
The structure division of control has related structure and principle.
It is double groove-shaped that the utility model additionally provides a kind of SiC for preparing integrated schottky diode of the present utility model
The method of MOSFET element, this method is described in detail by taking n-type (n-channel) SiC MOSFET as an example below.
As shown in figure 5, substrate (or referred to as substrate) is highly doped low-resistance n+ layers, concentration is more than 1E18cm-3.Buffering
The concentration of layer is about 1E18cm-3, about 1-2 μm of thickness, the purpose of cushion is to reduce lattice between substrate and epitaxial layer not
Matching, while the defect of teste substrate is in cushion, it is to avoid defect extends to drift layer.The concentration of drift layer exists
1E14-1E17cm-3Between, thickness is more than 5 μm, undertakes the pressure-resistant function of device, and concentration, thickness optimize according to the rated insulation voltage of device
Depending on design.It is p base layers above drift region, concentration is 1E15-5E17cm-3Between, thickness is more than 0.2 μm, than being preferably
0.2-2μm.There are one layer JFET layers between n- drift regions and p bases in another embodiment, concentration is less than 1E18cm-3, than drift
Qu Genggao is moved, thickness is approximately equal to p bases to the distance of Shan Xia p+ areas junction depth, it is therefore an objective to reduce the interregional electric conductions of this JFET
Resistance.It is n+ areas above p bases, doping concentration is more than 1E19cm-3, thickness is more than 0.2 μm.
As shown in fig. 6, on surface of SiC is done patterned first mask.First mask can be usually SiO2, thickness
The SiO that thickness according to mask demand is subsequently implanted into is consumed when adding etching groove2The sum of thickness, is typically 2-4 μm.With
CVD method is deposited, then again with the methods such as chemical wet etching formation SiO2Figure.With ICP method etching SiC grooves, source, grid are formed
Groove.Also knot termination environment and scribe area are etched simultaneously.The depth of groove is according to the pressure-resistant and electric conduction for designing device
Depending on resistance, be added than n++ area with the thickness of p bases it is slightly deep, usually between 1-4 μm.The width of gate groove preferably exists
Between 0.5-2 μm, the width of source groove is preferably between 2.5-10 μm.Use SiO2Mask etching SiC selection ratios can accomplish 3
More than, therefore will remaining major part SiO after the completion of etching2, it is used as the block mask of next step ion implanting.In addition, using SiO2
Mask etching SiC can obtain low defect, the groove effect of U-shaped bottom, beneficial to the reliability of device.
As shown in fig. 7, doing the second mask, the mask being subsequently implanted into is used as.Xiao Te in the middle of in the groove of mask protection source
Base region and gate groove.Middle schottky area width is typically 1.5-8 μm.Mask can be photoresist, medium etc., excellent
Selection of land can be with photoresist.It is general for photoresist depending on mask thicknesses are according to mask material and the energy of subsequent ion injection
More than 2.5 μm.Al ion implantings are carried out, the doped region concentration that injection is formed is more than 1E18cm-3, surface concentration is more than
1E19cm-3, depth is more than 0.35 μm.The direction of injection is the direction perpendicular to wafer direction and with certain inclination angle.One constant inclination
The direction injection at angle to the side wall of source groove primarily to can carry out effective injection, the highly doped p+ of formation completes source
Pole is electrically connected with p bases.The higher purpose of the implantation concentration on surface be in order to form the surface of more high-dopant concentration, in favor of
It is subsequently formed the Ohmic contact in source channel bottom p+ areas.The second mask is removed after the completion of injection.
As shown in figure 8, in the mask layer of surface deposition the 3rd, it is therefore preferable to medium, such as SiO2.3rd mask is mainly rear
The side wall of gate groove is protected during continuous injection.The method that photoetching is used after the completion of deposit, the 4th mask layer is used as in other region glue
Formed covering protection, and in gate groove unglazed photoresist, while also forming the glue mask of field limiting ring form in knot termination environment.With
ICP anisotropic etchings, remove the SiO of gate groove bottom2Medium, and continue to retain the SiO of gate trench sidewall2Medium, protects grid
Channel region.Al ion implantings, form p+ doping in gate groove bottom, and concentration is more than 1E18cm-3, depth is more than 0.35 μm, preferably
Ground depth is consistent with source channel bottom p+ areas.The junction termination structures of field limiting ring form are also form simultaneously, of the present utility model
In other embodiment can also use other forms junction termination structures, such as injection JTE (knot terminal extension), etch JTE,
JTE and field limiting ring combining form etc..Photoresist and SiO are removed after the completion of injection2Medium, and carry out RCA cleanings.In surface deposition
One layer of graphite linings, thickness is about 10-100nm, carries out high temperature activation anneal, and annealing temperature is more than 1600 DEG C, and the time is more than 3 points
Clock.Use O2、N2Plasma etching removes graphite linings with thermal oxidation process.
As shown in figure 9, being cleaned with RCA and BOE, sacrificial oxidation process is carried out.One layer of SiO is grown with the method for thermal oxide2,
Thickness is about 10-100nm, uses BOE erosion removals.Sacrificial oxidation process can remove defect and the damage that surface etch is brought
Layer.Depending on the method growth gate dielectric layer of reusable heat oxidation, threshold voltage of the thickness according to device, preferably thickness is 40-
80nm.The temperature of thermal oxide is between 1200 DEG C -1500 DEG C, thermal oxide is in O2Carried out in atmosphere, again in NO or N after oxidation2O or
POCl3Etc. annealing in atmosphere, improve MOS interfacial state.Highly doped polysilicon is deposited with CVD method, nothing can also be first deposited and mix
Miscellaneous polycrystal, then adulterated with the method formation of injection and annealing.Gate groove is filled with polysilicon, surface is planarized.
With the method formation glue mask of photoetching, the polysilicon outside gate groove is etched away, polysilicon gate is formed.
As shown in Figure 10, deposit isolation passivation layer, the general method deposit SiO with CVD2Or SiOxNy layers, thickness is preferred
Ground is more than 0.5 μm, removes source groove and the medium of ohmic contact regions with the method for chemical wet etching, retains Jie on gate polysilicon
Matter, formation grid are isolated with source.Metal ohmic contact is deposited in source ohmic contact regions, metal ohmic contact is overleaf deposited,
Carry out rapid thermal annealing under vacuum or inert atmosphere, annealing temperature is between 900-1100 DEG C, the time be 1 minute to 15 minutes it
Between, source, leakage Ohmic contact are formed respectively.Source, leakage metal ohmic contact it is general for Ni, Ti/Ni etc..
As shown in figure 11, schottky metal is deposited with PVD methods.PVD methods can produce the Metal deposition of isotropic,
Beneficial to the Metal deposition of source trenched side-wall.The method etched again with photoetching removes other regions outside source groove and ohmic contact regions
Metal.Schottky metal can be Ti, Mo, Ni, Pt etc..Thermal annealing is carried out again, and such as to Ti schottky metals, annealing temperature is
400-600 DEG C, the time is 5-30 minutes, forms the Schottky contacts of source channel bottom intermediate region, highly doped simultaneously for periphery
Miscellaneous p+ areas can form Ohmic contact.Annealing can improve the performance and uniformity of Schottky contacts.
As shown in figure 12, thick electrode metal is done, encapsulation when being easy to the device to apply.Source is electrically connected with schottky metal
Logical, electrode briquetting metal is above primitive unit cell, by isolating passivation layer and gate isolation.Gate electrode briquetting metal draws in the other end
Go out, as shown in Fig. 3 floor map.Do thick electrode metal in the back side.Finally do the thick passivation layer of last layer, such as SiO2、Si3N4、
Polyimides etc., and windowing, expose source, the weld zone of grid voltage block metal.
It is described above simply to illustrate that the utility model, it is understood that the utility model be not limited to the above implementation
Example, meets the various variants of the utility model thought within protection domain of the present utility model.
Claims (7)
1. a kind of double trench MOSFET devices of SiC of integrated schottky diode, the double trench MOSFET devices of the SiC have
The primitive cell structure of source region sequentially consists of drain electrode, n+ substrates, cushion, n- drift layers, p bases and n++ layers；Its feature exists
In being provided with two grooves in primitive cell structure, the gate groove and the gate groove at primitive cell structure center be provided in respectively
The source groove of periphery；The bottom surrounding of the gate groove and source groove has carried out the doping with drift region films of opposite conductivity；
The central area of channel bottom in source, is provided with Schottky contacts, forms the Schottky diode being electrically connected with source electrode；In Yuan Gou
Trench bottom surrounding and drift region films of opposite conductivity doped region formation Ohmic contact；The depth of two grooves is both greater than the p
Base.
2. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The gate groove Xia p+ areas are to suspend, i.e., be not electrically connected with source electrode.
3. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The gate groove Xia p+ areas are electrically connected with source electrode and the p bases.
4. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The doping concentration of the p bases is in 1E15-5E17cm-3Between, the thickness of p bases is 0.2-3 μm.
5. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
Described n++ layers doping concentration is more than 1E19cm-3, n++ layers of thickness is 0.2-2 μm.
6. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
Described in the doping concentration ratio in the region below the p bases and between the gate groove, the channel bottom doping depth of source groove
N- drift floor heights.
7. the double trench MOSFET devices of the SiC of integrated schottky diode according to claim 1, it is characterised in that
The p-type doped region of the channel bottom of the source groove is electrically connected with the p bases by the wall doping of source groove, i.e.
Source electrode is also electrically connected with p bases.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108198857A (en) * | 2017-12-28 | 2018-06-22 | 北京世纪金光半导体有限公司 | A kind of silicon carbide MOSFET device structure cell of integrated convex block shape Schottky diode |
| CN113497123A (en) * | 2020-04-01 | 2021-10-12 | 成都蓉矽半导体有限公司 | Separated insulated gate bipolar transistor with faster switching speed |
| CN113921400A (en) * | 2021-12-09 | 2022-01-11 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
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2017
- 2017-03-06 CN CN201720210180.5U patent/CN206574721U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108198857A (en) * | 2017-12-28 | 2018-06-22 | 北京世纪金光半导体有限公司 | A kind of silicon carbide MOSFET device structure cell of integrated convex block shape Schottky diode |
| CN113497123A (en) * | 2020-04-01 | 2021-10-12 | 成都蓉矽半导体有限公司 | Separated insulated gate bipolar transistor with faster switching speed |
| CN113921400A (en) * | 2021-12-09 | 2022-01-11 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
| CN113921400B (en) * | 2021-12-09 | 2022-03-25 | 南京华瑞微集成电路有限公司 | Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof |
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