CN113921400A - Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof - Google Patents
Groove gate MOSFET of integrated fin type SBD structure and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
The invention discloses a trench gate MOSFET of an integrated fin type SBD structure and a manufacturing method thereof. Etching the upper side of an epitaxial layer to form an SBD contact platform exposed out of the upper side of the epitaxial layer, depositing a dielectric layer on the upper sides of the epitaxial layer at two sides of the SBD contact platform, and etching the dielectric layer to form a metal deposition area; ohmic contact regions are formed on the upper sides of the first well region and the second well region, SBD contact regions are formed on the upper side and two sides of the SBD contact platform, and the SBD contact regions and the SBD contact platform are matched to form a fin type SBD structure. This send the fin formula SBD structure that forms through SBD contact station and SBD contact area cooperation improves the reverse recovery speed of device, reduces reverse recovery time Trr to make the SBD contact area upgrade to three-dimensional spatial structure by planar structure, the big spoke increases area of contact, thereby when Trr is the same, the chip area that occupies is littleer.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a trench gate MOSFET of an integrated fin type SBD structure and a manufacturing method thereof.
Background
The switching speed of the device is directly influenced due to the existence of a parasitic diode in the structure of the traditional groove type power device. The parasitic diode has a longer reverse recovery time, resulting in a larger dynamic loss of the device. Since the trench type power device is often used in an operating environment such as a DC/DC converter, it is necessary to reduce Trr by parallel SBD.
As shown in fig. 1, the SBD structure is integrated in the cell of the device by means of a split source or a split gate, and these two structures have disadvantages: 1. the SBD structure is introduced into the silicon body in a hole etching mode, so that the voltage resistance and the threshold voltage of the device can be influenced, the contact resistance of the device is increased, and even the avalanche tolerance capability of the device is reduced. 2. In order to achieve a sufficiently small Trr, the area of the contact hole of the SBD structure needs to be increased, and the larger the area is, the smaller the Trr is, so that the contact hole generally needs to occupy about 10% of the chip area, or even more; 3. the process flow is complex, the process control difficulty is high, and the manufacturing cost is high.
Disclosure of Invention
The invention aims to provide a trench gate MOSFET integrating a fin-type SBD structure and a manufacturing method thereof, aiming at the defects in the prior art.
In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a trench gate MOSFET integrated with a fin SBD structure, including:
providing a substrate of a first conductive type, and manufacturing an epitaxial layer on the upper side of the substrate;
etching the upper side of the epitaxial layer to form an SBD contact platform exposed out of the upper side of the epitaxial layer;
etching the epitaxial layers on two sides of the SBD contact platform to form a groove;
growing a gate oxide layer on the inner side of the groove;
forming a polysilicon gate of a first conductive type in the groove;
manufacturing body regions of a second conduction type in the epitaxial layers on two sides of the groove, and manufacturing and forming a first well region of a first conduction type and a second well region of the second conduction type at the upper end of the body regions, wherein the first well region is arranged on two sides of the groove, and the second well region is arranged on two sides of the first well region;
depositing a dielectric layer on the upper sides of the epitaxial layers on the two sides of the SBD contact platform, and etching the dielectric layer to form a metal deposition area;
forming ohmic contact regions on the upper sides of the first well region and the second well region, forming SBD contact regions on the upper side and two sides of the SBD contact platform, and forming a fin type SBD structure by matching the SBD contact regions with the SBD contact platform;
and sputtering a metal layer in the metal deposition area and on the upper sides of the dielectric layer and the fin-type SBD structure, wherein the metal layer is etched to form source metal and grid metal.
Further, the width of SBD contact platform is 0.2um-1.0 um.
Further, the width of the SBD contact platform is smaller than the height of the SBD contact platform.
Further, the height of the SBD contact platform is 2 to 3 times of the width of the SBD contact platform.
Further, the ohmic contact region and the SBD contact region are formed by depositing a titanium layer and a titanium nitride layer in sequence and annealing, wherein the annealing temperature is 800 ℃ and the annealing time is 30 s.
In a second aspect, the invention provides a trench gate MOSFET integrated with a fin-type SBD structure, comprising a substrate of a first conductivity type and an epitaxial layer arranged on the substrate, wherein an SBD contact pad exposed on the epitaxial layer is formed on the epitaxial layer by etching, trenches are formed on the epitaxial layer on both sides of the SBD contact pad by etching, a gate oxide layer is grown on the inner side of each trench, a polysilicon gate of the first conductivity type is formed on the inner side of each trench, a body region of a second conductivity type is formed in the epitaxial layer on both sides of each trench, a first well region of the first conductivity type and a second well region of the second conductivity type are formed at the upper end of each body region, the first well regions are arranged on both sides of each trench, the second well regions are arranged on both sides of the first well region, dielectric layers are deposited on the upper sides of the epitaxial layer on both sides of the SBD contact pad, and metal deposition regions are formed on the dielectric layers by etching, the upper sides of the first well region and the second well region are manufactured to form ohmic contact regions, the upper sides and the two sides of the SBD contact platforms are manufactured to form SBD contact regions, the SBD contact regions and the SBD contact platforms are matched to form fin type SBD structures, metal layers are sputtered in the metal deposition regions and on the upper sides of the dielectric layers and the fin type SBD structures, and the metal layers are etched to form source electrode metal and grid electrode metal.
Further, the width of SBD contact platform is 0.2um-1.0 um.
Further, the width of the SBD contact platform is smaller than the height of the SBD contact platform.
Further, the height of the SBD contact platform is 2 to 3 times of the width of the SBD contact platform.
Further, the ohmic contact region and the SBD contact region are formed by depositing a titanium layer and a titanium nitride layer in sequence and annealing, wherein the annealing temperature is 800 ℃ and the annealing time is 30 s.
Has the advantages that: 1. according to the invention, the epitaxial layer is etched, the exposed SBD contact platform is formed, the SBD contact area is formed by depositing Schottky barrier metal, the reverse recovery speed of the device is improved by the fin-type SBD structure formed by matching the SBD contact platform and the SBD contact area, and the reverse recovery time Trr is reduced;
2. according to the invention, the fin structure is introduced, so that the SBD contact area is upgraded from a planar structure to a three-dimensional structure, the contact area is greatly increased, and therefore, when the Trr is the same, the occupied chip area is smaller;
3. because the SBD structure is manufactured above the groove MOS, the whole structure of the device is not influenced, and the performance of the device can be stable;
4. the process is simple, and can be compatible with the traditional process, and the manufacturing cost can be reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art MOSFET structure;
FIG. 2 is a schematic diagram of a structure after an epitaxial layer is fabricated on a substrate;
FIG. 3 is a schematic diagram of the structure after etching to form SBD contact pads on the epitaxial layer;
FIG. 4 is a schematic diagram of the structure after trenches have been etched in the epitaxial layer;
FIG. 5 is a schematic diagram of the structure after a gate oxide layer is grown in the trench;
fig. 6 is a schematic structural view after a polysilicon gate is fabricated in a trench;
FIG. 7 is a schematic diagram of the structure after the first well region and the second well region are formed in the body region;
FIG. 8 is a schematic diagram of the structure after etching the dielectric layer;
fig. 9 is a schematic structural diagram of a trench gate MOSFET integrated with a fin SBD structure according to an embodiment of the present invention.
Detailed Description
The present invention will be further illustrated with reference to the accompanying drawings and specific examples, which are carried out on the premise of the technical solution of the present invention, and it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
As shown in fig. 2 to 9, an embodiment of the invention provides a method for manufacturing a trench gate MOSFET with an integrated fin SBD structure, including:
referring to fig. 2, a substrate 1 of a first conductivity type is provided, and an epitaxial layer 2 is fabricated on the upper side of the substrate 1. Taking the first conductivity type as N-type and the second conductivity type as P-type as an example, the N-type substrate 1 is doped with arsenic or phosphorus. The resistivity and thickness of the epitaxial layer 2 are determined by different device withstand voltages, typically the thickness of the epitaxial layer 2 is 3-15um and the resistivity of the epitaxial layer 2 is 0.1-1 Ω. cm.
Referring to fig. 3, an SBD contact pad 3 exposed from the upper side of the epitaxial layer 2 is etched on the upper side of the epitaxial layer 2. The width w of the SBD contact pad 3 is preferably 0.2um-1.0um, and the width is smaller than the height h, which is beneficial to improving the leakage. The height h of the SBD contact stage 3 may be set to be generally 2 to 3 times the width w. After the SBD contact platform 3 is formed by etching, impurities on the surface of the SBD contact platform 3 can be removed through oxidation processes such as sacrificial oxidation, the effect of repairing the surface of the.
Referring to fig. 4, trenches 4 are etched into the epitaxial layer 2 on both sides of the SBD contact pad 3. Specifically, a layer of silicon dioxide is deposited on the surface of the epitaxial layer 2 on the two sides of the SBD contact stage 3, the thickness of the silicon dioxide is about 4000 angstroms, and the thickness of the silicon dioxide can be finely adjusted according to the shape of the groove 4. And then, sequentially carrying out groove photoetching and etching to form a groove 4, wherein the depth of the groove 4 is preferably 0.6-2um, the width of the groove 4 is preferably 0.2-1.2um, and the inclination angle of the side wall of the groove 4 is preferably 89 degrees. A sacrificial oxide layer with the thickness of 500-.
Referring to fig. 5, a gate oxide layer 5 is grown inside the trench 4. The thickness of the gate oxide layer 5 is preferably 500-1000 angstroms, the growth temperature of the gate oxide layer 5 is 950-1050 ℃, and the thicker the thickness of the gate oxide layer 5 is, the higher the temperature is required for growth. In addition, when the gate oxide layer 5 grows, the gate oxide layer 5 is also formed on the upper side of the epitaxial layer 2 and the SBD contact platform 3, and the gate oxide layer 5 on the upper side of the epitaxial layer 2 and the SBD contact platform 3 can be etched together with the dielectric layer when the dielectric layer is etched.
Referring to fig. 6, a gate 6 of polysilicon of the first conductivity type is formed within the trench 4. Specifically, the polysilicon gate 6 is formed by polysilicon deposition, photolithography and etching, the thickness of the polysilicon gate 6 is preferably 0.8-1.2um, the doping concentration of the polysilicon gate 6 is preferably 1E19-6E19, and the doping element is preferably phosphorus.
Referring to fig. 7, a body region 7 of the second conductivity type is formed in the epitaxial layer 2 on both sides of the trench 4, and a first well region 8 of the first conductivity type and a second well region 9 of the second conductivity type are formed at the upper end of the body region 7, the first well region 8 is disposed on both sides of the trench 4, and the second well region 9 is disposed on both sides of the first well region 8. Specifically, the body region 7 is formed by a body implantation operation and a body annealing operation, the element implanted by the body implantation operation is preferably boron, the implantation energy is preferably 60KEV-120KEV, and the implantation dose is adjusted according to the requirements of VTH parameters, and is generally about 5E12-1.8E 13. When the body region injection operation is performed, the SBD contact stage 3 needs to be shielded by photoresist to avoid injecting boron into the SBD contact stage 3. The annealing temperature of the body region annealing operation is 1100 ℃, the annealing time is 60min, and double injection can be adopted to improve the uniformity of the doping concentration of the P well. The first well region 8 and the second well region 9 are formed by an implantation operation and an annealing operation, respectively, wherein the element implanted to form the first well region 8 is preferably arsenic, the implantation energy is 60KeV, the annealing temperature is 950 ℃, and the annealing time is 60 min. The elements implanted to form the second well region 9 are preferably boron difluoride and boron, the boron difluoride and boron are implanted in a plurality of times, the implantation dosage is 2E14-5E14, the implantation energy is 30-40KeV, the annealing temperature is 950 ℃, and the annealing time is 30 s.
Referring to fig. 8, a dielectric layer 10 is deposited on the upper side of the epitaxial layer 2 on both sides of the SBD contact stage 3, and a metal deposition region is etched on the dielectric layer. The thickness of the dielectric layer 10 is generally 8000-12000 angstroms, and boron element and phosphorus element in a certain proportion in the dielectric layer 10 absorb movable Na and K ions, thereby improving the reliability of the device.
Referring to fig. 9, ohmic contact regions 11 are formed on the upper sides of the first well region 8 and the second well region 9, SBD contact regions 12 are formed on the upper side and both sides of the SBD contact pad 3, and the SBD contact regions 12 cooperate with the SBD contact pad 3 to form a fin SBD structure. The ohmic contact region 11 and the SBD contact region 12 are formed by depositing a titanium layer and a titanium nitride layer in sequence and annealing, wherein the annealing temperature is 800 ℃ and the annealing time is 30 s.
And sputtering a metal layer in the metal deposition region and on the upper sides of the dielectric layer 10 and the fin-type SBD structure, and etching the metal layer to form a source metal 13 and a gate metal. The metal layer 13 is preferably an aluminum layer, the thickness of which is preferably 4um, and the aluminum can be doped with SiCu in a certain proportion to prevent mutual dissolution of aluminum and silicon.
It is also possible to deposit a passivation layer on the upper side of the device and etch the passivation layer to form Gate and Source opening regions. The passivation layer is preferably a silicon nitride passivation layer, and the thickness of the passivation layer is preferably 7000-12000 angstroms, and the passivation layer can reduce device leakage caused by mobile ions on the surface of the chip. It is also possible to thin it from the underside of the substrate 1 to a residual thickness of around 150um and then to form a back gold layer 14 by evaporation on the underside of the substrate 1, the back gold layer 14 preferably being a Ti-Ni-Ag (titanium-nickel-silver) layer.
Based on the above embodiments, referring to fig. 2 to fig. 9, it can be understood by those skilled in the art that the present invention further provides a trench gate MOSFET with an integrated fin SBD structure, which includes a substrate 1 of a first conductivity type and an epitaxial layer 2 disposed on an upper side of the substrate 1, where the substrate 1 of the first conductivity type is an N-type, and the substrate 1 of the N-type is typically doped with arsenic or phosphorus. The resistivity and thickness of the epitaxial layer 2 are determined by different device withstand voltages, typically the thickness of the epitaxial layer 2 is 3-15um and the resistivity of the epitaxial layer 2 is 0.1-1 Ω. cm. The upper side of the epitaxial layer 2 is etched to form the SBD contact station 3 exposed out of the upper side of the epitaxial layer 2, and the width w of the SBD contact station 3 is smaller than the height h of the SBD contact station, which is beneficial to improving electric leakage. The height h of the SBD contact stage 3 may be set to be generally 2 to 3 times the width w.
A body region 7 of the second conductivity type is formed in the epitaxial layer 2 on both sides of the trench 4, specifically, the body region 7 is formed by a body implantation operation and a body annealing operation, the element implanted by the body implantation operation is preferably boron, the implantation energy is preferably 60KEV-120KEV, and the implantation dose is adjusted according to the requirement of VTH parameters, and is usually about 5E12-1.8E 13. The annealing temperature of the body region annealing operation is 1100 ℃, the annealing time is 60min, and double injection can be adopted to improve the uniformity of the doping concentration of the P well. A first well region 8 of the first conductivity type and a second well region 9 of the second conductivity type are formed at the upper end of the body region 7, wherein the first well region 8 is disposed at two sides of the trench 4, and the second well region 9 is disposed at two sides of the first well region 8. The first well region 8 and the second well region 9 are formed by an implantation operation and an annealing operation, respectively, wherein the element implanted to form the first well region 8 is preferably arsenic, the implantation energy is 60KeV, the annealing temperature is 950 ℃, and the annealing time is 60 min. The elements implanted to form the second well region 9 are preferably boron difluoride and boron, the boron difluoride and boron are implanted in a plurality of times, the implantation dosage is 2E14-5E14, the implantation energy is 30-40KeV, the annealing temperature is 950 ℃, and the annealing time is 30 s.
A dielectric layer 10 is formed on the upper side of the epitaxial layer on the two sides of the SBD contact platform 4 in a deposition mode, the thickness of the dielectric layer 10 is generally 8000-12000 angstroms, and boron elements and phosphorus elements in a certain proportion in the dielectric layer 10 absorb movable Na and K ions, so that the reliability of the device is improved. A metal deposition area is formed on the dielectric layer 10 in an etching mode, an ohmic contact area 11 is formed on the upper sides of the first well area 8 and the second well area 9, an SBD contact area 12 is formed on the upper side and the two sides of the SBD contact platform 3, and the SBD contact area 12 and the SBD contact platform 3 are matched to form a fin type SBD structure. The ohmic contact region 11 and the SBD contact region 12 are formed by depositing a titanium layer and a titanium nitride layer in sequence and performing rapid annealing, wherein the annealing temperature is 800 ℃ and the annealing time is 30 s. And sputtering metal layers in the metal deposition region and on the upper sides of the dielectric layer 10 and the fin-type SBD structure, and etching the metal layers to form a source metal 13 and a gate metal. The metal layer 13 is preferably an aluminum layer, the thickness of which is preferably 4um, and the aluminum can be doped with SiCu in a certain proportion to prevent mutual dissolution of aluminum and silicon.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.
Claims (10)
1. The manufacturing method of the trench gate MOSFET of the integrated fin SBD structure is characterized by comprising the following steps:
providing a substrate of a first conductive type, and manufacturing an epitaxial layer on the upper side of the substrate;
etching the upper side of the epitaxial layer to form an SBD contact platform exposed out of the upper side of the epitaxial layer;
etching the epitaxial layers on two sides of the SBD contact platform to form a groove;
growing a gate oxide layer on the inner side of the groove;
forming a polysilicon gate of a first conductive type in the groove;
manufacturing body regions of a second conduction type in the epitaxial layers on two sides of the groove, and manufacturing and forming a first well region of a first conduction type and a second well region of the second conduction type at the upper end of the body regions, wherein the first well region is arranged on two sides of the groove, and the second well region is arranged on two sides of the first well region;
depositing a dielectric layer on the upper sides of the epitaxial layers on the two sides of the SBD contact platform, and etching the dielectric layer to form a metal deposition area;
forming ohmic contact regions on the upper sides of the first well region and the second well region, forming SBD contact regions on the upper side and two sides of the SBD contact platform, and forming a fin type SBD structure by matching the SBD contact regions with the SBD contact platform;
and sputtering a metal layer in the metal deposition area and on the upper sides of the dielectric layer and the fin-type SBD structure, wherein the metal layer is etched to form source metal and grid metal.
2. The method of claim 1, wherein the width of the SBD contact pad is 0.2um to 1.0 um.
3. The method of claim 1, wherein the SBD contact mesa has a width less than a height.
4. The method of claim 3, wherein the SBD contact mesa has a height of 2 to 3 times its width.
5. The method of claim 1, wherein the ohmic contact region and the SBD contact region are formed by sequentially depositing a titanium layer and a titanium nitride layer and annealing at 800 ℃ for 30 s.
6. The trench gate MOSFET is characterized by comprising a substrate of a first conductive type and an epitaxial layer arranged on the upper side of the substrate, wherein an SBD contact platform exposed out of the upper side of the epitaxial layer is formed on the upper side of the epitaxial layer through etching, trenches are formed on the epitaxial layer on two sides of the SBD contact platform through etching, a gate oxide layer grows on the inner side of each trench, a polysilicon gate of the first conductive type is formed on the inner side of each trench, body regions of a second conductive type are formed in the epitaxial layers on two sides of each trench, a first well region of the first conductive type and a second well region of the second conductive type are formed on the upper ends of the body regions, the first well regions are arranged on two sides of each trench, the second well regions are arranged on two sides of the first well region, dielectric layers are formed on the upper sides of the epitaxial layers on two sides of the SBD contact platform through deposition, and metal deposition regions are formed on the dielectric layers through etching, the upper sides of the first well region and the second well region are manufactured to form ohmic contact regions, the upper sides and the two sides of the SBD contact platforms are manufactured to form SBD contact regions, the SBD contact regions and the SBD contact platforms are matched to form fin type SBD structures, metal layers are sputtered in the metal deposition regions and on the upper sides of the dielectric layers and the fin type SBD structures, and the metal layers are etched to form source electrode metal and grid electrode metal.
7. The trench-gate MOSFET of integrated fin SBD structure of claim 6, wherein the width of the SBD contact mesa is 0.2um-1.0 um.
8. The trench-gate MOSFET of integrated fin SBD structure of claim 6, wherein the width of the SBD contact mesa is less than its height.
9. The trench-gate MOSFET of integrated fin SBD structure of claim 8, wherein the height of the SBD contact mesa is 2 to 3 times its width.
10. The trench-gate MOSFET of the integrated fin-type SBD structure of claim 6, wherein the ohmic contact region and the SBD contact region are formed by sequentially depositing a titanium layer and a titanium nitride layer and annealing at 800 ℃ for 30 s.
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| CN110637374A (en) * | 2017-05-17 | 2019-12-31 | 罗姆股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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| US20140231827A1 (en) * | 2013-02-15 | 2014-08-21 | Denso Corporation | Semiconductor device and manufacturing method thereof |
| CN206574721U (en) * | 2017-03-06 | 2017-10-20 | 北京世纪金光半导体有限公司 | A kind of double trench MOSFET devices of SiC of integrated schottky diode |
| CN110637374A (en) * | 2017-05-17 | 2019-12-31 | 罗姆股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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